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Esp32 s3 Wroom 2 Datasheet En-2902185
Esp32 s3 Wroom 2 Datasheet En-2902185
Datasheet
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VI C AR
2.4 GHz WiFi (802.11 b/g/n) and Bluetooth® 5 (LE) module
Built around ESP32S3R8V SoC, Xtensa® dualcore 32bit LX7 microprocessor
Flash up to 32 MB, 8 MB PSRAM
RE R IN
33 GPIOs, rich set of peripherals
O P
Onboard PCB antenna
SI HI
FO IM
1
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ESP32S3WROOM2
Pre-release v0.6
Espressif Systems
Copyright © 2022
www.espressif.com
1 Module Overview
1 Module Overview
Note:
Check the link or the QR code to make sure that you use the latest version of this document:
https://www.espressif.com/documentation/esp32-s3-wroom-2_datasheet_en.pdf
1.1 Features
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CPU and OnChip Memory • Advertising extensions
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• GPIO, SPI, LCD interface, Camera interface,
• 512 KB SRAM
UART, I2C, I2S, remote control, pulse counter,
• 16 KB SRAM in RTC LED PWM, USB 1.1 OTG, USB Serial/JTAG
• 8 MB PSRAM
IN controller, MCPWM, SDIO host, GDMA, TWAI®
controller (compatible with ISO 11898-1), ADC,
touch sensor, temperature sensor, timers and
WiFi
watchdogs
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• 802.11 b/g/n
Integrated Components on Module
• Bit rate: 802.11n up to 150 Mbps
• 40 MHz crystal oscillator
• A-MPDU and A-MSDU aggregation
• Up to 32 MB octal SPI flash
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• Bluetooth LE: Bluetooth 5, Bluetooth mesh • Operating voltage/Power supply: 3.0 ~ 3.6 V
• Speed: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps • Operating ambient temperature: –40 ~ 65 °C
1.2 Description
ESP32-S3-WROOM-2 is a powerful, generic Wi-Fi + Bluetooth LE MCU module that has a rich set of peripherals.
It provides acceleration for neural network computing and signal processing workloads. It is an ideal choice for a
wide variety of application scenarios related to AI and Artificial Intelligence of Things (AIoT), such as wake word
detection and speech commands recognition, face detection and recognition, smart home, smart appliances,
smart control panel, smart speaker, etc.
ESP32-S3-WROOM-2 comes with a PCB antenna. It has ESP32-S3R8V SoC embedded. A selection of module
variants are available for customers with flash memory of 16/32 MB and PSRAM memory of 8 MB.
Ordering Code Chip Embedded Flash (MB) PSRAM (MB) Dimensions (mm)
ESP32-S3-WROOM-2-N16R8V ESP32-S3R8V 16 8 (Octal SPI)
18 × 25.5 × 3.1
ESP32-S3-WROOM-2-N32R8V ESP32-S3R8V 32 8 (Octal SPI)
At the core of the modules is an ESP32-S3R8V, an Xtensa® 32-bit LX7 CPU that operates at up to 240 MHz.
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You can power off the CPU and make use of the low-power co-processor to constantly monitor the peripherals
for changes or crossing of thresholds.
ESP32-S3R8V integrates a rich set of peripherals including SPI, LCD interface, Camera interface, UART, I2C, I2S,
remote control, pulse counter, LED PWM, USB Serial/JTAG controller, MCPWM, SDIO host, GDMA, TWAI®
controller (compatible with ISO 11898-1), ADC, touch sensor, temperature sensor, timers and watchdogs, as well
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as up to 45 GPIOs. It also includes a full-speed USB 1.1 On-The-Go (OTG) interface to enable USB
communication.
Note:
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* For more information on ESP32-S3, please refer to ESP32-S3 Series Datasheet.
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1.3 Applications
• Generic Low-power IoT Sensor Hub • Smart Building
• Wi-Fi-enabled Toys
• Image Recognition
Contents
1 Module Overview 2
1.1 Features 2
1.2 Description 2
1.3 Applications 3
2 Block Diagram 7
3 Pin Definitions 8
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3.1 Pin Layout 8
3.2 Pin Description 8
3.3 Strapping Pins 10
4 Electrical Characteristics 13
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4.1 Absolute Maximum Ratings 13
4.2 Recommended Operating Conditions 13
4.3 DC Characteristics (3.3 V, 25 °C) 13
4.4
4.5
Current Consumption Characteristics
Wi-Fi RF Characteristics
IN 14
15
4.5.1 Wi-Fi RF Standards 15
4.5.2 Wi-Fi RF Transmitter (TX) Specifications 15
4.5.3 Wi-Fi RF Receiver (RX) Specifications
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16
4.6 Bluetooth LE Radio 17
4.6.1 Bluetooth LE RF Transmitter (TX) Specifications 17
4.6.2 Bluetooth LE RF Receiver (RX) Specifications 19
5 Module Schematics
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22
6 Peripheral Schematics 23
8 Product Handling 26
8.1 Storage Conditions 26
8.2 Electrostatic Discharge (ESD) 26
8.3 Reflow Profile 26
Revision History 28
List of Tables
1 Ordering Information 3
2 Pin Definitions 8
3 JTAG Signal Source Selection 10
4 Strapping Pins 11
5 Parameter Descriptions of Setup and Hold Times for the Strapping Pin 12
6 Absolute Maximum Ratings 13
7 Recommended Operating Conditions 13
8 DC Characteristics (3.3 V, 25 °C) 13
9 Current Consumption Depending on RF Modes 14
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10 Current Consumption Depending on Work Modes 14
11 Wi-Fi RF Standards 15
12 TX Power with Spectral Mask and EVM Meeting 802.11 Standards 15
13 TX EVM Test 15
14 RX Sensitivity 16
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15 Maximum RX Level 17
16 RX Adjacent Channel Rejection 17
17 Bluetooth LE Frequency 17
18
19
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Transmitter Characteristics - Bluetooth LE 1 Mbps
Transmitter Characteristics - Bluetooth LE 2 Mbps
17
18
20 Transmitter Characteristics - Bluetooth LE 125 Kbps 18
21 Transmitter Characteristics - Bluetooth LE 500 Kbps 19
22 Receiver Characteristics - Bluetooth LE 1 Mbps 19
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23 Receiver Characteristics - Bluetooth LE 2 Mbps 20
24 Receiver Characteristics - Bluetooth LE 125 Kbps 20
25 Receiver Characteristics - Bluetooth LE 500 Kbps 21
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List of Figures
1 ESP32-S3-WROOM-2 Block Diagram 7
2 Pin Layout (Top View) 8
3 Setup and Hold Times for the Strapping Pin 12
4 ESP32-S3-WROOM-2 Schematics 22
5 Peripheral Schematics 23
6 ESP32-S3-WROOM-2 Physical Dimensions 24
7 ESP32-S3-WROOM-2 Recommended PCB Land Pattern 25
8 Reflow Profile 26
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2 Block Diagram
ESP32-S3-WROOM-2
40 MHz
Crystal
3V3 Antenna
RF Matching
ESP32-S3R8V
EN GPIOs
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OSPI PSRAM
VDD_SPI
SPIDQS
SPICS0
SPICLK
SPIWP
SPIIO4
SPIIO5
SPIIO6
SPIIO7
SPIHD
SPIQ
SPID
OSPI Flash
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Figure 1: ESP32S3WROOM2 Block Diagram
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3 Pin Definitions
Keepout Zone
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GND 1 40 GND
3V3 2 39 IO1
EN 3 38 IO2
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IO4 4 GND GND GND 37 TXD0
IO5 5 GND
41
GND
36 RXD0
GND
IO6
IO7
6
7
GND GND
IN GND
35
34
IO42
IO41
IO15 8 33 IO40
IO16 9 32 IO39
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IO17 10 31 IO38
IO18 11 30 NC
IO8 12 29 NC
IO19 13 28 NC
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IO20 14 27 IO0
21
22
20
24
23
26
25
16
17
15
18
19
IO11
IO21
IO12
IO3
IO10
IO14
IO46
IO9
IO13
IO47
IO48
IO45
For explanations of pin names and function names, as well as configurations of peripheral pins, please refer to
ESP32-S3 Series Datasheet.
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IO16 9 I/O/T RTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N
IO17 10 I/O/T RTC_GPIO17, GPIO17, U1TXD, ADC2_CH6
IO18 11 I/O/T RTC_GPIO18, GPIO18, U1RXD, ADC2_CH7, CLK_OUT3
IO8 12 I/O/T RTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7, SUBSPICS1
IO19 13 I/O/T RTC_GPIO19, GPIO19, U1RTS, ADC2_CH8, CLK_OUT2, USB_D-
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IO20 14 I/O/T RTC_GPIO20, GPIO20, U1CTS, ADC2_CH9, CLK_OUT1, USB_D+
IO3 15 I/O/T RTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2
IO46 16 I/O/T GPIO46
IO9
IO10
17
18
I/O/T
I/O/T
IN
RTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, FSPIHD, SUBSPIHD
RTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4,
SUBSPICS0
RTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5,
IO11 19 I/O/T
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SUBSPID
RTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6,
IO12 20 I/O/T
SUBSPICLK
RTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7,
IO13 21 I/O/T
SUBSPIQ
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Note:
The content below is excerpted from Section Strapping Pins in ESP32-S3 Series Datasheet. For the strapping pin map-
ping between the chip and modules, please refer to Chapter 5 Module Schematics.
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• GPIO0
• GPIO45
• GPIO46
IN
• GPIO3
Software can read the values of corresponding bits from register “GPIO_STRAPPING”.
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During the chip’s system reset (power-on-reset, RTC watchdog reset, brownout reset, analog super watchdog
reset, and crystal clock glitch detection reset), the latches of the strapping pins sample the voltage level as
strapping bits of “0” or “1”, and hold these bits until the chip is powered down or shut down.
GPIO0, GPIO45 and GPIO46 are connected to the chip’s internal weak pull-up/pull-down during the chip reset.
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Consequently, if they are unconnected or the connected external circuit is high-impedance, the internal weak
pull-up/pull-down will determine the default input level of these strapping pins.
GPIO3 is floating by default. Its strapping value can be configured to determine the source of the JTAG signal
inside the CPU, as shown in Table 4. In this case, the strapping value is controlled by the external circuit that
cannot be in a high impedance state. Table 3 shows more configuration combinations of
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To change the strapping bit values, users can apply the external pull-down/pull-up resistances, or use the host
MCU’s GPIOs to control the voltage level of these pins when powering on ESP32-S3.
VDD_SPI Voltage 1
Pin Default 3.3 V 1.8 V
GPIO45 Pull-down 0 1
Booting Mode 2
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Pin Default SPI Boot Download Boot
GPIO0 Pull-up 1 0
GPIO46 Pull-down Don’t care 0
Enabling/Disabling ROM Messages Print During Booting 3 4
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JTAG Signal Selection
EFUSE_DIS_USB_JTAG = 0, EFUSE_DIS_PAD_JTAG = 0,
Pin Default
GPIO3 N/A
IN
EFUSE_STRAP_JTAG_SEL=1
0: JTAG signal from on-chip JTAG pins
1: JTAG signal from USB Serial/JTAG controller
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Note:
1. The VDD_SPI voltage of the ESP32-S3R8V chip has been set to 1.8 V by eFuse VDD_SPI_TIEH and VDD_SPI_FORCE,
and is no longer controlled by GPIO45.
2. The strapping combination of GPIO46 = 1 and GPIO0 = 0 is invalid and will trigger unexpected behavior.
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3. ROM boot messages can be printed over U0TXD (by default) or GPIO17 (U1TXD), depending on the eFuse bit
EFUSE_UART_PRINT_CHANNEL.
4. When both EFUSE_DIS_USB_SERIAL_JTAG and EFUSE_DIS_USB_OTG are 0, ROM boot messages will be printed
to the USB Serial/JTAG controller. Otherwise, the messages will be printed to UART, controlled by GPIO46 and
EFUSE_UART_PRINT_CONTROL. Specifically, when EFUSE_UART_PRINT_CONTROL value is:
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Figure 3 shows the setup and hold times for the strapping pin before and after the CHIP_PU signal goes high.
Details about the parameters are listed in Table 5.
tSU tHD
VIL_nRST
CHIP_PU
VIH
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Strapping pin
Table 5: Parameter Descriptions of Setup and Hold Times for the Strapping Pin
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Parameter Description Min (ms)
tSU Setup time before CHIP_PU goes from low to high 0
tHD Hold time after CHIP_PU goes high
IN 3
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4 Electrical Characteristics
The values presented in this section are preliminary and may change with the final release of this
datasheet.
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Table 6: Absolute Maximum Ratings
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4.2 Recommended Operating Conditions IN
Table 7: Recommended Operating Conditions
1
VIL Low-level input voltage –0.3 — 0.25 × VDD V
IIH High-level input current — — 50 nA
IIL Low-level input current — — 50 nA
2 1
VOH High-level output voltage 0.8 × VDD — — V
2 1
VOL Low-level output voltage — — 0.1 × VDD V
1
High-level source current (VDD = 3.3 V, VOH >=
IOH — 40 — mA
2.64 V, PAD_DRIVER = 3)
Low-level sink current (VDD1 = 3.3 V, VOL =
IOL — 28 — mA
0.495 V, PAD_DRIVER = 3)
RP U Internal weak pull-up resistor — 45 — kΩ
RP D Internal weak pull-down resistor — 45 — kΩ
Cont’d on next page
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With the use of advanced power-management technologies, the module can switch between different power
modes. For details on different power modes, please refer to Section Low Power Management
in ESP32-S3 Series Datasheet.
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Work mode Description Peak (mA)
802.11b, 1 Mbps, @20.5 dBm 355
802.11g, 54 Mbps, @18 dBm 297
Name Description
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Center frequency range of operating channel 2412 ~ 2484 MHz
Wi-Fi wireless standard IEEE 802.11b/g/n
11b: 1, 2, 5.5 and 11 Mbps
20 MHz 11g: 6, 9, 12, 18, 24, 36, 48, 54 Mbps
Data rate
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11n: MCS0-7, 72.2 Mbps (Max)
40 MHz 11n: MCS0-7, 150 Mbps (Max)
Antenna type PCB antenna
1
Device should operate in the center frequency range allocated by regional regulatory authorities. Target
center frequency range is configurable by software.
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4.5.2 WiFi RF Transmitter (TX) Specifications
Target TX power is configurable based on device or certification requirements. The default characteristics are
provided in Table 12.
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Table 12: TX Power with Spectral Mask and EVM Meeting 802.11 Standards
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Min Typ Max
Rate
(dBm) (dBm) (dBm)
802.11b, 1 Mbps — –98.2 —
802.11b, 2 Mbps — –95.6 —
802.11b, 5.5 Mbps — –92.8 —
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802.11b, 11 Mbps — –88.5 —
802.11g, 6 Mbps — –93.0 —
802.11g, 9 Mbps — –92.0 —
802.11g, 12 Mbps
802.11g, 18 Mbps
IN —
—
–90.8
–88.5
—
—
802.11g, 24 Mbps — –85.5 —
802.11g, 36 Mbps — –82.2 —
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802.11g, 48 Mbps — –78.0 —
802.11g, 54 Mbps — –76.2 —
802.11n, HT20, MCS 0 — –93.0 —
802.11n, HT20, MCS 1 — –90.6 —
802.11n, HT20, MCS 2 — –88.4 —
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802.11n, HT40, MCS 7 — 0 —
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802.11b, 1 Mbps — 35 —
802.11b, 11 Mbps IN — 35 —
802.11g, 6 Mbps — 31 —
802.11g, 54 Mbps — 14 —
802.11n, HT20, MCS 0 — 31 —
802.11n, HT20, MCS 7 — 13 —
802.11n, HT40, MCS 0 — 19 —
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802.11n, HT40, MCS 7 — 8 —
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Table 19: Transmitter Characteristics Bluetooth LE 2 Mbps
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— 2.50 — kHz
Max |f0 − fn | — 2.00 — kHz
Carrier frequency offset and drift
Max |fn − fn−5 | — 1.40 — kHz
|f1 − f0 |
∆ f 1avg
IN —
—
1.00
499.00
—
—
kHz
kHz
Min ∆ f 2max (for at least
Modulation characteristics — 416.00 — kHz
99.9% of all ∆ f 2max )
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∆ f 2avg /∆ f 1avg — 0.89 — —
±4 MHz offset — –42.00 — dBm
In-band spurious emissions ±5 MHz offset — –44.00 — dBm
>±5 MHz offset — –47.00 — dBm
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99.9% of all ∆ f 2max )
±2 MHz offset — –37.00 — dBm
In-band spurious emissions ±3 MHz offset — –42.00 — dBm
>±3 MHz offset — –44.00 — dBm
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Table 22: Receiver Characteristics Bluetooth LE 1 Mbps
Parameter
Sensitivity @30.8% PER —
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Description Min
—
Typ
–96.5
Max
—
Unit
dBm
Maximum received signal @30.8% PER — — 8 — dBm
Co-channel C/I F = F0 MHz — 9 — dB
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F = F0 + 1 MHz — –3 — dB
F = F0 – 1 MHz — –3 — dB
F = F0 + 2 MHz — –28 — dB
F = F0 – 2 MHz — –30 — dB
Adjacent channel selectivity C/I
F = F0 + 3 MHz — –31 — dB
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F = F0 – 3 MHz — –33 — dB
F > F0 + 3 MHz — –32 — dB
F > F0 – 3 MHz — –36 — dB
Image frequency — — –32 — dB
F = Fimage + 1 MHz — –39 — dB
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F = F0 – 6 MHz — –37 — dB
F > F0 + 6 MHz — –40 — dB
F > F0 – 6 MHz — –40 — dB
Image frequency — — –31 — dB
F = Fimage + 2 MHz — –37 — dB
Adjacent channel to image frequency
F = Fimage – 2 MHz — –8 — dB
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30 MHz ~ 2000 MHz — –15 — dBm
2003 MHz ~ 2399 MHz — –19 — dBm
Out-of-band blocking performance
2484 MHz ~ 2997 MHz — –15 — dBm
Intermodulation —
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3000 MHz ~ 12.75 GHz —
—
–6
–29
—
—
dBm
dBm
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Table 24: Receiver Characteristics Bluetooth LE 125 Kbps
F = F0 + 3 MHz — –35 — dB
F = F0 – 3 MHz — –45 — dB
F > F0 + 3 MHz — –35 — dB
F > F0 – 3 MHz — –48 — dB
Image frequency — — –35 — dB
F = Fimage + 1 MHz — –49 — dB
Adjacent channel to image frequency
F = Fimage – 1 MHz — –32 — dB
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F = F0 – 3 MHz — –38 — dB
F > F0 + 3 MHz — –37 — dB
F > F0 – 3 MHz — –41 — dB
Image frequency — — –37 — dB
F = Fimage + 1 MHz — –44 — dB
Adjacent channel to image frequency
F = Fimage – 1 MHz — –28 — dB
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IN
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5 Module Schematics
5 Module Schematics
This is the reference design of the module.
5 4 3 2 1
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GND
GND GND
3
Y1
GND
GND XOUT
C1 C4
D D
VDD33 VDD33 GND GND
XIN
TBD TBD
U3 ESP32-S3-WROOM-2
41
2
1 EPAD 40
The values of C1 and C4 vary with GND GND
R1 2 39 GPIO1
the selection of the crystal. CHIP_PU 3 3V3 IO1 38 GPIO2
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GND 10K(NC) GPIO4 4 EN IO2 37 U0TXD
The value of R4 varies with the actual 40MHz(±10ppm) GPIO5 5 IO4 TXD0 36 U0RXD
VDD33 6 IO5 RXD0 35
PCB board. GPIO46 D1 GPIO6
IO6 IO42
GPIO42
GPIO45 ESD GPIO7 7 34 GPIO41
U0RXD GPIO15 8 IO7 IO41 33 GPIO40
R3 499 U0TXD GPIO16 9 IO15 IO40 32 GPIO39
C3 C2 GPIO42 GPIO17 10 IO16 IO39 31 GPIO38
IO17 IO38
Submit Documentation Feedback
0
GPIO41 GPIO18 11 30
1uF 10nF GPIO40 GND GPIO8 12 IO18 NC 29
GPIO39 GPIO19 13 IO8 NC 28
VDD33 GND GPIO38 GPIO20 14 IO19 NC 27 GPIO0
IO20 IO0
R4
GND GND
L1 2.0nH(0.1nH)
IO46
IO10
IO11
IO12
IO13
IO14
IO21
IO47
IO48
IO45
IO3
IO9
C C10 C
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C6 C7 C8 C9 VDD33
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
0.1uF
15
16
17
18
19
20
21
22
23
24
25
26
10uF 1uF 0.1uF 0.1uF
GND
VDDA
VDDA
XTAL_P
XTAL_N
GPIO46
GPIO45
U0RXD
U0TXD
MTMS
MTDO
MTCK
GPIO38
MTDI
VDD3P3_CPU
22
GND
GPIO46
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO21
GPIO47
GPIO48
GPIO45
GPIO3
GPIO9
GND GND GND GND
ANT1
1 RF_ANT L2 TBD LNA_IN 1 42 R5 0 SPI_DQS
2 2 LNA_IN GPIO37 41 R6 0 SPI_IO7
3 VDD3P3 GPIO36 40 R7 0 SPI_IO6
L3 C11 C12
CHIP_PU VDD3P3 GPIO35 SPI_IO5
ESP32-S3-WROOM-2(pin-out)
PCB_ANT 4 39 R8 0
TBD TBD TBD GPIO0 5 CHIP_PU GPIO34 38 R9 0 SPI_IO4
GPIO1 6 GPIO0 GPIO33 37 GPIO47 VDD_SPI
GPIO2 7 GPIO1 SPICLK_P 36 GPIO48
IN
GND GND GND GPIO3 8 GPIO2 SPICLK_N 35 R16 0 SPI_D
GPIO4 9 GPIO3 SPID 34 R15 0 SPI_Q R11
C16
GPIO5 10 GPIO4 SPIQ 33 R10 0 SPI_CLK
GPIO6 11 GPIO5 SPICLK 32 SPI_CS0 10K VDD_SPI
TBD
GPIO7 12 GPIO6 SPICS0 31 R14 0 SPI_WP
GPIO8 13 GPIO7 SPIWP 30 R13 0 SPI_HD A4 B4
B B
GND GPIO9 14 GPIO8 SPIHD 29 A5 RESET# VCC D1
VDD3P3_RTC
C3 E4
SPI_CS0 C2 DQS VCC
The values of L3, C16, C11, L2 and C12 SPI_CLK CS#
C14 VDD_SPI B2 A2
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21 C13 R12
SPICS1
vary with the actual PCB board. SPI_D D3 SCLK NC1 A3
ESP32-S3-WROOM-2 Datasheet v0.6
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SPI_WP C4 SO(IO1) NC3 B5
U1 ESP32-S3R8V SPI_HD D4 IO2 NC4 C5
15
16
17
18
19
20
21
22
23
24
25
26
27
28
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0.1uF GND
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GND
A A
6 Peripheral Schematics
This is the typical application circuit of the module connected with peripheral components (for example, power
supply, antenna, reset button, JTAG interface, and UART interface).
7 34 IO41 TDI 2
IO7 IO41 2
1
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X1 R3 0(NC) IO15 8 33 IO40 TDO 3
R5 0(NC) IO16 9 IO15 IO40 32 IO39 TCK 4 3
32.768KHz(NC) IO16 IO39 4
IO17 10 31 IO38
NC
2
IO10
IO11
IO12
IO13
IO14
IO21
IO47
IO48
IO45
1 USB_D+ IO3
IO9
2 R4 0
2 SW1
USB OTG C6 C5 NC: No component. U1 R7 0 EN
A
15
16
17
18
19
20
21
22
23
24
25
26
TBD TBD C8 0.1uF
IO46
IO10
IO11
IO12
IO13
IO14
IO21
IO47
IO48
IO45
IO3
IO9
GNDGND GND
IN
Figure 5: Peripheral Schematics
• Soldering the EPAD to the ground of the base board is not a must, however, it can optimize thermal
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performance. If you choose to solder it, please apply the correct amount of soldering paste.
• To ensure that the power supply to the ESP32-S3 chip is stable during power-up, it is advised to add an
RC delay circuit at the EN pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ and
C = 1 µF. However, specific parameters should be adjusted based on the power-up timing of the module
and the power-up and reset sequence timing of the chip. For ESP32-S3’s power-up and reset sequence
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timing diagram, please refer to Section Power Scheme in ESP32-S3 Series Datasheet.
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5 4 3 2
Unit: mm
18±0.15 3.1±0.15
0.8
6
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1
Ø0
.5 0.5
25.5±0.15
40 x 0.9
40 x Ø0.55
4
16.51
1
17.6
1.27
40 x 0.9
12.66
7.64
1.05
15.8
1.5
A
13.97 1.27 2.015
40 x 0.45 1 40 x 0.85
Top View
IN Side View Bottom View
Unit: mm
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18±0.15 3.2±0.15
.5 2.49 0.8
Ø0
1
11.5 0.5
40 x 0.9
PR
2.46
40 x Ø0.55
4
19.2±0.15
1
1.27
15.8 4
16.51
40 x 0.9
12.66
13.2
17.6
7.64
1.05
1.5
Unit: mm
Via for thermal pad
Copper
18
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7.49
Antenna Area
6
40 x1.5
1 1 40
0.5
A
40 x0.9
25.5
4
16.51
IN 1
1.27
12.66
7.64
1.5
0.5
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15 26
0.5 1.27
2.015 2.015
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17.5
8 Product Handling
After unpacking, the module must be soldered within 168 hours with the factory conditions 25±5 °C and
/60%RH. If the above conditions are not met, the module needs to be baked.
RY
• Human body model (HBM): ±2000 V
• Charged-device model (CDM): ±500 V
A
Temperature (℃)
IN
Peak Temp.
235 ~ 250 ℃
IM
250
Preheating zone Reflow zone Cooling zone
150 ~ 200 ℃ 60 ~ 120 s 217 ℃ 60 ~ 90 s –1 ~ –5 ℃/s
217
200
Soldering time
> 30 s
EL
Ramp-up zone
1 ~ 3 ℃/s
100
50
PR
25
Time (sec.)
0
0 50 100 150 200 250
RY
Developer Zone
• ESP-IDF and other development frameworks on GitHub.
http://github.com/espressif
• ESP32 BBS Forum – Engineer-to-Engineer (E2E) Community for Espressif products where you can post questions,
share knowledge, explore ideas, and help solve problems with fellow engineers.
A
http://esp32.com/
• The ESP Journal – Best Practices, Articles, and Notes from Espressif folks.
http://blog.espressif.com/
IN
• See the tabs SDKs and Demos, Apps, Tools, AT Firmware.
http://espressif.com/en/support/download/sdks-demos
Products
IM
• ESP32-S3 Series SoCs – Browse through all ESP32-S3 SoCs.
http://espressif.com/en/products/socs?id=ESP32-S3
• ESP32-S3 Series Modules – Browse through all ESP32-S3-based modules.
http://espressif.com/en/products/modules?id=ESP32-S3
EL
Contact Us
PR
• See the tabs Sales Questions, Technical Enquiries, Circuit Schematic & PCB Design Review, Get Samples
(Online stores), Become Our Supplier, Comments & Suggestions.
http://espressif.com/en/contact-us/sales-questions
Revision History
A RY
IN
IM
EL
PR
Authorized Distributor
Espressif:
ESP32-S3-WROOM-2-N16R8V ESP32-S3-WROOM-2-N32R8V