wp512 Accel Crypto

White Paper: Zynq UltraScale+ MPSoC
WP512 (v1.0) May 21, 2019
Accelerating Cryptographic
Performance on the
Zynq UltraScale+ MPSoC
The Zynq® UltraScale+™ MPSoC’s embedded cryptographic

accelerator enables system architects to greatly increase
cryptographic performance—by as much as 10,000% or
more—compared to software-only solutions.
ABSTRACT
The Zynq UltraScale+ MPSoC features embedded cryptographic cores[Ref 1]
for AES-GCM-256 bit, SHA-3/384, and RSA, as well as Arm® v8 cryptographic
extensions[Ref 2] within the Arm Cortex®-A53 processor, providing
accelerated cryptographic performance.
The performance of the embedded cryptographic accelerators is described
under two software architectures, running on a real-time operating system
(RTOS) as well as in user space on Linux. In each scenario, the cryptographic
accelerator’s performance is compared to using a software-only cryptographic
solution. These performance measurements show how system architects can
maximize cryptographic performance depending on their needs.
© Copyright 2017–2019 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, UltraScale, Versal, Virtex, Vivado, Zynq, and other designated brands included herein
are trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, Arm, Arm1176JZ-S, CoreSight, Cortex, and PrimeCell are trademarks of Arm in
the EU and other countries. All other trademarks are the property of their respective owners.
WP512 (v1.0) May 21, 2019 www.xilinx.com 1

Accelerating Cryptographic Performance on the Zynq UltraScale+ MPSoC
Introduction
This white paper illustrates:
• The performance of software running on the Arm Cortex-A53 processor, leveraging the built-in
cryptographic accelerators in the Zynq UltraScale+ MPSoC’s Configuration Security Unit (CSU)
• The performance of the equivalent software algorithm running on the Arm Cortex-A53
processor, but leveraging the Arm v8 cryptographic extensions
Both results are compared to the native Arm Cortex-A53 software solution.
The Zynq UltraScale+ MPSoC accelerators located in the CSU contain the embedded cryptographic
cores for AES-GCM 256-bit encryption and decryption, SHA-3/384 hashing, and both public and
private RSA operations with a key size of up to 4,096 bits. Although the default clock for the CSU is
the Zynq UltraScale+ MPSoC's internal system oscillator running at 180MHz[Ref 1], the clock was
changed for these tests to run off the low power domain's phase-locked loop (PLL), set at 375MHz,
to achieve better performance. The cryptographic extensions available in the Arm v8 core
accelerate AES, SHA-1, SHA-2, and CRC-32 operations, but they do not support acceleration of any
RSA or SHA-3 operations.
Performance measurements for all tests were run on the Arm Cortex-A53 processor in the Zynq
UltraScale+ MPSoC, and utilized the wolfSSL[Ref 3] built-in benchmarking software version 3.12.0
running out of external dual data rate (DDR) memory. WolfSSL is able to leverage a range of
hardware for cryptographic functions during cryptographic performance measurements. On the
Zynq UltraScale+ MPSoC, this includes the embedded cryptographic core, Arm v8 cryptographic
extensions, and software-only algorithms. Data sets of 16 bytes up to 15,888 bytes were used to
measure the performance of the AES-GCM 256-bit and SHA3/384 cryptographic algorithms, while
RSA-2048 and RSA-4096 were used to measure RSA performance.
wolfSSL on FreeRTOS
WolfSSL version 3.12.0 was ported to FreeRTOS on Xilinx SDK 2017.1 for the Zynq UltraScale+
MPSoC to benchmark the performance of the software-only solution, Arm v8 cryptographic
extensions, and the Zynq UltraScale+ MPSoC’s embedded cryptographic core for the AES-GCM
256-bit, SHA3/384, RSA-2048, and RSA-4096 algorithms. CSU DMA caching and endian byte-
swapping was disabled in the XilSecure libraries[Ref 4] for the wolfSSL FreeRTOS port to maximize
the embedded cryptographic performance. Data block sizes of 16 bytes, 528 bytes, 1,024 bytes,
4,112 bytes, 7,696 bytes, and 15,888 bytes were used to measure the throughput of the AES-GCM
256-bit and SHA3/384 algorithms. RSA-2048 and RSA-4096 public and private operations were
performed to measure the average amount of time needed for each operation. For the RSA
operations, the pre-calculated exponential value was not used.

Results
Table 1 shows the results of AES-GCM 256-bit encryption running the wolfSSL benchmarks under
FreeRTOS. This table highlights in bold the fastest performing cryptographic extension and shows
that the Arm v8 cryptographic extensions outperform the Zynq UltraScale+ MPSoC’s embedded
cryptographic core for data blocks of less than or equal to 1,024 bytes, while the MPSoC’s crypto
core outperforms the Arm v8 cryptographic extensions for data blocks greater than 1,024 bytes.
Table 1: FreeRTOS Throughput, AES-GCM Encryption

FreeRTOS Operation Throughput:
AES-GCM 256-bit Encryption (MB/s)
Software Arm v8 Zynq UltraScale+ MPSoC
Block Size Only Crypto Extensions Crypto Hardware
16 3.785 53.041 4.012
528 7.52 278.156 122.285
1,024 7.634 297.949 219.531
4,112 7.73 315.976 555.58
7,696 7.743 318.9 691.379
15,888 7.746 318.949 844.344
Table 2 shows the results of AES-GCM 256-bit decryption running the wolfSSL benchmarks under
FreeRTOS. This table highlights in bold the fastest performing cryptographic extension and shows
that the Arm v8 cryptographic extensions outperform the Zynq UltraScale+ MPSoC’s embedded
cryptographic core for data blocks of less than or equal to 1,024 bytes, while the MPSoC crypto
core outperforms the Arm v8 cryptographic extensions for data blocks greater than 1,024 bytes.
Table 2: FreeRTOS Throughput, AES-GCM Decryption

AES-GCM 256-bit Decryption (MB/s)
16 3.756 43.414 2.069
528 7.515 166.307 59.153
1,024 7.634 175.415 100.244
4,112 7.73 183.429 237.055
7,696 7.75 184.771 291.194
15,888 7.746 184.854 373.363

In Table 3, the performance of SHA3/384 reveals that the software-only solution outperforms the
Zynq UltraScale+ MPSoC’s embedded cryptographic core only for data blocks of 16 bytes.
Table 3: FreeRTOS Throughput, SHA3/384

SHA3/384 (MB/s)
Software Zynq UltraScale+ MPSoC
Block Size Only Crypto Hardware
16 38.502 17.934
528 55.087 328.623
1,024 56.152 417.92
4,112 57.295 592.763
7,696 57.615 628.626
15,888 57.52 654.565
Table 4 shows that the Zynq UltraScale+ MPSoC embedded cryptographic core outperforms all
software-only based RSA solutions.
Table 4: FreeRTOS Average RSA Operation Time

FreeRTOS Avg. RSA Operation Time:
wolfSSL v3.12.0 (ms)
RSA Operation Only Crypto Hardware
Public Encrypt 2048 4.874 0.552
Private Decrypt 2048 89.25 12.846
wolfSSL on Linux
wolfSSL version 3.12.0 was run under Linux 4.14 as available in Xilinx release 2018.3[Ref 5] for the
Zynq UltraScale+ MPSoC. This was used to benchmark the software-only solution, Arm v8
cryptographic extensions, and the Zynq UltraScale+ MPSoC’s embedded cryptographic core
performance of the AES-GCM 256-bit, SHA3/384, RSA-2048, and RSA-4096 algorithms. Due to
memory management and execution privilege differences, applications running under Linux are
unlike RTOS applications, in that the same modifications made to the FreeRTOS port were not
applied to the Linux port. However, the same data set used in the FreeRTOS benchmarking was
used in Linux.
Due to Linux, the expectation is that user space applications run at the lowest-exception level (EL0)
on the Armv8 architecture. The Zynq UltraScale+ MPSoC’s cryptographic extensions are only
accessible from user space applications via a secure monitor call (SMC). This accesses the platform
management unit (PMU), which then accesses the cryptographic operation in the CSU using the
XilSecure library[Ref 4]. When the cryptographic operation is complete, the Linux application
continues to run after returning from the CSU, returning then from the PMU call, and subsequently
from the SMC. The high overhead of this scheme is reflected in the Linux benchmarking results.

Results
Table 5 shows the results of AES-GCM 256-bit encryption running the wolfSSL benchmarks under
Linux. This table highlights in bold the fastest performing cryptographic extension and shows that
the Arm v8 cryptographic extensions outperform the Zynq UltraScale+ MPSoC’s embedded
cryptographic core for all data block sizes. This is because the Arm v8 cryptographic extensions can
be directly accessed in user space and do not have to traverse a large software stack to reach the
CSU.
Table 5: Linux Throughput, AES-GCM Encryption

Linux 4.14 Operation Throughput:
AES-GCM 256-bit Encryption (MB/s)
16 4.426 54.309 0.151
528 8.971 300.263 4.68
1,024 9.105 322.934 8.66
4,112 9.206 344.002 27.769
7,696 9.235 347.552 42.572
15,888 9.23 345.605 59.948
Table 6 shows the results of AES-GCM 256-bit decryption running the wolfSSL benchmarks under
Linux. This table highlights in bold the fastest performing cryptographic extension and shows that
the Arm v8 cryptographic extensions outperform the Zynq UltraScale+ MPSoC’s embedded
cryptographic core for all data block sizes, due to the same reasons stated for encryption.
Table 6: Linux Throughput, AES-GCM Decryption

Linux 4.14 Operation Throughput:
AES-GCM 256-bit Decryption (MB/s)
16 4.397 34.835 0.146
528 8.955 179.661 4.535
1,024 9.1 192.258 8.52
4,112 9.22 203.652 27.083
7,696 9.231 205.579 41.784
15,888 9.213 204.456 59.311

In Table 7, the performance of SHA3/384 reveals that the software-only solution outperforms the
Zynq UltraScale+ MPSoC’s embedded cryptographic core for data block sizes less than or equal to
1,024 bytes, and the MPSoC crypto core outperforms the software-only solution for data block
sizes greater than or equal to 4,112 bytes.
Table 7: Linux Throughput, SHA3/384

Linux Operation Throughput:
SHA3/384 (MB/s)
Block Size Only Crypto Hardware
16 41.58 0.308
528 59.632 9.822
1,024 60.797 18.602
4,112 62.025 66.507
7,696 62.357 112.26
15,888 62.291 179.718
Table 8 shows that the Zynq UltraScale+ MPSoC’s embedded cryptographic core outperforms all
software-only RSA solutions, even with the high Linux calling overhead.
Table 8: Linux Average RSA Operation Time

Linux Avg. RSA Operation Time:
wolfSSL v3.12.0 (ms)
RSA Operation Only Crypto Hardware

Conclusion
With the exception only of the SHA3/384 Linux result, the cryptographic acceleration provided by
the Arm v8 cryptographic extensions and by the Zynq UltraScale+ MPSoC's embedded
cryptographic core outperforms a software-only solution.
Table 9 highlights the percentage of maximum performance improvement using the cryptographic
accelerators over a software-only solution. In Table 9, all maximum percentage of performance
improvements occurred in the wolfSSL FreeRTOS benchmark results using the Zynq UltraScale+
MPSoC's embedded cryptographic core with the largest block size for the AES and SHA algorithms,
and for all key sizes and all operations for the RSA algorithm.
Table 9: Performance Improvement: Cryptographic

Algorithms Over Software-Only Solutions
Algorithm Performance Improvement
AES-GCM 256-bit Encryption 10,800.39%
AES-GCM 256-bit Decryption 4,720.07%
SHA3/384 1,037.98%
RSA 2048 Public Encryption 782.97%
RSA 2048 Private Decryption 594.77%
RSA 4096 Public Encryption 849.69%
RSA 4096 Private Decryption 545.95%
The slight performance improvement of the software-only solutions between the FreeRTOS and
Linux data is due to the fact that the software-only solutions used different versions of compilers.
The FreeRTOS benchmarking used GCC version 6.2.1, while the Linux benchmarking used GCC
version 7.3.1. To confirm this difference in compilers, the software-only version of wolfSSL for Linux
was recompiled using GCC version 6.2.1 and the AES-GCM 256-bit algorithms were retested. The
results showed that AES-GCM 256-bit software-only encryption performance decreased to 7.023
MB/s, while decryption performance decreased to 7.022 MB/s. Even though this white paper
focuses on using cryptographic accelerators, the difference in compiler version performance shows
that using the latest tools is extremely important to maximize software performance.
Figure 1 compares all the benchmarking results from this white paper of the AES-GCM 256-bit
encryption algorithm run under the different benchmarking scenarios. Figure 1 clearly shows that
the software-only solutions have dramatically slower throughput compared to both accelerated
cryptographic solutions. When running wolfSSL benchmarking under FreeRTOS, the Zynq
UltraScale+ MPSoC's hardened cryptographic core outperforms the Arm v8 cryptographic
extensions for block sizes greater than 2,000 bytes. The FreeRTOS software-only solution overlaps
with the Linux software-only solution and is not legible on the chart. Due to the high overhead of
calling the MPSoC's AES-GCM 256-bit encryption engine from Linux, using the Arm v8
cryptographic extensions is always a better option to maximize performance.

X-Ref Target - Figure 1
wolfSSL 3.12.0 AES-GCM 256-Bit Encryption Performance

900
800
700
Throughput (MB/s)
600
500
400
300
200
100
0
0 2,000 4,000 6,000 8,000 10,000 12,000 14,000 16,000
Data Block Size (Bytes)
FreeRTOS Software Only Linux 4.14 Software Only

FreeRTOS Arm v8 Crypto Extensions Linux 4.14 Arm v8 Crypto Extensions
FreeRTOS Zynq UltraScale+ MPSoc Crypto Hardware Linux 4.14 Zynq UltraScale+ MPSoc Crypto Hardware
WP512_01_050719
Figure 1: Comparison Summary of All AES-GCM 256-Bit Encryption Results
Figure 2 compares all the performance results of the AES-GCM 256-bit decryption algorithm run
under the different benchmarking scenarios. Figure 2 does show results similar to those displayed
in Figure 1; however, the performance of the Zynq UltraScale+ MPSoC's embedded cryptographic
engine run under FreeRTOS outperforms the Arm v8 cryptographic extensions for block sizes
greater than 4,000 bytes. Again, the FreeRTOS software-only solution overlaps with the Linux
software-only solution and is not legible on the chart.
wolfSSL 3.12.0 AES-GCM 256-Bit Decryption Performance

400
350
300
Throughput (MB/s)
250
200
150
100
50
0
0 2,000 4,000 6,000 8,000 10,000 12,000 14,000 16,000

FreeRTOS Arm v8 Crypto Extensions Linux 4.14 Arm v8 Crypto Extensions
FreeRTOS Zynq UltraScale+ MPSoC Crypto Hardware Linux 4.14 Zynq UltraScale+ MPSoC Crypto Hardware
WP512_02_050719
Figure 2: Comparison Summary of All AES-GCM 256-Bit Decryption Results
Figure 3 shows the comparison results of running the SHA3/384 algorithm under the different
benchmarking scenarios. Like the results for AES-GCM 256-bit decryption, the performance of the
Zynq UltraScale+ MPSoC's embedded cryptographic engine when run under FreeRTOS clearly
outperforms all the other solutions except when using a block size of 16 bytes. Even Linux, with its

high calling overhead, shows performance improvement over a software-only solution when using
the embedded cryptographic accelerators for block sizes greater than 4,000 bytes.
wolfSSL 3.12.0 SHA3 Performance

700
600
500
Throughput (MB/s)
400
300
200
100
0
0 2,000 4,000 6,000 8,000 10,000 12,000 14,000 16,000

FreeRTOS ZU+Crypto Hardware Linux 4.14 ZU+Crypto Hardware
WP512_03_050719
Figure 3: Comparison Summary of All SHA3/384 Results
Figure 4, 5, 6, and 7 show the collective comparison of running all RSA operations under the various
benchmarking scenarios. These graphs consistently indicate that the use of the Zynq UltraScale+
MPSoC's embedded cryptographic core always outperforms a software-only solution. Additionally,
when accelerated performance is measured running RSA algorithms under FreeRTOS versus Linux,
FreeRTOS is always at least twice as fast due to the CSU being directly accessible in FreeRTOS.
wolfSSL 3.12.0 Average Operation Time

of RSA 2048 Public Encryption
5
4.874
4.5
4.424
4
3.5
Time (ms)
3
2.5
2
1.5
1.342
1
0.5
0.552
0
FreeRTOS FreeRTOS Linux 4.14 Linux 4.14
Software Only Zynq UltraScale+ MPSoC Software Only Zynq UltraScale+ MPSoC
Crypto Hardware Crypto Hardware
Benchmark Test
WP512_04_040819
Figure 4: Summary of All RSA-2048 Public Encryption Benchmark Results


of RSA 2048 Private Decryption
90
89.25
80 83.512
70
60
Time (ms)
50
40
30
20 25.71
10 12.846
0
Benchmark Test WP512_05_040819
Figure 5: Summary of All RSA-2048 Public Decryption Benchmark Results

of RSA 4096 Public Encryption
20
18 18.519
16 16.736
14
Time (ms)
12
10
8
6
4
4.152
2
1.95
0
Benchmark Test WP512_06_040819
Figure 6: Summary of All RSA-4096 Public Encryption Benchmark Results


of RSA 4096 Private Decryption
700
600 619.47
569.89
500
Time (ms) 400
300
200
191.778
100
95.9
0
Benchmark Test
WP512_07_040819
Figure 7: Summary of All RSA-4096 Public Decryption Benchmark Results
System architects who are tasked to define cryptographic solutions should evaluate:
• How the algorithm is run—utilizing Arm v8 cryptographic extensions, or using the Zynq
UltraScale+ MPSoC's embedded cryptographic core
• The size of each data block
• Where the algorithm is running—on a simple RTOS, or in Linux user space
• Out of which memory space the software is running—out of DDR memory, or out of on-chip
memory (OCM). While this paper did not test running the cryptographic algorithms out of DDR
versus OCM, this factor should be considered.
As shown in this white paper, these variables can significantly affect the performance of the Zynq
UltraScale+ MPSoC's accelerated cryptographic performance. The research for this white paper
covered only a small subset of possible benchmarking scenarios compared to the number of
possible solution combinations. End users should ultimately benchmark their own design to make
sure performance requirements are being met.
These results confirm that using the cryptographic accelerators on the Zynq UltraScale+ MPSoC
can vastly improve cryptographic performance and will benefit any market and any application that
utilizes the AES-GCM-256-bit algorithm, the SHA3/384 algorithm, the RSA-2048 algorithm, and/or
the RSA-4096 algorithm. Secondly, these algorithms cover all the foundations for a secure system
and covers the aspects of confidentiality, integrity, and authentication. Lastly, not only is a
performance increase achieved on the Zynq UltraScale+ MPSoC by using the cryptographic
accelerators but doing so will reduce the resource load on the Arm Cortex-A53s, the Arm
Cortex-R5s, and the programmable logic. In this way, Zynq UltraScale+ MPSoC applications have a
lot more system resources available to dedicate to the application's needs instead of devoting
resources to cryptographic needs.

References
1. Xilinx User Guide UG1085, Zynq UltraScale+ Device Technical Reference Manual
2. Arm Technical Reference Manual, Cortex®-A53 MPCore Processor Cryptography Extension,
Revision r0p4
3. wolfSSL website product landing page
4. Xilinx User Guide UG1137, Zynq UltraScale+ MPSoC Software Developer Guide, Appendix I:
XilSecure Library v3.1
5. Xilinx User Guide UG1144, Linux Tools Documentation Reference Guide
Revision History
The following table shows the revision history for this document:
Date Version Description of Revisions

05/21/2019 1.0 Initial Xilinx release.
Disclaimer
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx
products. To the maximum extent permitted by applicable law: (1) Materials are made available “AS IS” and with all faults,
Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT
LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability)
for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your
use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss
of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even
if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx
assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to
product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written
consent. Certain products are subject to the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s
Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and
support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe
or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products
in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at http://www.xilinx.com/
legal.htm#tos.
Automotive Applications Disclaimer

XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR
(III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF
ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.

wp512 Accel Crypto

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

wp512 Accel Crypto

Uploaded by

Copyright:

Available Formats

White Paper: Zynq UltraScale+ MPSoC

WP512 (v1.0) May 21, 2019

The Zynq® UltraScale+™ MPSoC’s embedded cryptographic

WP512 (v1.0) May 21, 2019 www.xilinx.com 1

WP512 (v1.0) May 21, 2019 www.xilinx.com 2

Table 1: FreeRTOS Throughput, AES-GCM Encryption

Table 2: FreeRTOS Throughput, AES-GCM Decryption

WP512 (v1.0) May 21, 2019 www.xilinx.com 3

Table 3: FreeRTOS Throughput, SHA3/384

Table 4: FreeRTOS Average RSA Operation Time

WP512 (v1.0) May 21, 2019 www.xilinx.com 4

Table 5: Linux Throughput, AES-GCM Encryption

Table 6: Linux Throughput, AES-GCM Decryption

WP512 (v1.0) May 21, 2019 www.xilinx.com 5

Table 7: Linux Throughput, SHA3/384

Table 8: Linux Average RSA Operation Time

WP512 (v1.0) May 21, 2019 www.xilinx.com 6

Table 9: Performance Improvement: Cryptographic

WP512 (v1.0) May 21, 2019 www.xilinx.com 7

X-Ref Target - Figure 1

wolfSSL 3.12.0 AES-GCM 256-Bit Encryption Performance

FreeRTOS Software Only Linux 4.14 Software Only

Figure 1: Comparison Summary of All AES-GCM 256-Bit Encryption Results

wolfSSL 3.12.0 AES-GCM 256-Bit Decryption Performance

FreeRTOS Software Only Linux 4.14 Software Only

Figure 2: Comparison Summary of All AES-GCM 256-Bit Decryption Results

WP512 (v1.0) May 21, 2019 www.xilinx.com 8

wolfSSL 3.12.0 SHA3 Performance

FreeRTOS Software Only Linux 4.14 Software Only

Figure 3: Comparison Summary of All SHA3/384 Results

wolfSSL 3.12.0 Average Operation Time

Figure 4: Summary of All RSA-2048 Public Encryption Benchmark Results

WP512 (v1.0) May 21, 2019 www.xilinx.com 9

X-Ref Target - Figure 5

wolfSSL 3.12.0 Average Operation Time

Figure 5: Summary of All RSA-2048 Public Decryption Benchmark Results

X-Ref Target - Figure 6

wolfSSL 3.12.0 Average Operation Time

Figure 6: Summary of All RSA-4096 Public Encryption Benchmark Results

WP512 (v1.0) May 21, 2019 www.xilinx.com 10

X-Ref Target - Figure 7

wolfSSL 3.12.0 Average Operation Time

Time (ms) 400

Figure 7: Summary of All RSA-4096 Public Decryption Benchmark Results

WP512 (v1.0) May 21, 2019 www.xilinx.com 11

Date Version Description of Revisions

Automotive Applications Disclaimer

WP512 (v1.0) May 21, 2019 www.xilinx.com 12

You might also like