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A New Hybrid Asymmetric Multilevel Inverter With Reduced Number of Switches
A New Hybrid Asymmetric Multilevel Inverter With Reduced Number of Switches
Abstract—This paper proposes a new hybrid asymmetric MLI so far [3]. The developing of hybrid MLI topology is the
multilevel inverter for generating the higher number of levels main goal to achieve higher number of levels. Most of the
with reduced number of power semiconductor switches. The hybrid topology utilizes a very high value of DC source
hybrid asymmetric multilevel inverter consists of full bridge because topologies are operated at the asymmetric condition.
inverter and reduced switch inverter topology. The reduced New hybrid multilevel inverter topologies can be developed
switch inverter topology can generate 13-level output voltage through the controllable degree of freedom of the DC voltage
without utilizing full bridge inverter. When the full bridge proportional relation [4]. In [5], a hybrid topology utilizes a
inverter is combined with reduced switch inverter topology, it reduced switch topology with secondary windings are cascaded
can generate the 27-level output voltage. Sinusoidal pulse width
to achieve high output voltage range. But the drawback is the
modulation technique is used to trigger the multilevel inverter
switches and to achieve high-quality output voltage with lesser
utilization of multiple transformers because cost and size of
total harmonic distortion. The performance of proposed transformers are high. In [6], Packed U-cell MLI is connected
multilevel inverter is tested by MATLAB/SIMULINK and with CHBMLI in three-phase condition. The topology is
validated the results with different parameters. The output operated at high voltage condition with different transient
voltage level of proposed multilevel inverter is satisfied IEEE519 conditions. In [7], diode bypassed transistor voltage source
harmonic standard without using any passive filters. MLI is introduced and it is hybridized with CHBMLI in [8].
The value of CHBMLI is the next consecutive geometric
Keywords—multilevel inverter; pulse width modulation; progression of reduced switch MLI. So, the CHBMLI have
reduced switch MLI; asymmetric; total harmonic distortion more peak inverse voltage and more stress on the switches. In
[9] transistor clamped MLI topology is combined with
I. INTRODUCTION conventional CHBMLI to generate higher voltage level. In [10,
Multilevel inverters have been focused for decades due to 11] requires the high number of DC link capacitors for
important features for generating the high-quality output achieving required output voltage level. In [12] a bidirectional
voltage, lower switching stress, utilizing for high switch is connected between two CHBMLI units and it utilized
voltage/power applications [1]. The Multilevel inverter has for fault recovering operation. In [13], a comparative analysis
rapidly increased research topic in power electronics is carried out for symmetric and asymmetric conditions with
applications such as electric hybrid vehicle, renewable energy the same number of switches. In [14], a combination of
sources, Flexible AC Transmission System (FACTS) and CHBMLI with double level circuit is utilized for photovoltaic
electric drives [1,2]. Nowadays many industries are used application. Multiple DC source MLIs are utilized for
conventional MLI configurations such as Diode Clamped photovoltaic and FACTS applications [15-17].
Multilevel Inverter (DCMLI), Flying Capacitor Multilevel This paper proposes a new hybrid asymmetric multilevel
Inverter (FCMLI) and Cascaded H-Bridge Multilevel Inverter inverter topology that can generate the higher number of output
(CHBMLI) in Mega Watt range [2]. But the main problem in voltage levels with the lesser number of power electronics
DCMLI and FCMLI has high number of additional components and lower DC source value. The value of DC
components such as blocking diodes, clamping capacitors and source in H-Bridge is chosen based on the lowest value of DC
DC-link capacitors when compared to conventional CHBMLI sources in reduced switch topology. The DC source value is
[1,2]. The balancing of each capacitor is the difficult task and considered as half of the value of lowest value of DC in
also design package is not easier because of utilizing more reduced switch MLI. Sinusoidal pulse width modulation
number of capacitors [3]. But, CHBMLI free from clamping (SPWM) with Phase Disposition carrier arrangement is utilized
diodes and clamping capacitors but high number of switches is for generating a 27-level output voltage and the results are
utilized for generating particular output voltage level. obtained. In the proposed topology, two switches are operated
Nowadays, hybrid asymmetric multilevel inverters are at the fundamental switching frequency and remaining
involving to generate the higher number of output voltage level switches are operated at high switching frequency. Also, peak
with the lesser number of switches. Generally, asymmetric inverse voltage of the proposed MLI is less when compared to
MLI generates a high number of voltage levels when compared conventional MLI topologies. Comparative study is carried out
with symmetric MLI. Many topologies are reported in hybrid
Number of −3
4× +1 −1
DC sources 4
Number of
voltage level 2 × (12 × ) + 1
Number of
3×( − 1)
10 × +4 +1
switches 6
Number of
3×( − 1)
8× +4 −1
driver circuit 6
Amplitude in volts
5
voltage level. The calculation of components for all topology is
based 27-level output voltage. Also, the proposed topology
0
requires 12 switches but in the table it represents 14 switches.
Because the topology utilizes two bidirectional switches. The
-5
creation of bidirectional switch is the combination of two
switches with emitter coupled. But, the bidirectional switch
-10
requires only one diver circuit. From the table 3, it is clearly
shows that the proposed asymmetric MLI utilizes less number 0 0.005 0.01 0.015 0.02
of components and cost effective. Time in seconds
(a)
TABLE 3 COMPARISION OF COMPONENTS WITH CONVENTIONAL MLIS 6
Current in amps
Parameters NPCMLI FCMLI CHBMLI Proposed 2
0
Number of diodes 650 - - -
-2
-4
Number of capacitors - 325 - -
-6
Number of voltage level 27 27 27 27 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Time in seconds
(b)
Number of switches 52 52 52 14 Fig. 2. (a) Phase Disposition carrier arragement (b) output voltage level for
proposed hybrid asymmetric MLI
Number of driver 52 52 12
52
circuit Fundamental (50Hz) = 325.1 , THD= 4.28%
100
Mag (% of Fundamental)
80 2.5
60 1.5
1
IV. SIMULATION RESULTS 40 0.5
0
0 50 100 150 200 250 300
The proposed multilevel inverter is designed for 27-level 20 Harmonic order
resistive inductive load (RL) = 422.5 Ω and 25 mH. Fig. 2.b -300
shows the output voltage level and output current waveform for 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
proposed hybrid asymmetric multilevel inverter without Time in seconds
(b)
passive filters. Fig. 4.a shows the simulation FFT plot for
Fig. 4. (a) Phase Disposition FFT plot and (b) Different ouput voltages for
proposed hybrid asymmetric multilevel inverter without proposed hybrid asymmetric MLI
S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1
1
0
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Time in seconds
Fig. 3. PWM Switching singal for proposed hybrid asymmetric MLI