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Intel Penryn CPU + Cantiga + ICH9M Chipset


F30II0 M/B / Sx XXXX

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01 COVER PAGE

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D
02 BLOCK DIAGRAM F30II0 M/B and Daughter P/N BD List : F30II0 M/B Power Rail State : D
03 MISCELLANEOUS

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04 GPIO
82GF30000-A0 MAIN BOARD ASSY F30II0 REV.A0 Signal
05 CPU Penryn 1 of 2 +*V_LDO +*V_AUX +*V_DDR +*VS +*V CLK

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37GF30000-A0 PCB Main BD F30II0 REV:A State
06 CPU Penryn 2 of 2
07 NB Cantiga 1 of 4 80GWF3000-A0 DCIN+LAN+USB BD FOR F30II0 R:A AC/DC S0/Moff (Full On) ON ON ON ON ON ON

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08 NB Cantiga 2 of 4 35GWF3000-A0 PCB DCIN+LAN+USB BD FOR F30II0 R:A
AC/DC S3/Moff (STR) ON ON ON ON OFF LOW

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09 NB Cantiga 3 of 4
80GPF3000-A0 ODD BB BD FOR F30II0 R:A
10 NB Cantiga 4 of 4 AC/DC S4/Moff (STD) ON ON OFF OFF OFF OFF

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35GPF3000-A0 PCB SATA ODD BB FOR F30II0 REV:A
11 DDR2 SODIMMs
AC S5/Moff (Soft Off) ON ON OFF OFF OFF OFF
12 DVI SHIFTER/SMART PWR 80G8F3000-A0 TOUCHPAD BD FOR F30II0 REV:A0

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13 CLOCK GENERATOR 35G8F3000-A0 PCB TOUCHPAD BD FOR F30II0 REV:A DC S5/Moff (Soft Off) ON OFF OFF OFF OFF OFF

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14 SB ICH9M 1 of 3
80G4F3000-A0 LED BD FOR F30II0 REV:A
15 SB ICH9M 2 of 3
35G4F3000-A0 PCB LED BD FOR F30II0 REV:A
16 SB ICH9M 3 of 3

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17 FAN/MINI CARD/ODD_BB/HDD CON 80Gxxxxxx-A0 SWITCH BD FOR F30II0 REV:A
C C
18 DVI/LCD CON 80Gxxxxxx-A0 MMB BD FOR F30II0 REV:A
19 WEB CAM/BT/NEW CARD/EXT_USB

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20 GLAN-82567LF
21 1394/CARD READER-JMB380

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22 AUDIO CODEC-ALC888
23 AUDIO AMP/eSATA+USB/FP CON

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24 EC-IT8512E/BIOS/TP/KB/MMB/HS
25 POWER SWITCH
26 +3.3V_AUX/+5V_AUX (OZ815)

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27 +CPU_CORE (MAX8770)
28 +GFX CORE (OZ827)

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29 +1.8V_DDR(OZ811)/+0.9V(LDO)
30 +1.05V/+1.5V (OZ8138)

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31 AC IN & CHARGER (OZ8602)

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32 MB REV. HISTORY
B 33 Daughter BD-DCIN+LAN+USB B

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34 Daughter BD-SATA ODD BB
35 Daughter BD-Touch PAD

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36 Daughter BD-LED
37

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38

MADE IN TAIWAN

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BU2-BK120

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ECS COMPUTER CORP.


Title
COVER PAGE
Size Document Number Rev
A
3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 1 of 36
5 4 3 2 1
5 4 3 2 1

SYSTEM BLOCK DIAGRAM

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Intel PENRYN 45-n

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Thermal Sense
478-Pin uFCPGA 5,6 EMC1402 5
D D

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FSB 667 / 800 / 1066

OUT

IN
EXTERNAL CLOCK GENERATOR VTT=1.05V

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CRYSTAL Clock Generator Intel NB - CANTIGA

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14.31818MHz ICS9LPRS365 13
Direct Management Interface Dual Channel
UNBUFFERED DDR2

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LCD CON LVDS (DMI) DDRII 667/800 NEAR SODIMM
18

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INTEGRATED GRAPHICS DIMM-A 6,11
LVDS/DVI 200-PIN DDR2 SODIMM

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Support for DDR2 at 667 MHz
DVI CON DVI DVI SHIFTER TMDS UNBUFFERED DDR2
18 CH7318 12 and 800 MHz
FAR SODIMM

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IntelR Active Management DIMM-B 6,11
Technology (IntelR AMT) 4.0 200-PIN DDR2 SODIMM
IntelR Active Management Technology (IntelR AMT) 4.0

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7,8,9,10

C C
Bluetooth Web Camera
19 19 DMIx4

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Int.SPK Digit.MIC
23 22
USB#8 USB#3 USB#2 USB#1 USB#0
Intel SB - ICH9M HD AUDIO I/F Audio Codec

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USB 2.0
17 19 19 19 23 USB2.0 (12) ALC888 22
SPDIF Line-In Ext.MIC

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SATA II (4 PORTS)
22 22 22
USB#9 USB#7 USB#5 USB#4 External SATA support
19 22 22 19 SATA II I/F SATA HDD
IntelR High Definition Audio 17

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Codec(s)
1 X6 PCIE I/F SATA ODD
Finger Print Mini Card#2 Mini Card#1 PCI-E Card X1 PCIE INTERFACE 17

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23 Robson 17 Shirley Peak17 New Card 19 Intell(R) Gigab it Ethernet Phy
LPC I/F
eSATA Port

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PCI/PCI BDGE 23
SM Bus 2 .0/I2C

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SPI I/F
B
RTC CRYSTAL B
INT RTC 32.768KHz

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LAN CRYSTAL PCIEXPRESS LAN
25.000MHz GLAN-82567LF 20 ACPI 3.0b 14, 15, 16

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1394 CRYSTAL 1394+CardReader

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24.576MHz JM380 21 LPC BUS

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ITE LPC SIO IT8512E LPC DEBUG CARD
SMART POWER CPU FAN CIRCUIT Power Button CRYSTAL
12 17 CIRCUIT 24 32.768KHz 24 23

POWER SWITCH SYSTEM POWER CPU_CORE POWER


25 OZ815 26 MAX8770 27
HELL MMB KEYBOARD T/P FLASH BIOS
Sensor (SPI ROM)
24 24 24 24 24
A A
GFX POWER DDRII MEM POWER MCH CORE & POWER
OZ827 28 OZ811/FP6137 29 OZ8138 30

ECS COMPUTER CORP.


BATTERY CHAGER Title
OZ8602 31
BLOCK DIAGRAM
Size Document Number Rev
3931 A
Custom F30II0
Date: Monday, November 05, 2007 Sheet 2 of 36
5 4 3 2 1
5 4 3 2 1

CPU Intel Penryn LAPTOP MODE USB PORTS DEVICES TABLE


POWER RAIL S0 S1 S3 S4 S5 USBP0 USBP1 USBP2 USBP3 USBP4 USBP5 USBP6 USBP7 USBP8 USBP9 USBP10 USBP11
VCC VID[6:0] ON ON OFF OFF OFF USB Ports USBN0 USBN1 USBN2 USBN3 USBN4 USBN5 USBN6 USBN7 USBN8 USBN9 USBN10 USBN11

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VCCP +1.05V ON ON OFF OFF OFF
VCCA +1.5V ON ON OFF OFF OFF Devices M/B eSATA DC-IN BD DC-IN BD WEBCAM Mini Card_1 Mini Card_2 New Card Finger PR Bluetooth
N/A N/A N/A

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USB0 USB_1 USB_2 USB_3 USB_4 USB_5 USB_6 USB_7 USB_8

D D

NB Cantiga LAPTOP MODE

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POWER RAIL S0 S1 S3 S4 S5 SYSTEM POWER RAIL LAPTOP MODE
VCC_AXG VID[4:0] ON ON OFF OFF OFF Voltage Name Control Pin S0 S1 S3 S4 S5

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VCC +1.05V ON ON OFF OFF OFF +CPU_CORE +CPU_CORE_ON ON ON OFF OFF OFF
VCC_AXF +1.05V ON ON OFF OFF OFF +GFX_CORE +GFX_VR_ON ON ON OFF OFF OFF

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VCC_PEG +1.05V ON ON OFF OFF OFF +1.05V +1.5V_ON ON ON OFF OFF OFF

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VCC_DMI +1.05V ON ON OFF OFF OFF +1.5V +1.5V_ON ON ON OFF OFF OFF
VCCA_DPLLA/B +1.05V ON ON OFF OFF OFF +1.8V follow +3.3V up ON ON OFF OFF OFF

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VCCA_HPLL +1.05V ON ON OFF OFF OFF +3.3V +5V_ON ON ON OFF OFF OFF
VCCA_MPLL +1.05V ON ON OFF OFF OFF +5V +5V_ON ON ON OFF OFF OFF

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VCCA_PEG_PLL +1.05V ON ON OFF OFF OFF +0.9V_DDR follow +1.8V_DDR up ON ON ON OFF OFF

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VCCA_SM +1.05V ON ON OFF OFF OFF +1.8V_DDR +DDR_ON ON ON ON OFF OFF
VCCA_SM_CK +1.05V ON ON OFF OFF OFF +1.8VS follow +1.8V_DDR up ON ON ON OFF OFF
VCCD_HPLL +1.05V ON ON OFF OFF OFF +3.3VS +5VS_ON ON ON ON OFF OFF

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VCCD_PEG_PLL +1.05V ON ON OFF OFF OFF +5VS +5VS_ON ON ON ON OFF OFF
C C
VTT +1.05V ON ON OFF OFF OFF VIN_SW PWR_KEEP ON ON ON OFF OFF
VCCA_PEG_BG +1.5V ON ON OFF OFF OFF +3.3V_AUX AC:follow VIN up ON ON ON ON ON

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VCCD_TVDAC +1.5V ON ON OFF OFF OFF DC:AUX_ON ON ON ON OFF OFF
VCCD_QDAC +1.5V ON ON OFF OFF OFF +5V_AUX AC:follow VIN up ON ON ON ON ON

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VCCD_TVDAC +1.5V ON ON OFF OFF OFF DC:AUX_ON ON ON ON OFF OFF
VCC_HV +3.3V ON ON OFF OFF OFF

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VCCA_CRT_DAC +3.3V ON ON OFF OFF OFF
VCCA_DAC_BG +3.3V ON ON OFF OFF OFF
VCCA_TV_DAC +3.3V ON ON OFF OFF OFF

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+3.3V_AUX
VCC_SM +1.8V_DDR ON ON ON OFF OFF
Power Block Diagram +3.3VS
MOSFET SW 25

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VCC_SM_CK +1.8V_DDR ON ON ON OFF OFF
VCC_TX_LVDS +1.8VS ON ON ON OFF OFF +5VS_ON

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VCCA_LVDS +1.8VS ON ON ON OFF OFF +3.3V_AUX +3.3V
Power PWM IC +3.3V +1.8VS NB LDO
VCCD_LVDS +1.8VS ON ON ON OFF OFF VIN MOSFET SW 25 FP6133-18S5P 10

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Power SW Mosfet +CPU_CORE PWM
MAX8770 27 +1.8VS /0.3A
B
Power Regulator +5V_ON B
+CPU_CORE /44A +DDR_ON

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SB ICH9M LAPTOP MODE Power Input +5V_AUX
+CPU_CORE_ON +5VS +3.3V
POWER RAIL S0 S1 S3 S4 S5 MOSFET SW 25 +1.8V 1394 LDO
FP6133-18S5P 21

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V_CPU_IO +1.05V ON ON OFF OFF OFF VADAP
DC-JACK All_AUX PWM +5VS_ON +1.8V /0.3A
Vcc_DMI +1.05V ON ON OFF OFF OFF 31 OZ815 26
+5V_AUX follow +3.3V up

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Vcc1_05 +1.05V ON ON OFF OFF OFF +3.3V_AUX /9.5A +5V
+5V_AUX /6A MOSFET SW 25
Vcc1_5_A +1.5V ON ON OFF OFF OFF
VIN AC: follow VIN up
Vcc1_5_B +1.5V ON ON OFF OFF OFF CHARGER +5V_ON

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31 DC: AUX_ON
OZ8602 VIN
VccDMIPLL +1.5V ON ON OFF OFF OFF
VIN_SW
VccGLAN1_5 +1.5V ON ON OFF OFF OFF MOSFET SW 25
VccGLANPLL +1.5V ON ON OFF OFF OFF
VBAT PWR_KEEP
VccSATAPLL +1.5V ON ON OFF OFF OFF BATTERY +GFX_CORE PWM
31 OZ827 28
VccUSBPLL +1.5V ON ON OFF OFF OFF
+GFX_CORE /9A
Vcc3_3 +3.3V ON ON OFF OFF OFF
+GFX_VR_ON
VccGLAN3_3 +3.3V ON ON OFF OFF OFF
VccCL3_3 +3.3V ON ON OFF OFF OFF VIN +1.8V_DDR
A +1.8V_DDR PWM +0.9V_DDR LDO A
VccLAN3_3 +3.3V ON ON OFF OFF OFF OZ811 29 FP6137 29
VccHDA3_3 +3.3V ON ON OFF OFF OFF +1.8V_DDR /11A +0.9V_DDR /1.0A
V5REF +5V ON ON OFF OFF OFF +DDR_ON follow +1.8V_DDR up
ECS COMPUTER CORP.
VccSusHDA3_3 +3.3VS ON ON ON OFF OFF
Title
VccSus3_3 +3.3VS ON ON ON OFF OFF +1.5V PWM +1.05V_PWM
OZ8138 28 OZ8138 28 MISCELLANEOUS
V5REF_Sus +5VS ON ON ON OFF OFF Size Document Number Rev
+1.5V_NB /4A +1.05V /11A A
VccRTC +3.0V ON ON ON ON ON 3931
Custom F30II0
+1.5V_ON +1.5V_ON Date: Monday, November 05, 2007 Sheet 3 of 36
5 4 3 2 1
5 4 3 2 1

ICH9-M General Purpose I/O ICH9-M General Purpose I/O ITE8512E General Purpose I/O ITE8512E General Purpose I/O
Power Power Default Default

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Name Type Description EDS v2.0
Name Type Description EDS v2.0
Name Type Description Spec v4.0.1
Name Type Description Spec v4.0.1
Well Well Pull Pull
GPIO0 I/O-I Core PM_SYNC# GPIO57 I/O-I Sus ICH_GPIO57 GPIOA0 I/O-I Up BTL_BEEP GPIOH0 I/O-I Dn +CPU_CORE_ON

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GPIO1 I/O-I Core EC_EXTSCI# GPIO58 I/O-I Sus SPI_CS#1 IPH 20K GPIOA1 I/O-I Up RF_OFF# GPIOH1 I/O-I Dn +GFX_VR_ON
D D
GPIO2 I/OD-I Core INT_PIRQE# GPIO59 I/O-N Sus USB_OC#0 GPIOA2 I/O-I Up EC_VID2 GPIOH2 I/O-I Dn EC_USB2

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GPIO3 I/OD-I Core INT_PIRQF# GPIO60 I/O-N Sus ICH_GPIO60 GPIOA3 I/O-I Up EC_VID3 GPIOH3 I/O-I Dn EC_USB1
GPIO4 I/OD-I Core INT_PIRQG# GPIOA4 I/O-I Up EC_VID4 GPIOH4 I/O-I Dn +5VS_ON

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GPIO5 I/OD-I Core INT_PIRQH# GPIOA5 I/O-I Up EC_VID5 GPIOH5 I/O-I Dn +DDR_ON
GPIO6 I/O-I Core EC_EXTSMI# GPIOA6 I/O-I Up SMP_100MV_EN# GPIOH6 I/O-I Dn +1.5V_ON

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GPIO7 I/O-I Core N.C GPIOA7 I/O-I Up SMP_50MV_EN# GPII0 I-ADC BATT_TEMP

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GPIO8 I/O-I Sus N.C GPIOB0 I/O-I Up NC_PWRONS GPII1 I-ADC ADAPTOR_I
GPIO9 I/O-N Sus LAN_WOL_EN GPIOB1 I/O-I Up BT_EN GPII2 I-ADC SUS_PWR_ACK

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GPIO10 I/O-I Sus SUS_PWR_ACK GPIOB2 I/O-I Dn LED_PWR_B GPII3 I-ADC EC_CPUISENSE
GPIO11 I/O-N Sus SMB_ALERT# GPIOB3 I/O-I SMB_CLK_BAT GPII4 I-ADC PM_SLP_S4#

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GPIO12 I/O-O Sus LANPHY_EN GPIOB4 I/O-I SMB_DATA_BAT GPII5 I-ADC PM_SLP_S3#

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GPIO13 I/O-I Sus ICH_TM_OFF# GPIOB5 I/O-O H_A20GATE GPII6 I-ADC PM_SLP_M#
GPIO14 I/O-I Sus AC_PRESENT GPIOB6 I/O-Fn Up H_RCIN# GPII7 I-ADC EC_CPUVSENSE
GPIO16 I/O-N Core PM_DPRSLPVR IPD 20K GPIOB7 I/O-I Dn MUTE_AMP# GPIOJ0 I/O-DA EC_BRIGHTNESS

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GPIO17 I/O-I Core N.C GPIOC0 I/O-I Dn SMARTVOL GPIOJ1 I/O-DA CHG_I
C C
GPIO18 I/O-O Core ICH_FP_EN GPIOC1 I/O-I SMB_CLK_GEN GPIOJ2 I/O-DA FAN_CTRL0
GPIO19 I/O-I Core SATA_DET#1 GPIOC2 I/O-I SMB_DATA_GEN GPIOJ3 I/O-DA CHG_ON

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GPIO20 I/O-O Core N.C IPD 20K GPIOC3 I/O-I Dn SMP2_EN# GPIOJ4 I/O-DA AC_PRESENT
GPIO21 I/O-I Core SATA_DET#0 GPIOC4 I/O-I Dn PWR_KEEP GPIOJ5 I/O-DA CHG_V

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GPIO22 I/O-I Core ICH_GPIO22 GPIOC5 I/O-I Dn EC_SKIP
GPIO23 I/O-N Core LPC_DRQ#1 IPH 20K GPIOC6 I/O-I Dn PM_PWRBTN#

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GPIO24 I/O-O Sus N.C GPIOC7 I/O-I Up GFXVR_EN
GPIO26 I/O-N Sus SLP_S4_STATE# GPIOD0 I/O-I Up AC_IN
GPIO27 I/O-O Sus N.C GPIOD1 I/O-I Up MMB_DE#

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GPIO28 I/O-O Sus ODD_PWR_EN GPIOD2 I/O-Fn Up BUF_PLT_RST#
GPIO29 I/O-N Sus USB_OC#5 GPIOD3 I/O-I Up EC_EXTSCI#_R

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GPIO30 I/O-N Sus USB_OC#6 GPIOD4 I/O-I Up EC_EXTSMI#_R
GPIO31 I/O-N Sus USB_OC#7 GPIOD5 I/O-I Up ALL_SYS_PWRGD

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GPIO33 I/O-O Core HDA_DOCK_EN# IPH 20K GPIOD6 I/O-I Dn FAN_SPEED#

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GPIO34 I/O-O Core N.C GPIOD7 I/O-I Dn LED_RF_B
B GPIO35 I/O-O Core CLK_SATA_OE# GPIOE0 I/O-I Dn PM_RSMRST# B

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GPIO36 I/O-I Core SATA_DET#4 GPIOE1 I/O-I Dn EC_MPWROK
GPIO37 I/O-I Core SATA_DET#5 GPIOE2 I/O-I Dn LED_CHR_B

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GPIO38 I/O-I Core N.C GPIOE3 I/O-I Dn LED_PWSW_W
GPIO39 I/O-I Core N.C GPIOE4 I/O-I Up PWR_SW

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GPIO40 I/O-N Sus USB_OC#1 GPIOE5 I/O-I Dn LED_CHR_R
GPIO41 I/O-N Sus USB_OC#2 GPIOE6 I/O-I Dn LPCPD#
GPIO42 I/O-N Sus USB_OC#3 GPIOE7 I/O-I Up NC_PWRON

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GPIO43 I/O-N Sus USB_OC#4 GPIOF0 I/O-I Up EC_PROCHOT
GPIO44 I/O-N Sus USB_OC#8 GPIOF1 I/O-I Up WEBCAM_EN
GPIO45 I/O-N Sus USB_OC#9 GPIOF2 I/O-I Up PM_LAN_ENABLE
GPIO46 I/O-N Sus USB_OC#10 GPIOF3 I/O-I Up +3.3VM_ON
GPIO47 I/O-N Sus USB_OC#11 GPIOF4 I/O-I Up PS2_CLK_TP
GPIO48 I/O-I Core N.C GPIOF5 I/O-I Up PS2_DATA_TP
GPIO49 I/O-O Core N.C GPIOF6 I/O-I Up NC_PERST#
GPIO50 I/O-N Core PCI_REQ#1 IPH 20K GPIOF7 I/O-I Up NC_CPPE#
A A
GPIO51 I/O-N Core N.C IPH 20K GPIOG0 I/O-O Up BKL_EC
GPIO52 I/O-N Core PCI_REQ#2 GPIOG1 I/O-O Dn +5V_ON
GPIO53 I/O-N Core N.C IPH 20K GPIOG2 I/O-Fn FLFRAME#
ECS COMPUTER CORP.
GPIO54 I/O-N Core PCI_REQ#3 GPIOG6 I/O-I LID#
IPH 20K Title
GPIO55 I/O-N Core PCI_GNT#3
GPIO
GPIO56 I/O-I Sus ICH_GPIO56 Size Document Number Rev
A
3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 4 of 36
5 4 3 2 1
5 4 3 2 1

+1.05V

U13A
[7] H_A#[35:3]
H_A#3 J4 H1 H_ADS#
A[3]# ADS# H_ADS# [7]
H_A#4 L5 E2 H_BNR#

ADDR GROUP_0
A[4]# BNR# H_BNR# [7]
H_A#5 L4 G5 H_BPRI#
A[5]# BPRI# H_BPRI# [7]

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H_A#6 K5
H_A#7 A[6]# H_DEFER# R376
M3 A[7]# DEFER# H5 H_DEFER# [7]
H_A#8 N2 F21 H_DRDY# 56R
A[8]# DRDY# H_DRDY# [7]
H_A#9 J1 E1 H_DBSY#

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A[9]# DBSY# H_DBSY# [7]
H_A#10 N3
H_A#11 A[10]# H_BREQ#
P5 A[11]# BR0# F1 H_BREQ# [7]
D H_A#12 P2 D
A[12]#

CONTROL
H_A#13 L2 D20 H_IERR#_R
H_A#14 A[13]# IERR# H_INIT#

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P4 A[14]# INIT# B3 H_INIT# [14]
H_A#15 P1 R377
H_A#16 A[15]# H_LOCK# @56R
R1 A[16]# LOCK# H4 H_LOCK# [7]
H_ADSTB#0 M1
[7] H_ADSTB#0 ADSTB[0]#

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C1 H_CPURST#
[7] H_REQ#[4:0] RESET# H_CPURST# [7]
H_REQ#0 K3 REQ[0]# H_RS#[2:0] [7]
H_REQ#1 H2 F3 H_RS#0
H_REQ#2 REQ[1]# RS[0]# H_RS#1
K2 F4

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H_REQ#3 REQ[2]# RS[1]# H_RS#2
J3 REQ[3]# RS[2]# G3
H_REQ#4 L1 G2 H_TRDY#
REQ[4]# TRDY# H_TRDY# [7]
[7] H_A#[35:3]

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H_A#17 Y2 G6 H_HIT#
A[17]# HIT# H_HIT# [7]
H_A#18 U5 E4 H_HITM#
A[18]# HITM# H_HITM# [7]
H_A#19 R3 A[19]#

ADDR GROUP_1

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H_A#20 W6 AD4
H_A#21 A[20]# BPM[0]# +1.05V
U4 A[21]# BPM[1]# AD3
H_A#22 Y5 AD1 Layout:
A[22]# BPM[2]#

XDP/ITP SIGNALS
H_A#23 U1 AC4 Place R32 close to

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H_A#24 A[23]# BPM[3]# XDP_BPM#4 R674 54.9R_1 CPU with stub length
R4 A[24]# PRDY# AC2
H_A#25 T5 AC1 XDP_BPM#5 R32 54.9R_1 <200mils.
H_A#26 A[25]# PREQ# XDP_TCK
T3 A[26]# TCK AC5

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H_A#27 W2 AA6 XDP_TDI R35 54.9R_1
H_A#28 A[27]# TDI XDP_TDO R28 54.9R_1
W5 A[28]# TDO AB3 EC_PROCHOT [24,27]
H_A#29 Y4 AB5 XDP_TMS R23 54.9R_1
H_A#30 A[29]# TMS XDP_TRST#
U2 A[30]# TRST# AB6
H_A#31 V4 C20 XDP_DBRESET# R382 1K_1 +3.3V

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H_A#32 A[31]# DBR# R29 54.9R_1 R354 220K
W3 A[32]#
H_A#33 AA4 R24 54.9R_1

G
H_A#34 A[33]# R361 68R
AB2 A[34]# +1.05V
C H_A#35 AA3 THERMAL U13B C
A[35]# [7] H_D#[63:0] H_D#[63:0] [7]
H_ADSTB#1 V1 D21 H_PROCHOT# D S H_D#0 E22 Y22 H_D#32
[7] H_ADSTB#1 ADSTB[1]# PROCHOT# D[0]# D[32]#
Q43 FET-2N7002E H_D#1 F24 AB24 H_D#33
H_A20M# D[1]# D[33]#
A24 H_THERMDA H_D#2 V24 H_D#34

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[14] H_A20M# A6 A20M# THERMDA E26 D[2]# D[34]#

DATA GRP 0
H_FERR# A5 B25 H_THERMDC H_D#3 G22 V26 H_D#35
[14] H_FERR# FERR# THERMDC D[3]# D[35]#

DATA GRP 2
H_IGNNE# C4 H_D#4 F23 V23 H_D#36
[14] H_IGNNE# IGNNE# D[4]# D[36]#
C7 PM_THRMTRIP# H_D#5 G25 T22 H_D#37
THERMTRIP# PM_THRMTRIP# [7,14] D[5]# D[37]#
H_STPCLK# R378 0R H_STPCLK#_R D5 H_D#6 E25 U25 H_D#38
[14] H_STPCLK# STPCLK# D[6]# D[38]#

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H_INTR C6 H_D#7 E23 U23 H_D#39
[14] H_INTR LINT0 D[7]# D[39]#
H CLK
ICH

H_NMI B4 A22 CLK_CPU_BCLK H_D#8 K24 Y25 H_D#40


[14] H_NMI LINT1 BCLK[0] CLK_CPU_BCLK [13] D[8]# D[40]#
H_SMI# A3 A21 H_D#9 G24 W22 H_D#41
[14] H_SMI# SMI# BCLK[1] D[9]# D[41]#
H_D#10 Y23 H_D#42

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J24 D[10]# D[42]#
M4 H_D#11 J23 W24 H_D#43
RSVD[01] R371 H_D#12 D[11]# D[43]#
N5 RSVD[02] H22 D[12]# D[44]# W25 H_D#44
T2 @100R_1 H_D#13 F26 AA23 H_D#45
RSVD[03] H_D#14 D[13]# D[45]#
V3 RSVD[04] K22 D[14]# D[46]# AA24 H_D#46
B2 CLK_CPU_BCLK# H_D#15 H23 AB25 H_D#47
RESERVED

RSVD[05] CLK_CPU_BCLK# [13] D[15]# D[47]#

s
D2 H_DSTBN#0 J26 Y26 H_DSTBN#2
RSVD[06] [7] H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 [7]
D22 H_DSTBP#0 H26 AA26 H_DSTBP#2
RSVD[07] [7] H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 [7]
D3 H_DINV#0 H25 U22 H_DINV#2
RSVD[08] [7] H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 [7]
F6 +3.3V

e
RSVD[09]
[7] H_D#[63:0] H_D#[63:0] [7]
R372 @0R CPU_NC_B1 B1 Layout: H_D#16 N22 AE24 H_D#48
NC_B1 H_D#17 D[16]# D[48]#
Route H_THERMDA and H_THERMDC K25 D[17]# D[49]# AD24 H_D#49
on same layer w/10 mil trace & H_D#18 P26 AA21 H_D#50
D[18]# D[50]#

d
Penryn R385 10 mil spacing. Route away H_D#19 R23 AB22 H_D#51
H_D#20 D[19]# D[51]#
PGA-479-PZ47823A 0R from noise sources with ground L23 D[20]# D[52]# AB21 H_D#52

DATA GRP 1
C405 guard tracks on each side. H_D#21 M24 AC26 H_D#53

i
D[21]# D[53]#

DATA GRP 3
100nF/10V_X7R H_D#22 L22 AD20 H_D#54
H_D#23 D[22]# D[54]#
M23 D[23]# D[55]# AE22 H_D#55
H_D#24 P25 AF23 H_D#56
B H_D#25 D[24]# D[56]# B
U16 P23 AC25 H_D#57 Layout:

v
H_D#26 D[25]# D[57]#
P22 D[26]# D[58]# AE21 H_D#58 Comp0,2 connect with Zo=27.4ohm,
EC_SCLK_THM 8 1 Z0501 H_D#27 T24 AD21 H_D#59 make trace length shorter than 0.5".
[24] EC_SCLK_THM SMBCLK VDD D[27]# D[59]#
H_D#28 R24 AC22 H_D#60 Comp1,3 connect with Zo=55ohm, make
EC_SDATA_THM 7 Z0502 R374 0R H_D#29 D[28]# D[60]#
[24] EC_SDATA_THM SMBDATA DP 2 L25 D[29]# D[61]# AD23 H_D#61 trace length shorter than 0.5".

o
H_D#30 T25 AF22 H_D#62
PM_THRM# R398 0R NS_OS#/A0 Z0503 C398 H_D#31 D[30]# D[62]#
[8,15] PM_THRM# 6 ALERT DN 3 N25 D[31]# D[63]# AC23 H_D#63
2.2nF/50V_X7R R373 0R H_DSTBN#1 L26 AE25 H_DSTBN#3
[7] H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 [7]
R399 20K_1 5 4 H_DSTBP#1 M26 AF24 H_DSTBP#3

r
+3.3V GND THERM [7] H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 [7]
NS_T_CRIT# R384 7.5K_1 +3.3V H_DINV#1 N24 AC20 H_DINV#3
[7] H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 [7]
EMC1402 +1.05V R321 1K_1 H_GTLREF AD26 R26 COMP0 R339 27.4R_1
M-MSOP8 R375 @1K_1 CPU_TEST1 GTLREF COMP[0] COMP1 R332 54.9R_1
C23 TEST1 MISC COMP[1] U26
R365 @1K_1 CPU_TEST2 D25 AA1 COMP2 R31 27.4R_1

P
TEST2 COMP[2] COMP3 R34 54.9R_1
C24 TEST3 COMP[3] Y1
R320 2K_1 Layout: AF26
Zo=55 ohm, TEST4 H_DPRSTP#
AF1 TEST5 DPRSTP# E5 H_DPRSTP# [7,14,27]
@100nF/10V_X7R C323 0.5" max for A26 B5 H_DPSLP#
AUX_OFF# [26] TEST6 DPSLP# H_DPSLP# [14]
H_GTLREF. C3 D24 H_DPWR#
TEST7 DPWR# H_DPWR# [7]
CPU_BSEL0 B22 D6 H_PWRGD
C

[7] CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGD [14]


CPU_BSEL1 B23 D7 H_CPUSLP#
[7] CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# [7]
+1.05V R93 10K_1 Z0504 B Q11 CPU_BSEL2 C21 AE6 H_PSI#
[7] CPU_BSEL2 BSEL[2] PSI# H_PSI# [27]
TR-2N3904
C

Penryn R285 @10K_1 +1.05V


E

PM_THRMTRIP# Z0505 B Q10 C96 PGA-479-PZ47823A


TR-2N3904 1uF/10V_0603_X5R
R381
E

1K_1 C401
100nF/10V_X7R

A A

ECS COMPUTER CORP.


Title
CPU Penryn 1 of 2
Size Document Number Rev
A
3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 5 of 36
5 4 3 2 1
5 4 3 2 1

Vcc Core Decoupling 1760 mil / 44.0A +CPU_CORE +CPU_CORE 1760 mil / 44.0A Vcc Core Decoupling
U13C U13D
A7 VCC[001] VCC[068] AB20 A4 VSS[001] VSS[082] P6
Layout: A9 AB7 A8 P21
VCC[002] VCC[069] VSS[002] VSS[083]
Place these outside socket A10 AC7 A11 P24
VCC[003] VCC[070] VSS[003] VSS[084]

e
cavity on L8 (North side C36 C77 C76 C73 C72 A12 AC9 C74 C70 C93 C317 A14 R2
10uF/6.3V_0805_X5R 10uF/6.3V_0805_X5R 10uF/6.3V_0805_X5R 10uF/6.3V_0805_X5R @10uF/6.3V_0805_X5R VCC[004] VCC[071] 10uF/6.3V_0805_X5R 10uF/6.3V_0805_X5R 10uF/6.3V_0805_X5R 10uF/6.3V_0805_X5R VSS[004] VSS[085]
Secondary). A13 VCC[005] VCC[072] AC12 A16 VSS[005] VSS[086] R5
A15 VCC[006] VCC[073] AC13 A19 VSS[006] VSS[087] R22
A17 AC15 Layout: A23 R25

c
VCC[007] VCC[074] VSS[007] VSS[088]
A18 AC17 Place these inside socket AF2 T1
VCC[008] VCC[075] VSS[008] VSS[089]
A20 VCC[009] VCC[076] AC18 cavity on L8 (North side B6 VSS[009] VSS[090] T4
D Layout: B7 AD7 Secondary). B8 T23 D
VCC[010] VCC[077] VSS[010] VSS[091]
Place these outside socket B9 AD9 B11 T26
C94 C25 C35 VCC[011] VCC[078] C311 C356 C334 C71 VSS[011] VSS[092]

n
cavity on L8 ( South side B10 VCC[012] VCC[079] AD10 B13 VSS[012] VSS[093] U3
Secondary). @10uF/6.3V_0805_X5R 10uF/6.3V_0805_X5R 10uF/6.3V_0805_X5R B12 AD12 10uF/6.3V_0805_X5R 10uF/6.3V_0805_X5R 10uF/6.3V_0805_X5R 10uF/6.3V_0805_X5R B16 U6
VCC[013] VCC[080] VSS[013] VSS[094]
B14 VCC[014] VCC[081] AD14 B19 VSS[014] VSS[095] U21
B15 VCC[015] VCC[082] AD15 B21 VSS[015] VSS[096] U24

e
B17 VCC[016] VCC[083] AD17 B24 VSS[016] VSS[097] V2
B18 VCC[017] VCC[084] AD18 C5 VSS[017] VSS[098] V5
B20 VCC[018] VCC[085] AE9 C8 VSS[018] VSS[099] V22
C9 AE10 C11 V25

r
C399 C92 C352 C346 VCC[019] VCC[086] C337 C364 C336 C41 VSS[019] VSS[100]
C10 VCC[020] VCC[087] AE12 C14 VSS[020] VSS[101] W1
10uF/6.3V_0805_X5R @10uF/6.3V_0805_X5R @10uF/6.3V_0805_X5R @10uF/6.3V_0805_X5R C12 AE13 10uF/6.3V_0805_X5R 10uF/6.3V_0805_X5R 10uF/6.3V_0805_X5R 10uF/6.3V_0805_X5R C16 W4
VCC[021] VCC[088] VSS[021] VSS[102]
C13 VCC[022] VCC[089] AE15 C19 VSS[022] VSS[103] W23

e
C15 AE17 Layout: C2 W26
VCC[023] VCC[090] VSS[023] VSS[104]
C17 AE18 Place these inside socket C22 Y3
VCC[024] VCC[091] VSS[024] VSS[105]
C18 VCC[025] VCC[092] AE20 cavity on L8 (South side C25 VSS[025] VSS[106] Y6

f
D9 VCC[026] VCC[093] AF9 Secondary). D1 VSS[026] VSS[107] Y21
Layout: D10 AF10 D4 Y24
C357 C363 VCC[027] VCC[094] C26 C351 C345 C333 VSS[027] VSS[108]
Place these inside socket cavity D12 AF12 D8 AA2
10uF/6.3V_0805_X5R 10uF/6.3V_0805_X5R VCC[028] VCC[095] 10uF/6.3V_0805_X5R @10uF/6.3V_0805_X5R @10uF/6.3V_0805_X5R 10uF/6.3V_0805_X5R VSS[028] VSS[109]
on L8 (North side Primary). D14 AF14 D11 AA5

e
VCC[029] VCC[096] VSS[029] VSS[110]
D15 VCC[030] VCC[097] AF15 D13 VSS[030] VSS[111] AA8
D17 VCC[031] VCC[098] AF17 D16 VSS[031] VSS[112] AA11
D18 VCC[032] VCC[099] AF18 D19 VSS[032] VSS[113] AA14

r
E7 AF20 +1.05V D23 AA16
VCC[033] VCC[100] VSS[033] VSS[114]
E9 VCC[034] 180 mil / 4.5A D26 VSS[034] VSS[115] AA19
E10 VCC[035] VCCP[01] G21 CPU_G21 R370 0R_0603 E3 VSS[035] VSS[116] AA22
C42 C40 C39 C75 E12 V6 E6 AA25
10uF/6.3V_0805_X5R @10uF/6.3V_0805_X5R 10uF/6.3V_0805_X5R @10uF/6.3V_0805_X5R VCC[036] VCCP[02] VSS[036] VSS[117]
E13 J6 Vccp Core Decoupling E8 AB1

le
VCC[037] VCCP[03] VSS[037] VSS[118]
E15 VCC[038] VCCP[04] K6 E11 VSS[038] VSS[119] AB4
E17 VCC[039] VCCP[05] M6 + E14 VSS[039] VSS[120] AB8
E18 J21 C61 C50 C62 C84 E16 AB11
C VCC[040] VCCP[06] 100nF/10V_X7R 100nF/10V_X7R 100nF/10V_X7R 220uF/2V_7343_SPCAP VSS[040] VSS[121] C
E20 VCC[041] VCCP[07] K21 E19 VSS[041] VSS[122] AB13
F7 VCC[042] VCCP[08] M21 E21 VSS[042] VSS[123] AB16
Layout: F9 N21 E24 AB19
C38 C37 VCC[043] VCCP[09] VSS[043] VSS[124]

t
Place these inside socket cavity F10 N6 F5 AB23
10uF/6.3V_0805_X5R @10uF/6.3V_0805_X5R VCC[044] VCCP[10] Layout: VSS[044] VSS[125]
on L8 (South side Primary). F12 VCC[045] VCCP[11] R21 F8 VSS[045] VSS[126] AB26
F14 R6 C47 C43 C44 Place these inside F11 AC3
VCC[046] VCCP[12] 100nF/10V_X7R 100nF/10V_X7R 100nF/10V_X7R VSS[046] VSS[127]
F15 VCC[047] VCCP[13] T21 socket cavity on L8 ( F13 VSS[047] VSS[128] AC6
F17 VCC[048] VCCP[14] T6 North side Secondary). F16 VSS[048] VSS[129] AC8

n
F18 VCC[049] VCCP[15] V21 F19 VSS[049] VSS[130] AC11
F20 W21 +1.5V F2 AC14
VCC[050] VCCP[16] L45 VSS[050] VSS[131]
AA7 VCC[051] 10 mil / 0.13A F22 VSS[051] VSS[132] AC16
B26 +VCCA_PROC

I
+ + + + AA9 VCC[052] VCCA[01] F25 VSS[052] VSS[133] AC19
C88 C403 C90 C402 AA10 C26 HCB1608KF-600T30_0603 G4 AC21
@330uF/2V_7343_SPCAP 330uF/2V_7343_SPCAP 330uF/2V_7343_SPCAP @330uF/2V_7343_SPCAP VCC[053] VCCA[02] VSS[053] VSS[134]
AA12 VCC[054] G1 VSS[054] VSS[135] AC24
AA13 AD6 H_VID0 C384 C381 G23 AD2
VCC[055] VID[0] H_VID0 [12] VSS[055] VSS[136]
AA15 AF5 H_VID1 10nF/25V_X7R 10uF/6.3V_0805_X5R G26 AD5
VCC[056] VID[1] H_VID1 [12] VSS[056] VSS[137]
AA17 AE5 H_VID2 H3 AD8
VCC[057] VID[2] H_VID2 [12] VSS[057] VSS[138]

s
AA18 AF4 H_VID3 Layout: H6 AD11
VCC[058] VID[3] H_VID3 [12] VSS[058] VSS[139]
AA20 AE3 H_VID4 Place C5 H21 AD13
VCC[059] VID[4] H_VID4 [12] VSS[059] VSS[140]
AB9 AF3 H_VID5 near pin-B26. H24 AD16
VCC[060] VID[5] H_VID5 [12] VSS[060] VSS[141]
AC10 AE2 H_VID6 J2 AD19

e
VCC[061] VID[6] H_VID6 [12] VSS[061] VSS[142]
AB10 VCC[062] J5 VSS[062] VSS[143] AD22
AB12 R43 100R_1 +CPU_CORE R22 @0R EC_CPUVSENSE J22 AD25
VCC[063] EC_CPUVSENSE [24] VSS[063] VSS[144]
AB14 VCC[064] J25 VSS[064] VSS[145] AE1
AB15 VCC[065] VCCSENSE AF7 VCCSENSE VCCSENSE [27] K1 VSS[065] VSS[146] AE4

d
AB17 VCC[066] K4 VSS[066] VSS[147] AE8
AB18 VCC[067] VSSSENSE AE7 VSSSENSE VSSSENSE [27] K23 VSS[067] VSS[148] AE11
K26 AE14

i
Penryn R47 100R_1 Layout: VSS[068] VSS[149]
L3 VSS[069] VSS[150] AE16
PGA-479-PZ47823A . Route VCCSENSE and VSSSENSE traces L6 AE19
VSS[070] VSS[151]
at 27.4 Ohms with 50 mil spacing. L21 VSS[071] VSS[152] AE23
B B
Place PU and PD within 1 inch of CPU. L24 AE26

v
+0.9V_DDR +0.9V_DDR VSS[072] VSS[153]
M2 A2

M_B_A6
RN3 8P4R_56R
C275 100nF/10V_X7R
DDR2 M_B_A3
RN9 8P4R_56R
C285 100nF/10V_X7R
M5
M22
VSS[073]
VSS[074]
VSS[075]
VSS[154]
VSS[155]
VSS[156]
AF6
AF8
8 1 1 8 M25 AF11
THRMINATION VSS[076] VSS[157]

o
M_B_A7 7 2 Layout: M_A_A6 2 7 Layout: N1 AF13
M_A_BS2 M_B_A5 VSS[077] VSS[158]
[8,11] M_A_BS2 6 3 Place one cap 3 6 Place one cap N4 AF16
M_B_A11 C276 100nF/10V_X7R M_B_A8 C286 100nF/10V_X7R VSS[078] VSS[159]
5 4 close to every 4 5 close to every N23 VSS[079] VSS[160] AF19
2 pullup 2 pullup N26 AF21

r
RN2 8P4R_56R RN8 8P4R_56R VSS[080] VSS[161]
resistors resistors P3 VSS[081] VSS[162] A25
M_ODT1 8 1 C254 100nF/10V_X7R terminated to M_B_A9 1 8 C252 100nF/10V_X7R terminated to AF25
[7,11] M_ODT1 VSS[163]
M_CS#1 7 2 +0.9V_DDR. M_B_A12 2 7 +0.9V_DDR.
[7,11] M_CS#1
M_A_CAS# 6 3 M_A_A11 3 6 Penryn
[8,11] M_A_CAS#
M_B_A13 5 4 C253 100nF/10V_X7R M_A_A7 4 5 C251 100nF/10V_X7R PGA-479-PZ47823A .

P
RN1 8P4R_56R RN7 8P4R_56R
M_A_A5 1 8 C277 100nF/10V_X7R M_B_BS2 1 8 C250 100nF/10V_X7R
[8,11] M_B_BS2
M_A_A8 2 7 M_CKE1 2 7
[7,11] M_CKE1
M_A_A9 3 6 M_A_A14 3 6
M_A_A12 4 5 C278 100nF/10V_X7R M_CKE2 4 5 C249 100nF/10V_X7R
[7,11] M_CKE2
RN4 8P4R_56R RN10 8P4R_56R
M_B_BS1 8 1 C243 100nF/10V_X7R M_A_A2 1 8 C279 100nF/10V_X7R
[8,11] M_B_BS1
M_B_A0 7 2 M_A_A4 2 7
M_B_A2 6 3 M_B_A10 3 6
M_B_A4 5 4 C244 100nF/10V_X7R M_B_A1 4 5 C280 100nF/10V_X7R

RN12 8P4R_56R RN6 8P4R_56R


M_A_RAS# 1 8 C245 100nF/10V_X7R M_ODT2 8 1 C281 100nF/10V_X7R
[8,11] M_A_RAS# [7,11] M_ODT2
M_CS#0 2 7 M_A_WE# 7 2
[7,11] M_CS#0 [8,11] M_A_WE#
M_CS#3 3 6 M_A_BS0 6 3
A [7,11] M_CS#3 [8,11] M_A_BS0 A
M_B_CAS# 4 5 C246 100nF/10V_X7R M_A_A10 5 4 C282 100nF/10V_X7R
[8,11] M_B_CAS#
RN11 8P4R_56R RN5 8P4R_56R
M_A_A0 1 8 C247 100nF/10V_X7R M_CS#2 8 1 C287 100nF/10V_X7R
[7,11] M_CS#2
M_A_BS1 2 7 M_B_RAS# 7 2
[8,11] M_A_BS1 [8,11] M_B_RAS#
[8,11] M_B_WE#
M_B_WE#
M_B_BS0
3
4
6
5 C248 100nF/10V_X7R
M_A_A1
M_A_A3
6
5
3
4 C288 100nF/10V_X7R
ECS COMPUTER CORP.
[8,11] M_B_BS0
M_CKE3 R274 56R C11 100nF/10V_X7R M_CKE0 R276 56R C283 100nF/10V_X7R Title
[7,11] M_CKE3 [7,11] M_CKE0
M_B_A14
M_A_A13
R275
R284
56R
56R C12 100nF/10V_X7R
[7,11] M_ODT3
M_ODT3
M_ODT0
R282
R283
56R
56R C284 100nF/10V_X7R
CPU Penryn 2 of 2
[7,11] M_ODT0 Size Document Number Rev
A
[8,11] M_A_A[14:0] [8,11] M_B_A[14:0]
3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 6 of 36
5 4 3 2 1
5 4 3 2 1

DMI X2 Select
U14B U14A
H_A#[35:3] [5]
A14 H_A#3
[5] H_D#[63:0] H_A#_3
MCH_CFG_5 Low = DMIx2 M36 RSVD1 SA_CK_0 AP24 M_CLK_DDR0 M_CLK_DDR0 [11]
H_D#0 F2 H_D#_0 H_A#_4 C15 H_A#4
High = DMIx4 DEFAULT N36 RSVD2 SA_CK_1 AT21 M_CLK_DDR1 M_CLK_DDR1 [11]
H_D#1 G8 H_D#_1 H_A#_5 F16 H_A#5
R33 RSVD3 SB_CK_0 AV24 M_CLK_DDR2 M_CLK_DDR2 [11]
H_D#2 F8 H_D#_2 H_A#_6 H13 H_A#6
T33 RSVD4 SB_CK_1 AU20 M_CLK_DDR3 M_CLK_DDR3 [11]
H_D#3 E6 H_D#_3 H_A#_7 C18 H_A#7

e
iTPM Host Interface AH9 H_D#4 G2 M16 H_A#8
RSVD5 H_D#_4 H_A#_8

DDR CLK/CONTROL/COMPENSATION
AH10 RSVD6 SA_CK#_0 AR24 M_CLK_DDR#0 M_CLK_DDR#0 [11]
H_D#5 H6 H_D#_5 H_A#_9 J13 H_A#9
AH12 RSVD7 SA_CK#_1 AR21 M_CLK_DDR#1 M_CLK_DDR#1 [11]
H_D#6 H2 H_D#_6 H_A#_10 P16 H_A#10
MCH_CFG_6 Low = iTPM Host Interface is enabled AH13 AU24 M_CLK_DDR#2 H_D#7 F6 R16 H_A#11

c
RSVD8 SB_CK#_0 M_CLK_DDR#2 [11] H_D#_7 H_A#_11
High = iTPM Host Interface is Disabled K12 RSVD9 SB_CK#_1 AV20 M_CLK_DDR#3 M_CLK_DDR#3 [11]
H_D#8 D4 H_D#_8 H_A#_12 N17 H_A#12
DEFAULT H_D#9 H3 M13 H_A#13
H_D#_9 H_A#_13
D
SA_CKE_0 BC28 M_CKE0 M_CKE0 [6,11]
H_D#10 M9 H_D#_10 H_A#_14 E17 H_A#14 D
ME TLS Confidentiality (Isolation Bypass Enable) SA_CKE_1 AY28 M_CKE1 M_CKE1 [6,11]
H_D#11 M11 H_D#_11 H_A#_15 P17 H_A#15
AY36 M_CKE2 H_D#12 H_A#16

n
SB_CKE_0 M_CKE2 [6,11] J1 H_D#_12 H_A#_16 F17
T24 RSVD14 SB_CKE_1 BB36 M_CKE3 M_CKE3 [6,11]
H_D#13 J2 H_D#_13 H_A#_17 G20 H_A#17
MCH_CFG_7 Low = AMT Firmware will use TLS cipher H_D#14 N12 B19 H_A#18
H_D#_14 H_A#_18

RSVD
suite with no confidentiality B31 RSVD15 SA_CS#_0 BA17 M_CS#0 M_CS#0 [6,11]
H_D#15 J6 H_D#_15 H_A#_19 J16 H_A#19

e
SA_CS#_1 AY16 M_CS#1 M_CS#1 [6,11]
H_D#16 P2 H_D#_16 H_A#_20 E20 H_A#20
High = AMT Firmware will use TLS cipher M1 RSVD17 SB_CS#_0 AV16 M_CS#2 M_CS#2 [6,11]
H_D#17 L2 H_D#_17 H_A#_21 H16 H_A#21
suite with Confidentiality SB_CS#_1 AR13 M_CS#3 M_CS#3 [6,11]
H_D#18 R2 H_D#_18 H_A#_22 J20 H_A#22
DEFAULT H_D#19 N9 L17 H_A#23

r
H_D#_19 H_A#_23
AY21 RSVD20 SA_ODT_0 BD17 M_ODT0 M_ODT0 [6,11]
H_D#20 L6 H_D#_20 H_A#_24 A17 H_A#24
FSB Frequency Select: MCH_CFG[0:2] SA_ODT_1 AY17 M_ODT1 M_ODT1 [6,11]
H_D#21 M5 H_D#_21 H_A#_25 B17 H_A#25
SB_ODT_0 BF15 M_ODT2 M_ODT2 [6,11]
H_D#22 J3 H_D#_22 H_A#_26 L16 H_A#26

e
CPU Driven 1066 800 667 B2 RSVD21 SB_ODT_1 AY13 M_ODT3 M_ODT3 [6,11]
H_D#23 N2 H_D#_23 H_A#_27 C21 H_A#27
BG23 H_D#24 R1 J17 H_A#28
RSVD22 H_D#_24 H_A#_28
RFS0 = 0R RFS0 = @0R RFS0 = @0R RFS0 = @0R BF23 RSVD23 SM_RCOMP BG22 SM_RCOMP R298 80.6R_1 +1.8V_DDR H_D#25 N5 H_D#_25 H_A#_29 H20 H_A#29

f
FSB RFS1 = 0R RFS1 = @0R RFS1 = @0R RFS1 = @0R BH18 RSVD24 SM_RCOMP# BH21 SM_RCOMP# R299 @20R_1 H_D#26 N6 H_D#_26 H_A#_30 B18 H_A#30
BF18 R309 @20R_1 H_D#27 P13 K17 H_A#31
Speed RFS2 = 0R RFS2 = @0R RFS2 = @0R RFS2 = @0R RSVD25 R310 80.6R_1 H_D#28 H_D#_27 H_A#_31 H_A#32
N8 H_D#_28 H_A#_32 B20
(MT/s) RFSA = @56R RFSA = @56R RFSA = @56R RFSA = 56R BF28 SM_RCOMP_VOH R293 1K_0.1 H_D#29 L7 F21 H_A#33
+1.8V_DDR

e
SM_RCOMP_VOH H_D#30 H_D#_29 H_A#_33 H_A#34
RFSB = @0R RFSB = 0R RFSB = @0R RFSB = @0R N10 H_D#_30 H_A#_34 K21
C292 C302 H_D#31 M3 L20 H_A#35
RFSC = @0R RFSC = 0R RFSC = 0R RFSC = 0R R300 10nF/25V_X7R 2.2uF/10V_0603_X5R H_D#32 Y3
H_D#_31 H_A#_35
H_D#_32

r
DEFAULT 3.01K_1 H_D#33 AD14 H12 H_ADS#
H_D#_33 H_ADS# H_ADS# [5]
C293 C299 H_D#34 Y6 B16 H_ADSTB#0
H_D#_34 H_ADSTB#_0 H_ADSTB#0 [5]
CPU_BSEL0 BH28 SM_RCOMP_VOL 10nF/25V_X7R 2.2uF/10V_0603_X5R H_D#35 Y10 G17 H_ADSTB#1
[5] CPU_BSEL0 SM_RCOMP_VOL H_D#_35 H_ADSTB#_1 H_ADSTB#1 [5]

ME JTAG
CPU_BSEL1 R301 1K_0.1 H_D#36 Y12 A9 H_BNR#
[5] CPU_BSEL1 H_D#_36 H_BNR# H_BNR# [5]
CPU_BSEL2 AL34 H_D#37 Y14 F11 H_BPRI#

le
[5] CPU_BSEL2 ME_JTAG_TCK M_VREF_MCH [11] H_D#_37 H_BPRI# H_BPRI# [5]
AV42 M_VREF_MCH R327 @1K_1 +1.8V_DDR H_D#38 Y7 G12 H_BREQ#
H_BREQ# [5]

HOST
SM_VREF R335 @1K_1 H_D#39 H_D#_38 H_BREQ# H_DEFER#
AK34 ME_JTAG_TDI W2 H_D#_39 H_DEFER# E9 H_DEFER# [5]
NOTE: RFS2 RFS1 RFS0 H_D#40 AA8 B10 H_DBSY#
H_D#_40 H_DBSY# H_DBSY# [5]
C
MCH_CFG0:2 CPU Driven. R450 R440 R433 AN35 AR36 SM_PWROK R342 @0R DDR_PWROK
DDR_PWROK [29]
H_D#41 Y9 AH7 CLK_MCH_BCLK
CLK_MCH_BCLK [13]
C
ME_JTAG_TDO SM_PWROK H_D#_41 HPLL_CLK
(Default) 0R 0R 0R
SM_REXT BF17 SM_REXT H_D#42 AA13 H_D#_42 HPLL_CLK# AH6 CLK_MCH_BCLK#
CLK_MCH_BCLK# [13]
000 = FSB1066 AM35 ME_JTAG_TMS SM_DRAMRST# BC36 SM_DRAMRST# TP16
SM_PWROK H_D#43 AA9 H_D#_43 H_DPWR# J11 H_DPWR#
H_DPWR# [5]
RFSA NOTE: H_D#44 H_DRDY#

t
010 = FSB800 AA11 H_D#_44 H_DRDY# F9 H_DRDY# [5]
R432 @56R +1.05V SM_DRAMRST# Would be needed for DDR3 only. H_D#45 AD11 H9 H_HIT#
110 = FSB667 H_D#_45 H_HIT# H_HIT# [5]
R431 1K_1 R312 C344 H_D#46 AD10 E12 H_HITM#
H_D#_46 H_HITM# H_HITM# [5]
B38 DREFCLK 499R_1 @100nF/10V_X7R H_D#47 AD13 H11 H_LOCK#
DPLL_REF_CLK DREFCLK [13] H_D#_47 H_LOCK# H_LOCK# [5]
CLK_BSEL0 R430 1K_1 MCH_CFG_0 T25 A38 DREFCLK# H_D#48 AE12 C9 H_TRDY#
[13] CLK_BSEL0 CFG_0 DPLL_REF_CLK# DREFCLK# [13] H_D#_48 H_TRDY# H_TRDY# [5]

n
CLK_BSEL1 R437 1K_1 MCH_CFG_1 R25 E41 DREFSSCLK H_D#49 AE9
[13] CLK_BSEL1 CFG_1 DPLL_REF_SSCLK DREFSSCLK [13] H_D#_49

CLK
CLK_BSEL2 R447 1K_1 MCH_CFG_2 P25 F41 DREFSSCLK# SM_PWROK H_D#50 AA2
[13] CLK_BSEL2 CFG_2 DPLL_REF_SSCLK# DREFSSCLK# [13] H_D#_50
RFSB H_D#51 AD8 H_D#_51
R438 @0R R439 1K_1 F43 CLK_PCIE_3GPLL H_D#52

I
+1.05V PEG_CLK CLK_PCIE_3GPLL [13] AA3 H_D#_52
R448 @0R R449 1K_1 E43 CLK_PCIE_3GPLL# H_D#53 AD3 J8 H_DINV#0
PEG_CLK# CLK_PCIE_3GPLL# [13] H_D#_53 H_DINV#_0 H_DINV#0 [5]
RFSC P20 R347 H_D#54 AD7 L3 H_DINV#1
CFG_3 H_D#_54 H_DINV#_1 H_DINV#1 [5]
P24 10K_1 H_D#55 AE14 Y13 H_DINV#2
CFG_4 H_D#_55 H_DINV#_2 H_DINV#2 [5]
R414 @2.21K_1 MCH_CFG_5 C25 H_D#56 AF3 Y1 H_DINV#3
CFG_5 DMI_TXN[3:0] [15] H_D#_56 H_DINV#_3 H_DINV#3 [5]
R92 @2.21K_1 MCH_CFG_6 N24 AE41 DMI_TXN0 H_D#57 AC1
CFG_6 DMI_RXN_0 H_D#_57

s
CFG

R73 @2.21K_1 MCH_CFG_7 M24 AE37 DMI_TXN1 H_D#58 AE3 L10 H_DSTBN#0
CFG_7 DMI_RXN_1 H_D#_58 H_DSTBN#_0 H_DSTBN#0 [5]
E21 CFG_8 DMI_RXN_2 AE47 DMI_TXN2 H_D#59 AC3 H_D#_59 H_DSTBN#_1 M7 H_DSTBN#1
H_DSTBN#1 [5]
R426 @2.21K_1 MCH_CFG_9 C23 AH39 DMI_TXN3 H_D#60 AE11 AA5 H_DSTBN#2
CFG_9 DMI_RXN_3 H_D#_60 H_DSTBN#_2 H_DSTBN#2 [5]
R419 @2.21K_1 MCH_CFG_10 C24 H_D#61 AE8 AE6 H_DSTBN#3

e
CFG_10 DMI_TXP[3:0] [15] H_D#_61 H_DSTBN#_3 H_DSTBN#3 [5]
N21 CFG_11 DMI_RXP_0 AE40 DMI_TXP0 H_D#62 AG2 H_D#_62
NOTE: R74 @2.21K_1 MCH_CFG_12 P21 AE38 DMI_TXP1 H_D#63 AD6 L9 H_DSTBP#0
CFG_12 DMI_RXP_1 H_D#_63 H_DSTBP#_0 H_DSTBP#0 [5]
Only one of the CFG10/ R69 @2.21K_1 MCH_CFG_13 T21 AE48 DMI_TXP2 M8 H_DSTBP#1
CFG_13 DMI_RXP_2 H_DSTBP#_1 H_DSTBP#1 [5]
DMI

CFG12/ CFG13 straps can R20 CFG_14 DMI_RXP_3 AH40 DMI_TXP3 +1.05V R401 221R_1 H_SWING C5 H_SWING H_DSTBP#_2 AA6 H_DSTBP#2
H_DSTBP#2 [5]

d
be enabled at any time. M20 R393 100R_1 AE5 H_DSTBP#3
CFG_15 DMI_RXN[3:0] [15] H_DSTBP#_3 H_DSTBP#3 [5]
R81 @2.21K_1 MCH_CFG_16 L21 AE35 DMI_RXN0 E3
CFG_16 DMI_TXN_0 H_RCOMP H_REQ#[4:0] [5]
H21 AE43 DMI_RXN1 C415 100nF/10V_X7R B15 H_REQ#0

i
CFG_17 DMI_TXN_1 H_REQ#_0
P29 CFG_18 DMI_TXN_2 AE46 DMI_RXN2 Layout:
H_REQ#_1 K13 H_REQ#1
+3.3V R75 @4.02K_1 MCH_CFG_19 R28 AH42 DMI_RXN3 H_RCOMP Trace R387 24.9R_1H_RCOMP F13 H_REQ#2
R71 @4.02K_1 MCH_CFG_20 CFG_19 DMI_TXN_3 width 10~20mil. H_REQ#_2 H_REQ#3
T28 CFG_20 DMI_RXP[3:0] [15] H_REQ#_3 B13
B B
AD35 DMI_RXP0 H_CPURST# C12 B14 H_REQ#4

v
DMI_TXP_0 [5] H_CPURST# H_CPURST# H_REQ#_4
Layout:
DMI_TXP_1 AE44 DMI_RXP1 [5] H_CPUSLP#
H_CPUSLP# E11 H_CPUSLP# H_RS#[2:0] [5]
Location of all MCH_CFG strap resistors
DMI_TXP_2 AF46 DMI_RXP2 H_RS#_0 B6 H_RS#0
needs to be close to trace to minimize stub. DMI_TXP_3 AH43 DMI_RXP3 H_RS#_1 F12 H_RS#1
+1.05V R402 1K_1 H_AVREF A11 C8 H_RS#2
H_AVREF H_RS#_2

o
PM_SYNC# R395 0R PM_SYNC#_R R29
[15] PM_SYNC# PM_SYNC#
H_DPRSTP# R412 0R PM_DPRSTP# B7 R392 2K_1 H_DVREF B11
[5,14,27] H_DPRSTP# PM_DPRSTP# H_DVREF
GRAPHICS

PM_EXTTS#0_EC N33 B33 GFXVR_VID_0


PM_EXT_TS#_0 GFX_VID_0 GFXVR_VID_0 [28]
TS#DIMM0_1 P32 B32 GFXVR_VID_1 R391 0R CANTIGA_1p2

r
[8,11] TS#DIMM0_1 PM_EXT_TS#_1 GFX_VID_1 GFXVR_VID_1 [28]
PM

DELAY_VR_PWRGOODAT40 G33 GFXVR_VID_2 PBGA1329-CANTIGA


[15,27] DELAY_VR_PWRGOOD PWROK GFX_VID_2 GFXVR_VID_2 [28]
BUF_PLT_RST# R330 100R_1 PLT_RST#_R AT11 F33 GFXVR_VID_3 FSB Dynamic ODT
[14,17,21,23,24] BUF_PLT_RST# RSTIN# GFX_VID_3 GFXVR_VID_3 [28]
PM_THRMTRIP# R89 0R THERMTRIP#_R T20 E33 GFXVR_VID_4
[5,14] PM_THRMTRIP# THERMTRIP# GFX_VID_4 GFXVR_VID_4 [28]
PM_DPRSLPVR R103 0R DPRSLPVR_R R32
VID

[15,27] PM_DPRSLPVR DPRSLPVR


C34 GFXVR_EN MCH_CFG_16 Low = Dynamic ODT Disabled

P
GFX_VR_EN GFXVR_EN [24]
High = Dynamic ODT Enabled DEFAULT

+3.3V R386 10K_1 PM_EXTTS#0_EC BG48 NC_1


BF48 NC_2 CL_CLK AH37 CL_CLK0 CL_CLK0 [15] DMI Lane Reversal
R72 10K_1 TS#DIMM0_1 BD48 AH36 CL_DATA0
NC_3 CL_DATA CL_DATA0 [15]
BC48 AN36 MPWROK
ME

NC_4 CL_PWROK MPWROK [15,24]


R102 @10K_1 PM_DPRSLPVR BH47 AJ35 CL_RST#0 MCH_CFG_19 Low = Normal
NC_5 CL_RST# CL_RST#0 [15]
BG47 NC_6 CL_VREF AH34 MCH_CLVREF_R R350 1K_1 +1.05V High = Lanes Reversed DEFAULT
PCI Express Graphics Lane BE47 R352 511R_1
NC_7
BH46 NC_8
BF46 C355 100nF/10V_X7R Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIe
NC_9
NC

MCH_CFG_9 Low = Reverse Lane BG45 N28 R487 @4.02K_1


DEFAULT NC_10 DDPC_CTRLCLK DDPC_CTRLDATA R80 @4.02K_1
High = Normal operation BH44 NC_11 DDPC_CTRLDATA M28 +3.3V
BH43 G36 SDVO_CTRLCLK MCH_CFG_20 Low = Only Digital Display Port (SDVO/DP/
NC_12 SDVO_CTRLCLK [12]
MISC

SDVO_CTRLCLK SDVO_CTRLDATA R101 10K_1


BH6 NC_13 SDVO_CTRLDATA E36
CLK_MCH_OE#
SDVO_CTRLDATA [12] +3.3V iHDMI) or PCIE or is operational DEFAULT
PCIE Loopback enable BH5 NC_14 CLKREQ# K36 CLK_MCH_OE# [13]
BG4 H36 MCH_ICH_SYNC# High = Digital Display Port (SDVO/DP/iHDMI) and
A NC_15 ICH_SYNC# MCH_ICH_SYNC# [15] A
BH3 NC_16 PCIE are operating simultaneously via PEG
MCH_CFG_10 Low = Enabled BF3 NC_17 TSATN# B12 MCH_TSATN# R416 54.9R_1 +1.05V
High = Disabled DEFAULT BH2 port
NC_18
BG2 NC_19
BE2 NC_20
XOR / ALLZ / Clock Un-gating BG1
BF1
NC_21 HDA_BCLK B28
B30
ECS COMPUTER CORP.
NC_22 HDA_RST#
HDA

MCH_CFG_12 MCH_CFG_13 Configuration BD1 NC_23 HDA_SDI B29


BC1 C29 Title
NC_24 HDA_SDO
0 0 Reserved F1 NC_25 HDA_SYNC A28 NB Cantiga 1 of 4
0 1 XOR Mode Enabled
1 0 All-Z Mode Enabled Size Document Number Rev
A
1 1 Normal operation DEFAULT CANTIGA_1p2
PBGA1329-CANTIGA
3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 7 of 36
5 4 3 2 1
5 4 3 2 1

U14D
[11] M_A_DQ[63:0]
M_A_DQ0 AJ38 BD21 M_A_BS0
SA_DQ_0 SA_BS_0 M_A_BS0 [6,11] +1.05V
M_A_DQ1 AJ41 BG18 M_A_BS1
SA_DQ_1 SA_BS_1 M_A_BS1 [6,11]
M_A_DQ2 AN38 AT25 M_A_BS2
SA_DQ_2 SA_BS_2 M_A_BS2 [6,11]
M_A_DQ3 AM38
M_A_DQ4 SA_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 M_A_RAS# M_A_RAS# [6,11]
U14C
M_A_DQ5 AJ40 BD20 M_A_CAS#
M_A_DQ6 AM44
SA_DQ_5
SA_DQ_6
SA_CAS#
SA_WE# AY20 M_A_WE#
M_A_CAS# [6,11]
M_A_WE# [6,11] LVDS R64

e
M_A_DQ7 AM42 L32 49.9R_1
M_A_DQ8 SA_DQ_7 L_BKLT_EN L_BKLT_CTRL
AN43 SA_DQ_8 M_A_DM[7:0] [11] [18] L_BKLT_EN G32 L_BKLT_EN

GRAPHICS
M_A_DQ9 AN44 AM37 M_A_DM0 T37 Z0801
M_A_DQ10 SA_DQ_9 SA_DM_0 PEG_COMPI
AU40 AT41 M_A_DM1 M32 T36

c
M_A_DQ11 SA_DQ_10 SA_DM_1 L_CTRL_CLK PEG_COMPO
AT38 SA_DQ_11 SA_DM_2 AY41 M_A_DM2 M33 L_CTRL_DATA
M_A_DQ12 AN41 AU39 M_A_DM3
M_A_DQ13 SA_DQ_12 SA_DM_3
D AN39 SA_DQ_13 SA_DM_4 BB12 M_A_DM4 [18] LVDS_DDC_CLK
LVDS_DDC_CLK K33
L_DDC_CLK PEG_RX#_0 H44 D
M_A_DQ14 AU44 AY6 M_A_DM5 LVDS_DDC_DATA J33 J46
SA_DQ_14 SA_DM_5 [18] LVDS_DDC_DATA L_DDC_DATA PEG_RX#_1
M_A_DQ15 AT7 M_A_DM6

n
AU42 SA_DQ_15 SA_DM_6 PEG_RX#_2 L44
M_A_DQ16 AV39 AJ5 M_A_DM7 LVDS_VDD_EN R394 0R L_VDD_EN_R M29 L40
SA_DQ_16 SA_DM_7 [18] LVDS_VDD_EN L_VDD_EN PEG_RX#_3
M_A_DQ17 AY44 N41
SA_DQ_17 M_A_DQS[7:0] [11] PEG_RX#_4

A
M_A_DQ18 BA40 AJ44 M_A_DQS0 R390 2.37K_1LVDS_IBG C44 P48
SA_DQ_18 SA_DQS_0 LVDS_IBG PEG_RX#_5

e
M_A_DQ19 BD43 AT44 M_A_DQS1 LVDS_VBG B43 N44
SA_DQ_19 SA_DQS_1 TP17 LVDS_VBG PEG_RX#_6
M_A_DQ20 AV41 BA43 M_A_DQS2 E37 T43
M_A_DQ21 SA_DQ_20 SA_DQS_2 LVDS_VREFH PEG_RX#_7
AY43 SA_DQ_21 SA_DQS_3 BC37 M_A_DQS3 E38 LVDS_VREFL PEG_RX#_8 U43
M_A_DQ22 BB41 AW12M_A_DQS4 LVDSA_CLK# C41 Y43

r
SA_DQ_22 SA_DQS_4 [18] LVDSA_CLK# LVDSA_CLK# PEG_RX#_9

MEMORY
M_A_DQ23 BC8 M_A_DQS5 LVDSA_CLK

PCI-EXPRESS
BC40 SA_DQ_23 SA_DQS_5 [18] LVDSA_CLK C40 LVDSA_CLK PEG_RX#_10 Y48
M_A_DQ24 AY37 AU8 M_A_DQS6 LVDSB_CLK# B37 Y36
SA_DQ_24 SA_DQS_6 [18] LVDSB_CLK# LVDSB_CLK# PEG_RX#_11 +3.3V
M_A_DQ25 BD38 AM7 M_A_DQS7 LVDSB_CLK A37 AA43
SA_DQ_25 SA_DQS_7 [18] LVDSB_CLK LVDSB_CLK PEG_RX#_12

e
M_A_DQ26 AV37 AD37
SA_DQ_26 M_A_DQS#[7:0] [11] PEG_RX#_13
M_A_DQ27 AT36 AJ43 M_A_DQS#0 LVDSA_DATA#0 H47 AC47
SA_DQ_27 SA_DQS#_0 [18] LVDSA_DATA#0 LVDSA_DATA#_0 PEG_RX#_14
M_A_DQ28 AY38 AT43 M_A_DQS#1 LVDSA_DATA#1 E46 AD39
SA_DQ_28 SA_DQS#_1 [18] LVDSA_DATA#1 LVDSA_DATA#_1 PEG_RX#_15

f
M_A_DQ29 BB38 BA44 M_A_DQS#2 LVDSA_DATA#2 G40
SA_DQ_29 SA_DQS#_2 [18] LVDSA_DATA#2 LVDSA_DATA#_2
M_A_DQ30 AV36 BD37 M_A_DQS#3 A40 H43 R77
M_A_DQ31 SA_DQ_30 SA_DQS#_3 LVDSA_DATA#_3 PEG_RX_0
AW36 SA_DQ_31 SA_DQS#_4 AY12 M_A_DQS#4 NOTE:
PEG_RX_1 J44 20K_1
M_A_DQ32 BD13 BD8 M_A_DQS#5 All LVDS data signals LVDSA_DATA0 H48 L43

e
SA_DQ_32 SA_DQS#_5 [18] LVDSA_DATA0 LVDSA_DATA_0 PEG_RX_2
M_A_DQ33 AU11 AU9 M_A_DQS#6 and its compliments LVDSA_DATA1 D45 L41 TMDS_B_HDP#
SA_DQ_33 SA_DQS#_6 [18] LVDSA_DATA1 LVDSA_DATA_1 DVIB_HDP#/PEG_RX_3
M_A_DQ34 BC11 AM8 M_A_DQS#7 SHOULD BE ROUTED LVDSA_DATA2 F40 N40 Q9

D
SA_DQ_34 SA_DQS#_7 [18] LVDSA_DATA2 LVDSA_DATA_2 PEG_RX_4
M_A_DQ35 BA12 DIFFERENTIALLY. B40 P47 FET-2N7002E
SYSTEM
SA_DQ_35 M_A_A[14:0] [6,11] LVDSA_DATA_3 PEG_RX_5

r
M_A_DQ36 AU13 BA21 M_A_A0 N43
M_A_DQ37 SA_DQ_36 SA_MA_0 PEG_RX_6
AV13 SA_DQ_37 SA_MA_1 BC24 M_A_A1 [18] LVDSB_DATA#0
LVDSB_DATA#0 A41
LVDSB_DATA#_0 DVIC_HDP#/PEG_RX_7 T42 R76 G
M_A_DQ38 BD12 BG24 M_A_A2 LVDSB_DATA#1 H38 U42 7.5K_1
[18] LVDSB_DATA#1

S
M_A_DQ39 SA_DQ_38 SA_MA_2 LVDSB_DATA#_1 PEG_RX_8
BC12 SA_DQ_39 SA_MA_3 BH24 M_A_A3 [18] LVDSB_DATA#2
LVDSB_DATA#2 G37
LVDSB_DATA#_2 PEG_RX_9 Y42
M_A_DQ40 BB9 BG25 M_A_A4 J37 W47 R90 20K_1

le
M_A_DQ41 SA_DQ_40 SA_MA_4 LVDSB_DATA#_3 PEG_RX_10
BA9 SA_DQ_41 SA_MA_5 BA24 M_A_A5 PEG_RX_11 Y37
M_A_DQ42 AU10 BD24 M_A_A6 LVDSB_DATA0 B42 AA42
SA_DQ_42 SA_MA_6 [18] LVDSB_DATA0 LVDSB_DATA_0 PEG_RX_12
M_A_DQ43 AV9 BG27 M_A_A7 LVDSB_DATA1 G38 AD36
SA_DQ_43 SA_MA_7 [18] LVDSB_DATA1 LVDSB_DATA_1 PEG_RX_13
C M_A_DQ44 BA11 BF25 M_A_A8 LVDSB_DATA2 F37 AC48 C
SA_DQ_44 SA_MA_8 [18] LVDSB_DATA2 LVDSB_DATA_2 PEG_RX_14
M_A_DQ45 BD9 AW24M_A_A9 K37 AD40
SA_DQ_45 SA_MA_9 LVDSB_DATA_3 PEG_RX_15 TMDS_B_HDP [12]
M_A_DQ46 AY8 BC21 M_A_A10
M_A_DQ47 SA_DQ_46 SA_MA_10
BG26 M_A_A11 J41 TMDS_B_DATA2#

t
BA6 SA_DQ_47 SA_MA_11 DVIB_DATA2#/PEG_TX#_0 TMDS_B_DATA2# [12]
M_A_DQ48 BH26 M_A_A12 M46 TMDS_B_DATA1#
DDR

AV5 SA_DQ_48 SA_MA_12 DVIB_DATA1#/PEG_TX#_1 TMDS_B_DATA1# [12]


M_A_DQ49 AV7 BH17 M_A_A13 R88 75R_1 MCH_TVA_DAC F25 M47 TMDS_B_DATA0#
SA_DQ_49 SA_MA_13 TVA_DAC DVIB_DATA0#/PEG_TX#_2 TMDS_B_DATA0# [12]
M_A_DQ50 AT9 AY25 M_A_A14 R82 75R_1 MCH_TVB_DAC H25 M40 TMDS_B_CLK#
SA_DQ_50 SA_MA_14 TVB_DAC DVIB_CLK#/PEG_TX#_3 TMDS_B_CLK# [12]

TV
M_A_DQ51 AN8 R79 75R_1 MCH_TVC_DAC K25 M42
SA_DQ_51 TVC_DAC DVIC_DATA2#/PEG_TX#_4

n
M_A_DQ52 AU5 R48
M_A_DQ53 SA_DQ_52 U14E DVIC_DATA1#/PEG_TX#_5
AU6 SA_DQ_53 [11] M_B_DQ[63:0] H24 TV_RTN DVIC_DATA0#/PEG_TX#_6 N38
M_A_DQ54 AT5 M_B_DQ0 AK47 BC16 M_B_BS0 T40
SA_DQ_54 SB_DQ_0 SB_BS_0 M_B_BS0 [6,11] DVIC_CLK#/PEG_TX#_7
M_A_DQ55 M_B_DQ1 BB17 M_B_BS1 TV_DCONSEL0_MCH

I
AN10 SA_DQ_55 AH46 SB_DQ_1 SB_BS_1 M_B_BS1 [6,11] TP2 C31 TV_DCONSEL_0 PEG_TX#_8 U37
M_A_DQ56 AM11 M_B_DQ2 AP47 BB33 M_B_BS2 TV_DCONSEL1_MCH E32 U40
SA_DQ_56 SB_DQ_2 SB_BS_2 M_B_BS2 [6,11] TP1 TV_DCONSEL_1 PEG_TX#_9
M_A_DQ57 AM5 M_B_DQ3 AP46 R95 0R Y40
M_A_DQ58 SA_DQ_57 M_B_DQ4 SB_DQ_3 PEG_TX#_10
AJ9 SA_DQ_58 AJ46 SB_DQ_4 SB_RAS# AU17 M_B_RAS# M_B_RAS# [6,11]
R96 0R
PEG_TX#_11 AA46
M_A_DQ59 AJ8 M_B_DQ5 AJ48 BG16 M_B_CAS# AA37
SA_DQ_59 SB_DQ_5 SB_CAS# M_B_CAS# [6,11] PEG_TX#_12
M_A_DQ60 AN12 M_B_DQ6 AM48 BF14 M_B_WE# CRT_BLUE E28 AA40
SA_DQ_60 SB_DQ_6 SB_WE# M_B_WE# [6,11] [18] CRT_BLUE CRT_BLUE PEG_TX#_13

s
M_A_DQ61 AM13 M_B_DQ7 AP48 CRT_GREEN G28 AD43
SA_DQ_61 SB_DQ_7 [18] CRT_GREEN CRT_GREEN PEG_TX#_14
M_A_DQ62 AJ11 M_B_DQ8 AU47 CRT_RED J28 AC46
SA_DQ_62 SB_DQ_8 M_B_DM[7:0] [11] [18] CRT_RED CRT_RED PEG_TX#_15

VGA
M_A_DQ63 AJ12 M_B_DQ9 AU46 AM47 M_B_DM0
SA_DQ_63 M_B_DQ10 SB_DQ_9 SB_DM_0
BA48 AY47 M_B_DM1 R78 150R_1 J42 TMDS_B_DATA2

e
SB_DQ_10 SB_DM_1 DVIB_DATA2/PEG_TX_0 TMDS_B_DATA2 [12]
CANTIGA_1p2 M_B_DQ11 AY48 BD40 M_B_DM2 Layout: R94 150R_1 L46 TMDS_B_DATA1
SB_DQ_11 SB_DM_2 DVIB_DATA1/PEG_TX_1 TMDS_B_DATA1 [12]
PBGA1329-CANTIGA M_B_DQ12 AT47 BF35 M_B_DM3 Place 150 Ohm termination R91 150R_1 M48 TMDS_B_DATA0
SB_DQ_12 SB_DM_3 DVIB_DATA0/PEG_TX_2 TMDS_B_DATA0 [12]
M_B_DQ13 AR47 BG11 M_B_DM4 resistors close to GMCH. G29 M39 TMDS_B_CLK
SB_DQ_13 SB_DM_4 CRT_IRTN DVIB_CLK/PEG_TX_3 TMDS_B_CLK [12]
M_B_DQ14 BA47 BA3 M_B_DM5 M43
SB_DQ_14 SB_DM_5 DVIC_DATA2/PEG_TX_4

d
M_B_DQ15 BC47 AP1 M_B_DM6 CRT_DDC_CLK H32 R47
SB_DQ_15 SB_DM_6 [12] CRT_DDC_CLK CRT_DDC_CLK DVIC_DATA1/PEG_TX_5
M_B_DQ16 BC46 AK2 M_B_DM7 CRT_DDC_DATA J32 N37
SB_DQ_16 SB_DM_7 [12] CRT_DDC_DATA CRT_DDC_DATA DVIC_DATA0/PEG_TX_6
M_B_DQ17 BC44 T39

i
SB_DQ_17 M_B_DQS[7:0] [11] DVIC_CLK/PEG_TX_7
M_B_DQ18 BG43 AL47 M_B_DQS0 U36
B
M_B_DQ19 SB_DQ_18 SB_DQS_0 PEG_TX_8
BF43 SB_DQ_19 SB_DQS_1 AV48 M_B_DQS1 PEG_TX_9 U39
M_B_DQ20 BE45 BG41 M_B_DQS2 CRT_HSYNC R104 24R_1 HSYNC J29 Y39
B SB_DQ_20 SB_DQS_2 [18] CRT_HSYNC CRT_HSYNC PEG_TX_10 B
M_B_DQ21 BC41 BG37 M_B_DQS3 Y46

v
M_B_DQ22 SB_DQ_21 SB_DQS_3 PEG_TX_11
BF40 SB_DQ_22 SB_DQS_4 BH9 M_B_DQS4 R83 1.02K_0.5 CRTIREF E29 CRT_TVO_IREF PEG_TX_12 AA36
M_B_DQ23 BB2 M_B_DQS5
MEMORY

BF41 SB_DQ_23 SB_DQS_5 PEG_TX_13 AA39


M_B_DQ24 BG38 AU1 M_B_DQS6 CRT_VSYNC R105 24R_1 VSYNC L29 AD42
SB_DQ_24 SB_DQS_6 [18] CRT_VSYNC CRT_VSYNC PEG_TX_14
M_B_DQ25 BF38 AN6 M_B_DQS7 AD46
SB_DQ_25 SB_DQS_7 PEG_TX_15

o
M_B_DQ26 BH35 SB_DQ_26 M_B_DQS#[7:0] [11]
M_B_DQ27 BG35 AL46 M_B_DQS#0
M_B_DQ28 SB_DQ_27 SB_DQS#_0
BH40 AV47 M_B_DQS#1 CANTIGA_1p2
On Board DDR2 Thermal Sensor M_B_DQ29 BG39
SB_DQ_28 SB_DQS#_1
BH41 M_B_DQS#2 PBGA1329-CANTIGA

r
M_B_DQ30 SB_DQ_29 SB_DQS#_2
BG34 SB_DQ_30 SB_DQS#_3 BH37 M_B_DQS#3 HSYNC C105 @22pF/50V_NP0 SDVO Present
M_B_DQ31 BH34 BG9 M_B_DQS#4
M_B_DQ32 SB_DQ_31 SB_DQS#_4
BH14 SB_DQ_32 SB_DQS#_5 BC2 M_B_DQS#5 VSYNC C108 @22pF/50V_NP0
M_B_DQ33 BG12 AT2 M_B_DQS#6 SDVO_CTRLDATA Low = No SDVO/HDMI/DP interface
+3.3V M_B_DQ34 SB_DQ_33 SB_DQS#_6
BH11 AN5 M_B_DQS#7 disabled DEFAULT

P
M_B_DQ35 SB_DQ_34 SB_DQS#_7
BG8 SB_DQ_35 M_B_A[14:0] [6,11]
M_B_DQ36 AV17 M_B_A0 CRT_BLUE C95 @10pF/50V_NP0 High = SDVO/HDMI/DP interface enabled
SYSTEM

BH12 SB_DQ_36 SB_MA_0


M_B_DQ37 BF11 BA25 M_B_A1
M_B_DQ38 SB_DQ_37 SB_MA_1
BF8 SB_DQ_38 SB_MA_2 BC25 M_B_A2 CRT_GREEN C98 @10pF/50V_NP0
M_B_DQ39 BG7 AU25 M_B_A3 Local Flat Panel (LFP) Present
R281 R306 R290 M_B_DQ40 SB_DQ_39 SB_MA_3
BC5 SB_DQ_40 SB_MA_4 AW25M_B_A4 CRT_RED C91 @10pF/50V_NP0
@221R_1 @10K_1 @10K_1 M_B_DQ41 BC6 BB28 M_B_A5
C271 U8 M_B_DQ42 SB_DQ_41 SB_MA_5
AY3 SB_DQ_42 SB_MA_6 AU28 M_B_A6 L_DDC_DATA Low = LFP Disabled DEFAULT
@100nF/10V_X7R M_B_DQ43 AY1 AW28M_B_A7 High = LFP Card Present; PCIE disabled
1032_VDD 1032_SCLK M_B_DQ44 SB_DQ_43 SB_MA_7
1 VDD SCLK 8 BF6 SB_DQ_44 SB_MA_8 AT33 M_B_A8
7 1032_SDATA M_B_DQ45 BF5 BD33 M_B_A9
DDR_THERM_D+ SDATA M_B_DQ46 SB_DQ_45 SB_MA_9
[11] DDR_THERM_D+ 2 D+ BA1 SB_DQ_46 SB_MA_10 BB16 M_B_A10 Digital Display Present
DDR_THERM_D- 3 4 1032_THERM# M_B_DQ47 BD3 AW33M_B_A11
[11] DDR_THERM_D- D- THERM SB_DQ_47 SB_MA_11
M_B_DQ48 AV2 AY33 M_B_A12
SB_DQ_48 SB_MA_12
DDR

5 6 1032_ALERT# M_B_DQ49 AU3 BH15 M_B_A13 DDPC_CTRLDATA Low = Digital display (HDMI/DP) device
GND ALERT M_B_DQ50 SB_DQ_49 SB_MA_13
AR3 SB_DQ_50 SB_MA_14 AU33 M_B_A14 absent DEFAULT
A
M_B_DQ51 AN2 A
@ADM1032 M_B_DQ52 SB_DQ_51
AY2 SB_DQ_52 High = Digital display (HDMI/DP) Device
M-MSOP8 M_B_DQ53 AV1
M_B_DQ54 SB_DQ_53 Present
AP3 SB_DQ_54
PM_THRM# R305 @0R M_B_DQ55 AR1
[5,15] PM_THRM# SB_DQ_55
M_B_DQ56 AL1 SB_DQ_56
[7,11] TS#DIMM0_1
TS#DIMM0_1 R291 @0R M_B_DQ57
M_B_DQ58
AL2
AJ1
SB_DQ_57 ECS COMPUTER CORP.
SB_SMB_DATA R307 @0R M_B_DQ59 SB_DQ_58
[11,15,17] SB_SMB_DATA AH1 SB_DQ_59
M_B_DQ60 AM2 Title
SB_DQ_60
[11,15,17] SB_SMB_CLK
SB_SMB_CLK R308 @0R M_B_DQ61
M_B_DQ62
AM3 SB_DQ_61 NB Cantiga 2 of 4
AH3 SB_DQ_62
M_B_DQ63 AJ3 Size Document Number Rev
SB_DQ_63 A
CANTIGA_1p2
3931
Custom F30II0
PBGA1329-CANTIGA Date: Monday, November 05, 2007 Sheet 8 of 36
5 4 3 2 1
5 4 3 2 1

+1.05V
U14F
120 mil / 2.9A
350 mil / 8.7A AG34 VCC_1
AC34 VCC_2
U14I U14J +1.8V_DDR U14G +GFX_CORE AB34
C372 VCC_3
AU48 VSS_1 VSS_100 AM36 BG21 VSS_199 VSS_297 AH8 AA34 VCC_4

e
AR48 AE36 L12 Y8 180 mil / 4.15A 10uF/6.3V_0805_X5R Y34
VSS_2 VSS_101 VSS_200 VSS_298 VCC_5
AL48 VSS_3 VSS_102 P36 AW21 VSS_201 VSS_299 L8 AP33 VCC_SM_1 VCC_AXG_NCTF_1 W28 V34 VCC_6
BB47 VSS_4 VSS_103 L36 AU21 VSS_202 VSS_300 E8 AN33 VCC_SM_2 VCC_AXG_NCTF_2 V28 U34 VCC_7
AW47 J36 AP21 B8 BH32 W26 AM33

c
VSS_5 VSS_104 VSS_203 VSS_301 C310 VCC_SM_3 VCC_AXG_NCTF_3 VCC_8
AN47 VSS_6 VSS_105 F36 AN21 VSS_204 VSS_302 AY7 BG32 VCC_SM_4 VCC_AXG_NCTF_4 V26 AK33 VCC_9
AJ47 B36 AH21 AU7 Layout: 10uF/6.3V_0805_X5R BF32 W25 AJ33
VSS_7 VSS_106 VSS_205 VSS_303 VCC_SM_5 VCC_AXG_NCTF_5 VCC_10
D AF47 AH35 AF21 AN7 Place on BD32 V25 AG33 D
VSS_8 VSS_107 VSS_206 VSS_304 VCC_SM_6 VCC_AXG_NCTF_6 VCC_11

POWER
AD47 AA35 AB21 AJ7 the edge. BC32 W24 C373 AF33
VSS_9 VSS_108 VSS_207 VSS_305 VCC_SM_7 VCC_AXG_NCTF_7 220nF/25V_0603_X7R VCC_12

n
AB47 VSS_10 VSS_109 Y35 R21 VSS_208 VSS_306 AE7 BB32 VCC_SM_8 VCC_AXG_NCTF_8 V24
Y47 VSS_11 VSS_110 U35 M21 VSS_209 VSS_307 AA7 BA32 VCC_SM_9 VCC_AXG_NCTF_9 W23 AE33 VCC_13
T47 T35 J21 N7 AY32 V23 Layout: AC33
VSS_12 VSS_111 VSS_210 VSS_308 VCC_SM_10 VCC_AXG_NCTF_10 VCC_14
N47 BF34 G21 J7 AW32 AM21 Cavity Capacitors. AA33
VSS_13 VSS_112 VSS_211 VSS_309 VCC_SM_11 VCC_AXG_NCTF_11 VCC_15

VCC CORE
L47 AM34 BC20 BG6 C296 AV32 AL21 Y33
VSS_14 VSS_113 VSS_212 VSS_310 10uF/6.3V_0805_X5R VCC_SM_12 VCC_AXG_NCTF_12 VCC_16
G47 VSS_15 VSS_114 AJ34 BA20 VSS_213 VSS_311 BD6 AU32 VCC_SM_13 VCC_AXG_NCTF_13 AK21 W33 VCC_17
BD46 VSS_16 VSS_115 AF34 AW20 VSS_214 VSS_312 AV6 AT32 VCC_SM_14 VCC_AXG_NCTF_14 W21 V33 VCC_18
BA46 AE34 AT20 AT6 AR32 V21 C383 U33

r
VSS_17 VSS_116 VSS_215 VSS_313 VCC_SM_15 VCC_AXG_NCTF_15 220nF/25V_0603_X7R VCC_19
AY46 VSS_18 VSS_117 W34 AJ20 VSS_216 VSS_314 AM6 AP32 VCC_SM_16 VCC_AXG_NCTF_16 U21 AH28 VCC_20
AV46 VSS_19 VSS_118 B34 AG20 VSS_217 VSS_315 M6 AN32 VCC_SM_17 VCC_AXG_NCTF_17 AM20 AF28 VCC_21
AR46 VSS_20 VSS_119 A34 Y20 VSS_218 VSS_316 C6 BH31 VCC_SM_18 VCC_AXG_NCTF_18 AK20 AC28 VCC_22

e
AM46 BG33 N20 BA5 Layout: BG31 W20 AA28

VCC SM
VSS_21 VSS_120 VSS_219 VSS_317 C298 VCC_SM_19 VCC_AXG_NCTF_19 VCC_23
V46 BC33 K20 AH5 Place C65 where BF31 U20 AJ26
VSS_22 VSS_121 VSS_220 VSS_318 100nF/10V_X7R VCC_SM_20 VCC_AXG_NCTF_20 VCC_24
R46 VSS_23 VSS_122 BA33 F20 VSS_221 VSS_319 AD5 LVDS and DDR2 BG30 VCC_SM_21 VCC_AXG_NCTF_21 AM19 AG26 VCC_25

f
P46 VSS_24 VSS_123 AV33 C20 VSS_222 VSS_320 Y5 taps. BH29 VCC_SM_22 VCC_AXG_NCTF_22 AL19 AE26 VCC_26
H46 AR33 A20 L5 BG29 AK19 C382 AC26
VSS_25 VSS_124 VSS_223 VSS_321 VCC_SM_23 VCC_AXG_NCTF_23 100nF/10V_X7R VCC_27
F46 VSS_26 VSS_125 AL33 BG19 VSS_224 VSS_322 J5 BF29 VCC_SM_24 VCC_AXG_NCTF_24 AJ19 AH25 VCC_28
BF44 AH33 A18 H5 BD29 AH19 AG25

e
VSS_27 VSS_126 VSS_225 VSS_323 VCC_SM_25 VCC_AXG_NCTF_25 VCC_29

POWER
AH44 AB33 BG17 F5 BC29 AG19 AF25

VCC GFX NCTF


VSS_28 VSS_127 VSS_226 VSS_324 VCC_SM_26 VCC_AXG_NCTF_26 VCC_30
AD44 VSS_29 VSS_128 P33 BC17 VSS_227 VSS_325 BE4 + BB29 VCC_SM_27 VCC_AXG_NCTF_27 AF19 AG24 VCC_31
AA44 L33 AW17 C289 BA29 AE19 AJ23
VSS_30 VSS_129 VSS_228 VCC_SM_28 VCC_AXG_NCTF_28 VCC_32

r
Y44 H33 AT17 BC3 NOTE: 330uF/2V_7343_SPCAP AY29 AB19 AH23
U44
T44
VSS_31
VSS_32
VSS_33
VSS VSS_130
VSS_131
VSS_132
N32
K32
R17
M17
VSS_229
VSS_230
VSS_231
VSS VSS_327
VSS_328
VSS_329
AV3
AL3
Pins BA36, BB24, BD16, BB21, AW16, AW13,
AT13 could be left NC for DDR2 boards.
AW29
AV29
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
AA19
Y19
AF23
VCC_33
VCC_34
M44 F32 H17 R3 VCC_SM/NC Pins may be left NC in DDR2 AU29 W19 R68 0R +VCC_MCH_35 T32
VSS_34 VSS_133 VSS_232 VSS_330 VCC_SM_32 VCC_AXG_NCTF_32 VCC_35
F44 C32 C17 P3 designs for ease of routing. AT29 V19

le
VSS_35 VSS_134 VSS_233 VSS_331 VCC_SM_33 VCC_AXG_NCTF_33 Layout: +1.05V
BC43 VSS_36 VSS_135 A31 VSS_332 F3 AR29 VCC_SM_34 VCC_AXG_NCTF_34 U19
AV43 AN29 BA16 BA2 AP29 AM17 R84 is used for internal test
VSS_37 VSS_136 VSS_235 VSS_333 VCC_SM_35 VCC_AXG_NCTF_35
AU43 VSS_38 VSS_137 T29 VSS_334 AW2 VCC_AXG_NCTF_36 AK17 purpose only.
C AM43 N29 AU16 AU2 @100nF/10V_X7R C303 VCC_SM_36 BA36 AH17 AM32 C
VSS_39 VSS_138 VSS_237 VSS_335 @100nF/10V_X7R C304 VCC_SM_37 VCC_SM_36/NC VCC_AXG_NCTF_37 VCC_NCTF_1
J43 VSS_40 VSS_139 K29 AN16 VSS_238 VSS_336 AR2 BB24 VCC_SM_37/NC VCC_AXG_NCTF_38 AG17 AL32 VCC_NCTF_2
C43 H29 N16 AP2 @100nF/10V_X7R C307 VCC_SM_38 BD16 AF17 120 mil / 2.9A AK32
VSS_41 VSS_140 VSS_239 VSS_337 VCC_SM_38/NC VCC_AXG_NCTF_39 VCC_NCTF_3

t
BG42 VSS_42 VSS_141 F29 K16 VSS_240 VSS_338 AJ2 BB21 VCC_SM_39/NC VCC_AXG_NCTF_40 AE17 AJ32 VCC_NCTF_4
AY42 A29 G16 AH2 @100nF/10V_X7R C309 VCC_SM_40 AW16 AC17 AH32
VSS_43 VSS_142 VSS_241 VSS_339 VCC_SM_40/NC VCC_AXG_NCTF_41 VCC_NCTF_5
AT42 VSS_44 VSS_143 BG28 E16 VSS_242 VSS_340 AF2 AW13 VCC_SM_41/NC VCC_AXG_NCTF_42 AB17 AG32 VCC_NCTF_6
AN42 BD28 BG15 AE2 @100nF/10V_X7R C46 VCC_SM_42 AT13 Y17 + AE32
VSS_45 VSS_144 VSS_243 VSS_341 VCC_SM_42/NC VCC_AXG_NCTF_43 C385 VCC_NCTF_7
AJ42 VSS_46 VSS_145 BA28 AC15 VSS_244 VSS_342 AD2 VCC_AXG_NCTF_44 W17 AC32 VCC_NCTF_8

n
AE42 AV28 W15 AC2 V17 @330uF/2V_7343_SPCAP AA32
VSS_47 VSS_146 VSS_245 VSS_343 +GFX_CORE VCC_AXG_NCTF_45 VCC_NCTF_9
N42 VSS_48 VSS_147 AT28 A15 VSS_246 VSS_344 Y2 VCC_AXG_NCTF_46 AM16 Y32 VCC_NCTF_10
L42 VSS_49 VSS_148 AR28 BG14 VSS_247 VSS_345 M2 VCC_AXG_NCTF_47 AL16 W32 VCC_NCTF_11
350 mil / 8.7A

I
BD41 VSS_50 VSS_149 AJ28 AA14 VSS_248 VSS_346 K2 VCC_AXG_NCTF_48 AK16 U32 VCC_NCTF_12
AU41 AG28 C14 AM1 Y26 AJ16 Layout: AM30
VSS_51 VSS_150 VSS_249 VSS_347 VCC_AXG_1 VCC_AXG_NCTF_49 VCC_NCTF_13
AM41 AE28 BG13 AA1 AE25 AH16 Place close to the GMCH. AL30
VSS_52 VSS_151 VSS_250 VSS_348 VCC_AXG_2 VCC_AXG_NCTF_50 VCC_NCTF_14
AH41 VSS_53 VSS_152 AB28 BC13 VSS_251 VSS_349 P1 AB25 VCC_AXG_3 VCC_AXG_NCTF_51 AG16 AK30 VCC_NCTF_15
AD41 Y28 BA13 H1 C79 AA25 AF16 AH30
VSS_54 VSS_153 VSS_252 VSS_350 10uF/6.3V_0805_X5R VCC_AXG_4 VCC_AXG_NCTF_52 VCC_NCTF_16
AA41 VSS_55 VSS_154 P28 AE24 VCC_AXG_5 VCC_AXG_NCTF_53 AE16 AG30 VCC_NCTF_17

s
Y41 K28 U24 MCH_VSS_351 R65 0R AC24 AC16 AF30
VSS_56 VSS_155 VSS_351 MCH_VSS_352 R70 0R VCC_AXG_6 VCC_AXG_NCTF_54 VCC_NCTF_18
U41 VSS_57 VSS_156 H28 AN13 VSS_255 VSS_352 U28 AA24 VCC_AXG_7 VCC_AXG_NCTF_55 AB16 AE30 VCC_NCTF_19
T41 F28 AJ13 U25 MCH_VSS_353 R66 0R Y24 AA16 AC30

VCC NCTF
VSS_58 VSS_157 VSS_256 VSS_353 MCH_VSS_354 R67 0R VCC_AXG_8 VCC_AXG_NCTF_56 VCC_NCTF_20
M41 C28 AE13 U29 AE23 Y16 AB30

e
VSS_59 VSS_158 VSS_257 VSS_354 MCH_VSS_355 R54 0R VCC_AXG_9 VCC_AXG_NCTF_57 VCC_NCTF_21
G41 VSS_60 VSS_159 BF26 N13 VSS_258 VSS_355 AJ6 AC23 VCC_AXG_10 VCC_AXG_NCTF_58 W16 AA30 VCC_NCTF_22
B41 AH26 L13 C99 AB23 V16 Y30
VSS_61 VSS_160 VSS_259 10uF/6.3V_0805_X5R VCC_AXG_11 VCC_AXG_NCTF_59 VCC_NCTF_23
BG40 VSS_62 VSS_161 AF26 G13 VSS_260 VSS_NCTF_1 AF32 AA23 VCC_AXG_12 VCC_AXG_NCTF_60 U16 W30 VCC_NCTF_24
BB40 VSS_63 VSS_162 AB26 E13 VSS_261 VSS_NCTF_2 AB32 AJ21 VCC_AXG_13 V30 VCC_NCTF_25

d
AV40 VSS_64 VSS_163 AA26 BF12 VSS_262 VSS_NCTF_3 V32 AG21 VCC_AXG_14 U30 VCC_NCTF_26
AN40 VSS_65 VSS_164 C26 AV12 VSS_263 VSS_NCTF_4 AJ30 AE21 VCC_AXG_15 AL29 VCC_NCTF_27
H40 B26 AT12 AM29 AC21 AK29

i
VSS_66 VSS_165 VSS_264 VSS_NCTF_5 VCC_AXG_16 VCC_NCTF_28
E40 BH25 AM12 AF29 AA21 AJ29
VSS NCTF

VSS_67 VSS_166 VSS_265 VSS_NCTF_6 C78 C69 VCC_AXG_17 VCC_NCTF_29


AT39 VSS_68 VSS_167 BD25 AA12 VSS_266 VSS_NCTF_7 AB29 Y21 VCC_AXG_18 AH29 VCC_NCTF_30
AM39 BB25 J12 U26 1uF/10V_0603_X5R @1uF/10V_0603_X5R AH20 AG29
B VSS_69 VSS_168 VSS_267 VSS_NCTF_8 VCC_AXG_19 VCC_NCTF_31 B
AJ39 AV25 A12 U23 AF20 AE29

v
VSS_70 VSS_169 VSS_268 VSS_NCTF_9 VCC_AXG_20 VCC_NCTF_32
AE39 VSS_71 VSS_170 AR25 BD11 VSS_269 VSS_NCTF_10 AL20 AE20 VCC_AXG_21 AC29 VCC_NCTF_33
N39 AJ25 BB11 V20 AC20 AA29

VCC GFX
VSS_72 VSS_171 VSS_270 VSS_NCTF_11 VCC_AXG_22 VCC_NCTF_34
L39 VSS_73 VSS_172 AC25 AY11 VSS_271 VSS_NCTF_12 AC19 AB20 VCC_AXG_23 Y29 VCC_NCTF_35
B39 VSS_74 VSS_173 Y25 AN11 VSS_272 VSS_NCTF_13 AL17 AA20 VCC_AXG_24 W29 VCC_NCTF_36

o
BH38 VSS_75 VSS_174 N25 AH11 VSS_273 VSS_NCTF_14 AJ17 T17 VCC_AXG_25 V29 VCC_NCTF_37
BC38 L25 AA17 Layout: C89 T16 AL28
VSS_76 VSS_175 VSS_NCTF_15 470nF/16V_0603_X7R VCC_AXG_26 VCC_NCTF_38
BA38 J25 Y11 U17 Cavity Capacitors. AM15 AK28
VSS_77 VSS_176 VSS_275 VSS_NCTF_16 VCC_AXG_27 VCC_NCTF_39
AU38 G25 N11 AL15 AL26

r
VSS_78 VSS_177 VSS_276 VCC_AXG_28 VCC_NCTF_40
AH38 VSS_79 VSS_178 E25 G11 VSS_277 VSS_SCB_1 BH48 AE15 VCC_AXG_29 AK26 VCC_NCTF_41
AD38 BF24 C11 BH1 AJ15 AK25
VSS SCB

VSS_80 VSS_179 VSS_278 VSS_SCB_2 VCC_AXG_30 VCC_NCTF_42


AA38 VSS_81 VSS_180 AD12 BG10 VSS_279 VSS_SCB_3 A48 AH15 VCC_AXG_31 AK24 VCC_NCTF_43
Y38 VSS_82 VSS_181 AY24 AV10 VSS_280 VSS_SCB_4 C1 AG15 VCC_AXG_32 AK23 VCC_NCTF_44
U38 AT24 AT10 C63 C82 AF15

P
VSS_83 VSS_182 VSS_281 100nF/10V_X7R 100nF/10V_X7R VCC_AXG_33
T38 VSS_84 VSS_183 AJ24 AJ10 VSS_282 VSS_SCB_6 A3 AB15 VCC_AXG_34
J38 AH24 AE10 AA15 CANTIGA_1p2
VSS_85 VSS_184 VSS_283 VCC_AXG_35 PBGA1329-CANTIGA
F38 VSS_86 VSS_185 AF24 AA10 VSS_284 NC_26 E1 Y15 VCC_AXG_36
C38 VSS_87 VSS_186 AB24 M10 VSS_285 NC_27 D2 V15 VCC_AXG_37
BF37 R24 BF9 C3 U15

VCC SM LF
VSS_88 VSS_187 VSS_286 NC_28 VCC_AXG_38
BB37 VSS_89 VSS_188 L24 BC9 VSS_287 NC_29 B4 AN14 VCC_AXG_39 VCC_SM_LF1 AV44 +VCCSM_LF1
AW37 VSS_90 VSS_189 K24 AN9 VSS_288 NC_30 A5 + + AM14 VCC_AXG_40 VCC_SM_LF2 BA37 +VCCSM_LF2
AT37 J24 AM9 A6 C80 C81 U14 AM40 +VCCSM_LF3
VSS_91 VSS_190 VSS_289 NC_31 @330uF/2V_7343_SPCAP @330uF/2V_7343_SPCAP VCC_AXG_41 VCC_SM_LF3
AN37 VSS_92 VSS_191 G24 AD9 VSS_290 NC_32 A43 T14 VCC_AXG_42 VCC_SM_LF4 AV21 +VCCSM_LF4
AJ37 VSS_93 VSS_192 F24 G9 VSS_291 NC_33 A44 VCC_SM_LF5 AY5 +VCCSM_LF5 C328 C340
H37 E24 B9 B45 AM10 +VCCSM_LF6 1uF/6.3V_X5R 1uF/6.3V_X5R
NC

VSS_94 VSS_193 VSS_292 NC_34 VCC_SM_LF6


C37 VSS_95 VSS_194 BH23 BH8 VSS_293 NC_35 C46 Layout:
VCC_SM_LF7 BB13 +VCCSM_LF7 C305 C57
BG36 AG23 BB8 D47 Place close to the GMCH. 220nF/6.3V_X5R 470nF/6.3V_X5R
VSS_96 VSS_195 VSS_294 NC_36 C58 C338
BD36 VSS_97 VSS_196 Y23 AV8 VSS_295 NC_37 B47
AK15 B23 AT8 A46 C308 100nF/10V_X7R 220nF/6.3V_X5R
VSS_98 VSS_197 VSS_296 NC_38 100nF/10V_X7R
AU36 VSS_99 VSS_198 A23 NC_39 F48
E48 VCC_AXG_SENSE AJ14 JMK105BJ474KV-F
A NC_40 [28] VCC_AXG_SENSE VCC_AXG_SENSE A
C48 VSS_AXG_SENSE AH14
NC_41 [28] VSS_AXG_SENSE VSS_AXG_SENSE
NC_42 B48
CANTIGA_1p2 A47 Layout:
PBGA1329-CANTIGA NC_43
Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially.
CANTIGA_1p2
PBGA1329-CANTIGA
ECS COMPUTER CORP.
CANTIGA_1p2
PBGA1329-CANTIGA Title
NB Cantiga 3 of 4
Size Document Number Rev
A
3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 9 of 36
5 4 3 2 1
5 4 3 2 1

+1.8VS / 300mA
24 mil / 0.4A U17 20 mil / 0.3A
+3.3VS 1 VIN VOUT 5 +1.8VS
2 GND
C434 C404

e
@1uF/10V_0603_X5R 3 4 Z1007 @4.7uF/10V_0805_X5R
SHDN BP
@FP6133
M-SOT23-5 C426

c
@100nF/10V_X7R
R420 @10K_1 Z1006 R421 @220K
D D
+DDR_ON R422 @0R
[24,29] +DDR_ON
L48 10 mil / 0.2A 10 mil / 0.2A

n
+1.05V +3.3V L12
FCM1608KF-121T06_0603 +1.8VS +1.8V_DDR
+ FCM1608KF-121T06_0603

e
C420 C411 C414 C409
@100uF/6.3V_3528_NEC 100nF/10V_X7R 100nF/10V_X7R 10nF/25V_X7R
U14H
60 mil / 1.3A

r
L47 10 mil / 0.2A 10 mil / 0.2A U13
+1.05V
FCM1608KF-121T06_0603
+3.3V
B27 VCCA_CRT_DAC_1
POWER VTT_1
VTT_2
VTT_3
T13
U12 +
+1.05V

e
+ A26 T12 C374 C387 C371 C390 C389
C400 C396 C419 C407 VCCA_CRT_DAC_2 VTT_4 470nF/16V_0603_X7R 2.2uF/10V_0603_X5R 4.7uF/10V_0805_X5R 4.7uF/10V_0805_X5R @100uF/6.3V_3528_NEC
VTT_5 U11
@100uF/6.3V_3528_NEC 100nF/10V_X7R 100nF/10V_X7R 10nF/25V_X7R T11

CRT
VTT_6

f
A25 VCCA_DAC_BG VTT_7 U10
B25 VSSA_DAC_BG VTT_8 T10
L41 10 mil / 0.2A U9
VTT_9
+1.05V T9

e
0R_0603 VTT_10
VTT_11 U8
+V1.05M_DPLLA F47 T8
C362 C369 VCCA_DPLLA VTT_12 L52
VTT_13 U7 24 mil / 0.5A

r
4.7uF/10V_0805_X5R 100nF/10V_X7R +V1.05M_DPLLB L48 T7

PLL

VTT
VCCA_DPLLB VTT_14 +1.05V
U6 0R_0603
+V1.05M_HPLL VTT_15
AD1 VCCA_HPLL VTT_16 T6
L11 10 mil / 0.2A U5 C421 C413
+V1.05M_MPLL VTT_17 1uF/6.3V_X5R @10uF/6.3V_0805_X5R
+1.05V AE1 T5

le
FCM1608KF-121T06_0603 VCCA_MPLL VTT_18
VTT_19 V3
10 mil / 0.2A U3

A LVDS
R58 1R C64 VTT_20
+1.8VS J48 VCCA_LVDS VTT_21 V2
C 100nF/10V_X7R U2 C
Z1001 C67 10uF/6.3V_0805_X5R C406 1nF/50V_X7R VTT_22
J47 VSSA_LVDS VTT_23 T2
+V1.05M_PEGPLL V1 12 mil / 0.3A L32
VTT_24

t
8 mil / 0.1A VTT_25 U1 +1.8V_DDR
L44 10 mil / 0.2A +1.5V AD48 FCI2012F-1R0K_0805
VCCA_PEG_BG
+1.05V
FCM1608KF-221T05_0603 C107 100nF/10V_X7R C306 R311 1R

A PEG
VCC_AXF_1 B22 +V1.05M_AXF 100nF/10V_X7R

n
R63 1R C367 C370 100nF/10V_X7R B21 Z1004

AXF
100nF/10V_X7R VCC_AXF_2 C294 10uF/6.3V_0805_X5R
VCC_AXF_3 A21
Z1002 C83 10uF/6.3V_0805_X5R +V1.05M_PEGPLL AA48
VCCA_PEG_PLL

I
+V1.05M_A_SM
L38 50 mil / 1.2A BF21 +V1.8_SM_CK

SM CK
+V1.05M_A_SM VCC_SM_CK_1 L46
+1.05V AR20 VCCA_SM_1 VCC_SM_CK_2 BH20 10 mil / 0.2A
FCM1608KF-121T06_0603 AP20 BG20 +1.8VS
VCCA_SM_2 VCC_SM_CK_3 FCI2012F-R10K_0805
+ AN20 VCCA_SM_3 VCC_SM_CK_4 BF20

s
C358 C51 C347 C348 C59 AR17

A SM
100uF/6.3V_3528_NEC 4.7uF/10V_0805_X5R 10uF/6.3V_0805_X5R @10uF/6.3V_0805_X5R 1uF/6.3V_X5R VCCA_SM_4 C394 C397
AP17 VCCA_SM_5
Layout: Layout: AN17 1nF/50V_X7R 10uF/6.3V_0805_X5R
VCCA_SM_6
Edge Cap. Cavity Cap. AT16 K47 +V1.8_TXLVDS

e
VCCA_SM_7 VCC_TX_LVDS
AR16 VCCA_SM_8
AP16 VCCA_SM_9
L37 20 mil / 0.3A

d
+1.05V +V1.05M_A_SM_CK AP28 10 mil / 0.2A
FCM1608KF-121T06_0603 VCCA_SM_CK_1 R383 10R_1 Z1005
AN28 VCCA_SM_CK_2 VCC_HV_1 C35 C A +1.05V
AP25 B35 D11 BAT54

HV
i
C341 C49 C52 VCCA_SM_CK_3 VCC_HV_2
AN25 VCCA_SM_CK_4 VCC_HV_3 A35 +3.3V
10uF/6.3V_0805_X5R @2.2uF/6.3V_0603_X5R 100nF/10V_X7R AN24 VCCA_SM_CK_5
AM28

A CK
B VCCA_SM_CK_NCTF_1 C416 B
AM26

v
VCCA_SM_CK_NCTF_2 100nF/10V_X7R
AM25 VCCA_SM_CK_NCTF_3
AL25 VCCA_SM_CK_NCTF_4
AM24 VCCA_SM_CK_NCTF_5
L51 10 mil / 0.2A AL24 VCCA_SM_CK_NCTF_6

o
+3.3V AM23 100 mil / 2.4A L40
FCM1608KF-221T05_0603 VCCA_SM_CK_NCTF_7
AL23 VCCA_SM_CK_NCTF_8 VCC_PEG_1 V48 +VCC_PEG +1.05V
U48 0R_0805

PEG
C417 C410 VCC_PEG_2
V47

r
VCC_PEG_3 +
100nF/10V_X7R 10nF/25V_X7R +V3.3S_A_TVDAC B24 U47 C380 C361 C386

TV
VCCA_TV_DAC_1 VCC_PEG_4 4.7uF/10V_0805_X5R @10uF/6.3V_0805_X5R 100uF/6.3V_3528_NEC
A24 VCCA_TV_DAC_2 VCC_PEG_5 U46

L49 C408 100nF/10V_X7R


@FCM1608KF-221T05_0603 10 mil / 0.2A
HDA

P
+1.5V +VCC_HDA A32
L53 VCC_HDA
10 mil / 0.2A 10 mil / 0.2A
+1.5V +1.5V M25
D TV/CRT
FCM1608KF-221T05_0603 VCCD_TVDAC
VCC_DMI_1 AH48
AF48
DMI
C430 C432 C106 C103 VCC_DMI_2
VCC_DMI_3 AH47
100nF/10V_X7R 10nF/25V_X7R 100nF/10V_X7R 10nF/25V_X7R AG47 C366
VCC_DMI_4 100nF/10V_X7R

+V1.5S_QDAC L28 VCCD_QDAC


C388 100nF/10V_X7R
10 mil / 0.2A
AF1 A8 +VTTLF_CAP1
VTTLF

+1.05V VCCD_HPLL VTTLF1


L1 +VTTLF_CAP2
VTTLF2
+1.05V AA47 VCCD_PEG_PLL VTTLF3 AB2 +VTTLF_CAP3
A A
+VCC_HDA R675 0R 10 mil / 0.2A C350 100nF/10V_X7R
C377 C392 C418
470nF/6.3V_X5R 470nF/6.3V_X5R 470nF/6.3V_X5R
LVDS

+1.8VS M38 VCCD_LVDS_1


L37 VCCD_LVDS_2
10 mil / 0.2A
C85 1uF/6.3V_X5R
JMK105BJ474KV-F JMK105BJ474KV-F JMK105BJ474KV-F
ECS COMPUTER CORP.
CANTIGA_1p2 Title
PBGA1329-CANTIGA NB Cantiga 4 of 4
Size Document Number Rev
A
3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 10 of 36
5 4 3 2 1
5 4 3 2 1

+1.8V_DDR +1.8V_DDR

180 mil / 4.5A 180 mil / 4.5A


C261 C13 C262 C14 C16 C18 C265 C263 C10 C264 C9 C17 C266 C267
100nF/10V_X7R 100nF/10V_X7R 100nF/10V_X7R 100nF/10V_X7R 2.2uF/10V_0603_X5R 2.2uF/10V_0603_X5R 2.2uF/10V_0603_X5R 100nF/10V_X7R 100nF/10V_X7R 100nF/10V_X7R 100nF/10V_X7R 2.2uF/10V_0603_X5R 2.2uF/10V_0603_X5R 2.2uF/10V_0603_X5R

Layout: Layout:
Place close to DIMM_A0 along +1.8V_DDR power shape. Place close to DIMM_B0 along +1.8V_DDR power shape.

103
104
111
112
117
118

103
104
111
112
117
118
81
82
87
88
e
95
96

81
82
87
88
95
96
CN6 CN22
[6,8] M_A_A[14:0] M_A_DQ[63:0] [8] [6,8] M_B_A[14:0] M_B_DQ[63:0] [8]
M_A_A0 102 5 M_A_DQ0 M_B_A0 102 5 M_B_DQ0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
M_A_A1 A0 DQ0 M_A_DQ1 M_B_A1 A0 DQ0 M_B_DQ1
101 7 101 7

c
M_A_A2 A1 DQ1 M_A_DQ2 M_B_A2 A1 DQ1 M_B_DQ2
100 A2 DQ2 17 100 A2 DQ2 17
Layout: M_A_A3 99 19 M_A_DQ3 M_B_A3 99 19 M_B_DQ3
M_A_A4 A3 DQ3 M_A_DQ4 Layout: M_B_A4 A3 DQ3 M_B_DQ4
D Place close to 98 4 98 4 D
M_A_A5 A4 DQ4 M_A_DQ5 M_B_A5 A4 DQ4 M_B_DQ5
DIMM_A0 along 97 6 Place close to 97 6
M_A_A6 A5 DQ5 M_A_DQ6 M_B_A6 A5 DQ5 M_B_DQ6

n
+1.8V_DDR power 94 A6 DQ6 14 DIMM_B0 along 94 A6 DQ6 14
shape. M_A_A7 92 16 M_A_DQ7 +1.8V_DDR power M_B_A7 92 16 M_B_DQ7
M_A_A8 A7 DQ7 M_A_DQ8 M_B_A8 A7 DQ7 M_B_DQ8
93 A8 DQ8 23 shape. 93 A8 DQ8 23
M_A_A9 91 25 M_A_DQ9 M_B_A9 91 25 M_B_DQ9
A9 DQ9 A9 DQ9

e
M_A_A10 105 35 M_A_DQ10 M_B_A10 105 35 M_B_DQ10
M_A_A11 A10/AP DQ10 M_A_DQ11 M_B_A11 A10/AP DQ10 M_B_DQ11
90 A11 DQ11 37 90 A11 DQ11 37
M_A_A12 89 20 M_A_DQ12 +1.8V_DDR M_B_A12 89 20 M_B_DQ12 +1.8V_DDR
M_A_A13 A12 DQ12 M_A_DQ13 M_B_A13 A12 DQ12 M_B_DQ13
116 22 116 22

r
M_A_A14 NC/A13 DQ13 M_A_DQ14 M_B_A14 NC/A13 DQ13 M_B_DQ14
86 NC/A14 DQ14 36 86 NC/A14 DQ14 36
84 38 M_A_DQ15 84 38 M_B_DQ15
NC/A15 DQ15 M_A_DQ16 NC/A15 DQ15 M_B_DQ16
DQ16 43 DQ16 43

e
45 M_A_DQ17 C301 C272 45 M_B_DQ17 C239 C238
M_A_BS0 DQ17 M_A_DQ18 2.2uF/10V_0603_X5R 2.2uF/10V_0603_X5R M_B_BS0 DQ17 M_B_DQ18 2.2uF/10V_0603_X5R 2.2uF/10V_0603_X5R
[6,8] M_A_BS0 107 BA0 DQ18 55 [6,8] M_B_BS0 107 BA0 DQ18 55
M_A_BS1 106 57 M_A_DQ19 M_B_BS1 106 57 M_B_DQ19
[6,8] M_A_BS1 BA1 DQ19 [6,8] M_B_BS1 BA1 DQ19

f
M_A_BS2 85 44 M_A_DQ20 M_B_BS2 85 44 M_B_DQ20
[6,8] M_A_BS2 BA2 DQ20 [6,8] M_B_BS2 BA2 DQ20
46 M_A_DQ21 46 M_B_DQ21
DQ21 M_A_DQ22 DQ21 M_B_DQ22
[8] M_A_DM[7:0] DQ22 56 [8] M_B_DM[7:0] DQ22 56
M_A_DM0 10 58 M_A_DQ23 M_B_DM0 10 58 M_B_DQ23

e
M_A_DM1 DM0 DQ23 M_A_DQ24 +1.8V_DDR M_B_DM1 DM0 DQ23 M_B_DQ24 +1.8V_DDR
26 DM1 DQ24 61 26 DM1 DQ24 61
M_A_DM2 52 63 M_A_DQ25 M_B_DM2 52 63 M_B_DQ25
M_A_DM3 DM2 DQ25 M_A_DQ26 Layout: M_B_DM3 DM2 DQ25 M_B_DQ26 Layout:
67 DM3 DQ26 73 67 DM3 DQ26 73

r
M_A_DM4 130 75 M_A_DQ27 + Place close to M_B_DM4 130 75 M_B_DQ27 + Place close to
M_A_DM5 DM4 DQ27 M_A_DQ28 C8 M_B_DM5 DM4 DQ27 M_B_DQ28 C256
147 DM5 DQ28 62 DIMM_A0 along 147 DM5 DQ28 62 DIMM_B0 along
M_A_DM6 170 64 M_A_DQ29 @330uF/2V_7343_SPCAP +1.8V_DDR M_B_DM6 170 64 M_B_DQ29 @330uF/2V_7343_SPCAP +1.8V_DDR
M_A_DM7 DM6 DQ29 M_A_DQ30 M_B_DM7 DM6 DQ29 M_B_DQ30
185 DM7 DQ30 74 power shape. 185 DM7 DQ30 74 power shape.
76 M_A_DQ31 76 M_B_DQ31

le
DQ31 M_A_DQ32 DQ31 M_B_DQ32
[8] M_A_DQS[7:0] DQ32 123 [8] M_B_DQS[7:0] DQ32 123
M_A_DQS0 13 125 M_A_DQ33 M_B_DQS0 13 125 M_B_DQ33
M_A_DQS1 DQS0 DQ33 M_A_DQ34 M_B_DQS1 DQS0 DQ33 M_B_DQ34
31 DQS1 DQ34 135 31 DQS1 DQ34 135
C M_A_DQS2 51 137 M_A_DQ35 M_B_DQS2 51 137 M_B_DQ35 C
M_A_DQS3 DQS2 DQ35 M_A_DQ36 M_B_DQS3 DQS2 DQ35 M_B_DQ36
70 DQS3 DQ36 124 70 DQS3 DQ36 124
M_A_DQS4 131 126 M_A_DQ37 M_B_DQS4 131 126 M_B_DQ37
M_A_DQS5 DQS4 DQ37 M_A_DQ38 M_B_DQS5 DQS4 DQ37 M_B_DQ38

t
148 DQS5 DQ38 134 148 DQS5 DQ38 134
M_A_DQS6 169 136 M_A_DQ39 M_B_DQS6 169 136 M_B_DQ39
M_A_DQS7 DQS6 DQ39 M_A_DQ40 M_B_DQS7 DQS6 DQ39 M_B_DQ40
188 DQS7 DQ40 141 188 DQS7 DQ40 141
143 M_A_DQ41 143 M_B_DQ41
DQ41 M_A_DQ42 DQ41 M_B_DQ42 Layout:
[8] M_A_DQS#[7:0] DQ42 151 [8] M_B_DQS#[7:0] DQ42 151

n
M_A_DQS#0 11 153 M_A_DQ43 M_B_DQS#0 11 153 M_B_DQ43 Place close to
M_A_DQS#1 DQS#0 DQ43 M_A_DQ44 M_B_DQS#1 DQS#0 DQ43 M_B_DQ44
29 DQS#1 DQ44 140 29 DQS#1 DQ44 140 DIMM_B0 the center.
M_A_DQS#2 49 142 M_A_DQ45 M_B_DQS#2 49 142 M_B_DQ45
M_A_DQS#3 DQS#2 DQ45 M_A_DQ46 M_B_DQS#3 DQS#2 DQ45 M_B_DQ46

I
68 152 68 152

C
M_A_DQS#4 DQS#3 DQ46 M_A_DQ47 M_B_DQS#4 DQS#3 DQ46 M_B_DQ47
129 DQS#4 DQ47 154 129 DQS#4 DQ47 154
M_A_DQS#5 146 157 M_A_DQ48 M_B_DQS#5 146 157 M_B_DQ48 B DDR_THERM_D+
DQS#5 DQ48 DQS#5 DQ48 DDR_THERM_D+ [8]
M_A_DQS#6 167 159 M_A_DQ49 M_B_DQS#6 167 159 M_B_DQ49
M_A_DQS#7 DQS#6 DQ49 M_A_DQ50 M_B_DQS#7 DQS#6 DQ49 M_B_DQ50 Q37
186 173 186 173

E
DQS#7 DQ50 M_A_DQ51 DQS#7 DQ50 M_B_DQ51 @TR-2N3904
DQ51 175 DQ51 175

s
M_CLK_DDR0 30 158 M_A_DQ52 M_CLK_DDR2 30 158 M_B_DQ52
[7] M_CLK_DDR0 CK0 DQ52 [7] M_CLK_DDR2 CK0 DQ52
M_CLK_DDR1 164 160 M_A_DQ53 M_CLK_DDR3 164 160 M_B_DQ53 DDR_THERM_D-
[7] M_CLK_DDR1 CK1 DQ53 [7] M_CLK_DDR3 CK1 DQ53 DDR_THERM_D- [8]
M_CLK_DDR#0 32 174 M_A_DQ54 M_CLK_DDR#2 32 174 M_B_DQ54
[7] M_CLK_DDR#0 CK#0 DQ54 [7] M_CLK_DDR#2 CK#0 DQ54
M_CLK_DDR#1 166 176 M_A_DQ55 M_CLK_DDR#3 166 176 M_B_DQ55

e
[7] M_CLK_DDR#1 CK#1 DQ55 [7] M_CLK_DDR#3 CK#1 DQ55
179 M_A_DQ56 179 M_B_DQ56
M_A_RAS# DQ56 M_A_DQ57 M_B_RAS# DQ56 M_B_DQ57
[6,8] M_A_RAS# 108 RAS# DQ57 181 [6,8] M_B_RAS# 108 RAS# DQ57 181
M_A_CAS# 113 189 M_A_DQ58 M_B_CAS# 113 189 M_B_DQ58
[6,8] M_A_CAS# CAS# DQ58 [6,8] M_B_CAS# CAS# DQ58
M_A_WE# 109 191 M_A_DQ59 M_B_WE# 109 191 M_B_DQ59
[6,8] M_A_WE# WE# DQ59 [6,8] M_B_WE# WE# DQ59

d
180 M_A_DQ60 180 M_B_DQ60 R287 0R DDR_EVENT#
DQ60 M_A_DQ61 DQ60 M_B_DQ61
DQ61 182 DQ61 182
192 M_A_DQ62 192 M_B_DQ62

i
DQ62 DQ62 TS#DIMM0_1 [7,8]
M_CKE0 79 194 M_A_DQ63 M_CKE2 79 194 M_B_DQ63
[6,7] M_CKE0 CKE0 DQ63 [6,7] M_CKE2 CKE0 DQ63
M_CKE1 80 M_CKE3 80
[6,7] M_CKE1 NC/CKE1 [6,7] M_CKE3 NC/CKE1
B DDR_EVENT# DDR_EVENT# B
50 50

v
M_CS#0 NC1 M_CS#2 NC1
[6,7] M_CS#0 110 S0# NC2 69 [6,7] M_CS#2 110 S0# NC2 69
M_CS#1 115 163 M_CS#3 115 163
[6,7] M_CS#1 NC/S1# NC/TEST [6,7] M_CS#3 NC/S1# NC/TEST
83 Layout: 83
NC/S2# NC/S2#
120 Place close to SO-DIMM_B0 pin199. 120
NC/S3# NC/S3#

o
VDDSPD 199 +3.3V VDDSPD 199 +3.3V
M_ODT0 114 M_ODT2 114
[6,7] M_ODT0 ODT0 [6,7] M_ODT2 ODT0
M_ODT1 119 NC3 C19 C20 M_ODT3 119 NC3 C259 C270

r
[6,7] M_ODT1 NC/ODT1 GND1 [6,7] M_ODT3 NC/ODT1 GND1
NC4 100nF/10V_X7R 2.2uF/10V_0603_X5R NC4 100nF/10V_X7R 2.2uF/10V_0603_X5R
SB_SMB_DATA GND2 SB_SMB_DATA GND2
[8,15,17] SB_SMB_DATA 195 SDA 195 SDA
SB_SMB_CLK 197 196 SB_SMB_CLK 197 196
[8,15,17] SB_SMB_CLK SCL VSS SCL VSS
193 193 Layout:
VSS VSS
190 190 Place close to SO-DIMM_B0 pin199.

P
M_VERF_DIMM VSS M_VERF_DIMM VSS
1 VREF VSS 187 1 VREF VSS 187
183 +1.8V_DDR 183
VSS VSS
VSS 184 VSS 184
C15 SA0_DIM0 198 178 C260 SA0_DIM1 198 178
100nF/10V_X7R SA1_DIM0 SA0 VSS Layout: 100nF/10V_X7R SA1_DIM1 SA0 VSS
200 SA1 VSS 177 200 SA1 VSS 177
172 Place close to SO-DIMMs. 172
C21 VSS C290 VSS
2 VSS VSS 171 2 VSS VSS 171
2.2uF/10V_0603_X5R 3 168 R288 C273 2.2uF/10V_0603_X5R 3 168
VSS VSS 1K_1_0603 100nF/10V_X7R VSS VSS
8 VSS VSS 165 8 VSS VSS 165
9 VSS VSS 162 9 VSS VSS 162
12 161 M_VERF_DIMM 12 161
Layout: VSS VSS Layout: VSS VSS
15 VSS VSS 156 15 VSS VSS 156
Place close to 18 155 Place close to 18 155
VSS VSS VSS VSS
SO-DIMM_A0 pin1. 21 VSS VSS 150 SO-DIMM_B0 pin1. 21 VSS VSS 150
24 149 R289 C268 C269 24 149
VSS VSS 1K_1_0603 100nF/10V_X7R 1nF/50V_X7R VSS VSS
27 VSS VSS 145 27 VSS VSS 145
A
R14 R13 28 144 R277 R278 28 144 A
10K_1 10K_1 VSS VSS 10K_1 10K_1 VSS VSS
33 VSS VSS 139 33 VSS VSS 139
34 VSS VSS 138 34 VSS VSS 138
39 VSS VSS 133 39 VSS VSS 133
40 VSS VSS 132 40 VSS VSS 132
41 128 +3.3V 41 128
VSS VSS VSS VSS
42 127 [7] M_VREF_MCH
M_VREF_MCH R331 0R 42 127 ECS COMPUTER CORP.
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VSS VSS VSS
47 VSS VSS 122 47 VSS VSS 122
NOTE: NOTE:
SO-DIMM_A0 SPD Address is 0xA0. SO-DIMM_B0 SPD Address is 0xA4. Title
48
53
54
59
60
65
66
71
72
77
78
121

48
53
54
59
60
65
66
71
72
77
78
121
SO-DIMM_A0 TS Address is 0x30. DDR-292524
AS042X-N4SX_A5640C
SO-DIMM_B0 TS Address is 0x34. DDR-SR210008-E
DDRRX-20001-XX8S
DDR2 SODIMMs
Size Document Number Rev
A
3931
Custom F30II0
DDR2 SO-DIMM A0 H=4_STD DDR2 SO-DIMM B0 H=8_RVS Date: Monday, November 05, 2007 Sheet 11 of 36
5 4 3 2 1
5 4 3 2 1

+1.05V +1.05V
+5V RN13 8P4R_0R
H_VID5 1 8 CPU_VID5
[6] H_VID5 CPU_VID5 [27] +1.05V
100nF/10V_X7R C473 H_VID4 2 7 CPU_VID4
[6] H_VID4 CPU_VID4 [27]

5
6
7
8

5
6
7
8
H_VID3 3 6 CPU_VID3
SMART POWER RN16
8P4R_4.7K
RN15
8P4R_4.7K
[6] H_VID3
4 5
CPU_VID3 [27]
LV_LOCK
Q46

24

G
U19 H_VID2 1 8 CPU_VID2 @FET-FDV301N
[6] H_VID2 CPU_VID2 [27]

4
3
2
1

4
3
2
1
e
H_VID1 2 7 CPU_VID1 R389

VCC
[6] H_VID1 CPU_VID1 [27]
CPU_VID2 EC_VID3_R H_VID0 3 6 CPU_VID0 S D 4.7K
[6] H_VID0 CPU_VID0 [27]
CPU_VID3 EC_VID4_R H_VID6 4 5 CPU_VID6
[6] H_VID6 CPU_VID6 [27]
H_VID5 3 2 CPU_VID5 H_VID0 CPU_VID0

c
H_VID4 1A1 1B1 CPU_VID4 RN14 8P4R_0R
4 1A2 1B2 5
H_VID3 7 6 CPU_VID3 +1.05V S D
HH_VID2 1A3 1B3 CPU_VID2 R425 @0R R676 4.7K
D 8 1A4 1B4 9 D
11 1A5 1B5 10
Q47

G
EC_VID5 1 8 EC_VID5_R 14 15 SMP_50MV_EN# @FET-FDV301N
[24] EC_VID5 2A1 2B1 [24] SMP_50MV_EN#
EC_VID4 2 7 EC_VID4_R 17 16
[24] EC_VID4 2A2 2B2 +1.05V +1.05V
EC_VID3 3 6 EC_VID3_R 18 19
[24] EC_VID3 2A3 2B3

e
EC_VID2 4 5 EC_VID2_R 21 20
[24] EC_VID2 2A4 2B4
RN17 @8P4R_100R_1 22 23 LV_LOCK LV_LOCK
2A5 2B5 R484 10K_1 LV_LOCK Q45 Q58
+3.3V

G
R508 10K_1 CPU_VID# 1 @FET-FDV301N @FET-FDV301N

r
+5V 1OE#
EC_VID# 13 R510 R509

D
100nF/10V_X7R C471 2OE# R485 10K_1 Z1201 4.7K 4.7K
+5V +3.3V S D S D

GND
5

e
G Q56 H_VID1 CPU_VID1 H_VID2 HH_VID2
1 +1.05V R471 1K_1 @FET-2N7002E

S
4 @SN74CBT3384AS S D S D
D

12
f
2 M-TSSOP24

C
D12 @BAT54
SMP2_EN# G Q57 U22 H_VID5 C A Z1202 B Q54 Q59 Q50
[24] SMP2_EN#

G
@FET-2N7002E @7SZ00P5X @TR-2N3904 SMP_50MV_EN# @FET-FDV301N SMP_100MV_EN# @FET-FDV301N

e
[24] SMP_100MV_EN#
S

M-SC70-5

E
R482 @0R H_VID4 C A

r
D13 @BAT54

le
Pin CH7318 PS8101
C C

DVI SHIFTER 3 Pull-Low 10K_1 Note 1

t
4 Pull-Low 10K_1 Note 1
+3.3V_DVI +3.3V_DVI +3.3V_DVI +3.3V
L54 6 Pull-Low 1.2K Pull-Low 499R_1
TMDS_B_DATA1# TMDS_B_DATA0
[8] TMDS_B_DATA1# TMDS_B_DATA0 [8]

n
TMDS_B_DATA1 TMDS_B_DATA0# HCB1608KF-600T30_0603 10 Pull-Low 10K_1 NC
[8] TMDS_B_DATA1 TMDS_B_DATA0# [8]
TMDS_B_DATA2# TMDS_B_CLK C451 C452 32 Pull-High 10K_1 Pull-High 4.7K_1
[8] TMDS_B_DATA2# TMDS_B_CLK [8]
TMDS_B_DATA2 TMDS_B_CLK# 1uF/10V_0603_X5R 10uF/6.3V_0805_X5R

I
+3.3V_DVI [8] TMDS_B_DATA2 TMDS_B_CLK# [8]
34 Pull-Low 10K_1 Note 2
C465 100nF/10V_X7R C463 100nF/10V_X7R
35 Pull-Low 10K_1 Note 2

s
R474 R473 Note 1 - PS8101 Equalization
48

47

46

45

44

43

42

41

40

39

38

37
@4.7K @4.7K U18 R404 @4.7K +3.3V_DVI
PC0, PC1 [Pin3/4] 1.65Gbps Comment

e
IN_D4-

IN_D3-

IN_D2-

IN_D1-
IN_D4+

VCC3V_8

IN_D3+

GND10

IN_D2+

VCC3V_7

IN_D1+

GND9
R405 @4.7K
00 8 dB
+3.3V_DVI C428 100nF/10V_X7R 1 36
GND1 GND8
01 12 dB

d
2 35 7318_FUN4 R403 10K_1
VCC3V_1 FUNCTION4/CFG
10 4 dB Recommended
R463 10K_1 7318_FUN1 3 34 7318_FUN3 R406 10K_1

i
FUNCTION1/PC0 FUNCTION3/DDCBUF_EN
11 0 dB
R464 10K_1 7318_FUN2 4 33 +3.3V_DVI C439 100nF/10V_X7R
FUCNTION2/PC1 VCC3V_6
B 7318_DCC_EN R407 10K_1 B
5 32 +3.3V_DVI

v
R465 1.2K 7318_ANG1 6
GND2

ANALOG1(REXT)
CH7318/ DDC_EN

GND7 31
Note 2 - PS8101 DDCBUF_EN / CFG Pin 34/35

TMDS_B_HDP 7318_HPD# R388 0R DDCBUF_EN High = DDC Active Buffer Enable


[8] TMDS_B_HDP 7 HPD_SOURCE
PS8101 HPD_SINK 30 DVI_HDP# [18]

o
(7318_SDA/SCL_SE Pull-High 1.5K)
CRT_DDC_DATA R475 @0R 7318_SDA_SE 8 29 DVI_DDC_DATA
[8] CRT_DDC_DATA SDA_SOURCE SDA_SINK DVI_DDC_DATA [18]
SDVO_CTRLDATA R476 0R Low = DDC Active Buffer Disable
[7] SDVO_CTRLDATA
CRT_DDC_CLK R478 @0R 7318_SCL_SE 9 28 DVI_DDC_CLK (7318_SDA/SCL_SE Pull-High 47K)

r
[8] CRT_DDC_CLK SCL_SOURCE SCL_SINK DVI_DDC_CLK [18]
SDVO_CTRLCLK R477 0R
[7] SDVO_CTRLCLK
R479 10K_1 7318_ANG2 10 27
ANALOG2/RT_EN# GND6
CFG High = Low-level input vol <0.44v
11 26 +3.3V_DVI C433 100nF/10V_X7R Low-level output vol 0.66v
VCC3V_2 VCC3V_5

P
12 25 7318_TMDS_EN R408 10K_1 Low = Low-level input vol <0.40v
OUT_D4+

OUT_D3+

OUT_D2+

OUT_D1+
VCC3V_3

VCC3V_4

+3.3V_DVI +3.3V_DVI
OUT_D4-

OUT_D3-

OUT_D2-

OUT_D1-

C449 100nF/10V_X7R GND3 TMDS_EN


Low-level output vol 0.60v
GND4

GND5

49 R409 @100K_1
GND11

CH7318 PS8101 DDC Buffering Config Table


7318_OUT_D4+ 13

7318_OUT_D4- 14

15

7318_OUT_D3+ 16

7318_OUT_D3- 17

18

7318_OUT_D2+ 19

7318_OUT_D2- 20

21

7318_OUT_D1+ 22

7318_OUT_D1- 23

24

+3.3V_DVI R466 2.2K 7318_SDA_SE QFN48_7MA


R467 2.2K 7318_SCL_SE DDC_EN, DDCBUF_EN,OE# DDC Passive Buffer DDC Active Buffer
Pin 32/34/25
C429 100nF/10V_X7R C464 100nF/10V_X7R 1,0,x ON OFF
1,1,0 OFF ON
DVI_B_DATA2 R459 0R R397 0R DVI_B_CLK#
[18] DVI_B_DATA2 DVI_B_CLK# [18]
1,1,1 OFF OFF
R468 @6.8R Z1203 C467 @0.7pF/50V_NP0 @0.7pF/50V_NP0 C431 Z1205 R396 @6.8R
A
R458 @75R R410 @75R 0,x,x OFF OFF A
DVI_B_DATA2# R456 0R R415 0R DVI_B_CLK
[18] DVI_B_DATA2# DVI_B_CLK [18]
DVI_B_DATA1 R446 0R R427 0R DVI_B_DATA0#
[18] DVI_B_DATA1 DVI_B_DATA0# [18]
R436 @6.8R Z1204 C440 @0.7pF/50V_NP0 @0.7pF/50V_NP0 C436 Z1206 R423 @6.8R

DVI_B_DATA1#
R443
R441
@75R
0R
R429
R434
@75R
0R DVI_B_DATA0
ECS COMPUTER CORP.
[18] DVI_B_DATA1# DVI_B_DATA0 [18]
Title
+3.3V_DVI +3.3V_DVI
DVI SHIFTER/SMART PWR
Size Document Number Rev
A
3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 12 of 36
5 4 3 2 1
5 4 3 2 1

Layout: CLK_VDD_IO +3.3V +1.5V


Put decoupling caps close to L64

e
ICS9LPR365 power pin. HCB1608KF-600T30_0603 20 mil / 0.5A
CLK_VDD
L61

c
C513 C506 20 mil / 0.5A @HCB1608KF-600T30_0603 20 mil / 0.5A
4.7uF/10V_0805_X5R @4.7uF/10V_0805_X5R
D D

C153 C147 Layout:

n
Layout: @4.7uF/10V_0805_X5R 4.7uF/10V_0805_X5R Put decoupling caps close to ICS9LPR365 power pin.
Put decoupling caps close to ICS9LPR365 power pin.
+3.3V +3.3V U23

e
L16
HCB1608KF-600T30_0603 20 mil / 0.5A C162 C166 C140 C142 C164 C141
R546 @10K_1 CLKREQ_A# CLK_VDD 2 12 100nF/10V_X7R 100nF/10V_X7R 100nF/10V_X7R 100nF/10V_X7R 100nF/10V_X7R 100nF/10V_X7R
R552 @10K_1 CLKREQ_B# VDD_PCI VDD_I/O
9 20

r
VDD_48 VDD_PLL3_I/O
+ 16 VDD_PLL3 VDD_SRC_I/O_1 26
R576 10K_1 CLKREQ_H# C526 C139 C145 C146 C158 C157 C163 39 36
R533 10K_1 CLKREQ_G# 100uF/6.3V_3528_NEC 100nF/10V_X7R 100nF/10V_X7R 100nF/10V_X7R 100nF/10V_X7R 100nF/10V_X7R 100nF/10V_X7R VDD_SRC VDD_SRC_I/O_2
55 VDD_CPU VDD_SRC_I/O_3 45

e
61 49 R591 @10K_1 CLK_VDD
VDD_REF VDD_CPU_I/O
37 PM_STPCPU#
CPU_STOP# PM_STPCPU# [15]

f
38 PM_STPPCI#
PCI_STOP# PM_STPPCI# [15]
Reserved FOR EMI 56 CLK_PWRGD
CKPWRGD/PD# CLK_PWRGD [15]
CLK_XTAL_OUT 59 54 CPU0 R602 0R CLK_CPU_BCLK

e
XTAL_OUT CPU_0 CLK_CPU_BCLK [5]
C503 @10pF/50V_NP0 PCI_3 CLK_XTAL_IN 60 53 CPU0# R601 0R CLK_CPU_BCLK#
XTAL_IN CPU_0# CLK_CPU_BCLK# [5]
Y3 CLK_SATA_OE# R547 475R_1 CLKREQ_A# 1 51 CPU1 R600 0R CLK_MCH_BCLK
[15] CLK_SATA_OE# PCI_0/CLKREQ_A# CPU_1_MCH CLK_MCH_BCLK [7]
C521 @10pF/50V_NP0 PIC_4/LCDCK_SEL CLK_MCH_OE# R553 475R_1 CLKREQ_B# 3 50 CPU1# R599 0R CLK_MCH_BCLK#
[7] CLK_MCH_OE# PCI_1/CLKREQ_B# CPU_1_MCH# CLK_MCH_BCLK# [7]

r
PCI_2/TIME 4 47 SRC8 R157 0R CLK_PCIE_NC
PCI_2/TME SRC_8/CPU_ITP CLK_PCIE_NC [19]
C498 @10pF/50V_NP0 PCIF_5/ITP_EN CL 14.31818M-20-20-KT-D Ce CLK_PCI_LPC R535 33R PCI_3 5 46 SRC8# R158 0R CLK_PCIE_NC#
[24] CLK_PCI_LPC PCI_3 SRC_8#/CPU_ITP# CLK_PCIE_NC# [19]
CLK_PCI_DBG R566 33R PIC_4/LCDCK_SEL 6
[23] CLK_PCI_DBG PCI_4/27_SELECT
C529 C528 CLK_PCIF_ICH R520 33R PCIF_5/ITP_EN 7
[14] CLK_PCIF_ICH PCIF_5/ITP_EN
C497 @10pF/50V_NP0 CLKBSEL0 20pF/50V_NP0 33pF/50V_NP0 48

le
CLK_DEBUG48 R132 33R NC
[23] CLK_DEBUG48
C154 @10pF/50V_NP0 CLKBSEL1 CLK_USB48 R131 33R CLKBSEL0 10
[15] CLK_USB48 USB_48MHz/FS_A
CLKBSEL1 57
C C539 @10pF/50V_NP0 CLKBSEL2 FS_B/TEST_MODE LCDCK R528 0R DREFSSCLK C
LCDCLK/27M 17 DREFSSCLK [7]
18 LCDCK# R527 0R DREFSSCLK#
LCDCLK#/27M_SS DREFSSCLK# [7]
CLK_REF_ICH R176 33R CLKBSEL2 62
[15] CLK_REF_ICH REF/FS_C/TEST_SEL
C500 @10pF/50V_NP0 CLK_PCI_LPC

t
Ce = 2*CL - ( Cs + Ci )
C522 @10pF/50V_NP0 CLK_PCI_DBG DREFCLK R530 0R DOT_96 13 21 SRC2 R145 0R CLK_PCIE_SATA
[7] DREFCLK SRC_0/DOT_96 SRC_2/SATAT CLK_PCIE_SATA [14]
CL = Crystal Load Cap = 20P DREFCLK# R529 0R DOT_96# 14 22 SRC2# R146 0R CLK_PCIE_SATA#
[7] DREFCLK# SRC_0#/DOT_96# SRC_2#/SATAC CLK_PCIE_SATA# [14]
C493 @10pF/50V_NP0 CLK_PCIF_ICH 24 SRC3 R147 0R CLK_PCIE_1394
SRC_3/CLKREQ_C# CLK_PCIE_1394 [21]

n
Ci = IC internal Cap = 5P SMB_CLK_GEN 64 25 SRC3# R148 0R CLK_PCIE_1394#
[24] SMB_CLK_GEN SCL SRC_3#/CLKREQ_D# CLK_PCIE_1394# [21]
C137 @10pF/50V_NP0 CLK_DEBUG48 SMB_DATA_GEN 63 27 SRC4 R526 0R CLK_PCIE_3GPLL
[24] SMB_DATA_GEN SDA SRC_4 CLK_PCIE_3GPLL [7]
Cs = 2P 28 SRC4# R525 0R CLK_PCIE_3GPLL#
SRC_4# CLK_PCIE_3GPLL# [7]
C136 @10pF/50V_NP0 CLK_USB48 SRC6 R596 0R CLK_PCIE_ICH

I
SRC_6 41 CLK_PCIE_ICH [15]
Ce = Crystal external Cap = 33P 40 SRC6# R595 0R CLK_PCIE_ICH#
SRC_6# CLK_PCIE_ICH# [15]
C173 @10pF/50V_NP0 CLK_REF_ICH 44 CLKREQ_F# R598 0R CLK_NC_OE#
SRC_7/CLKREQ_F# CLK_NC_OE# [19]
8 43 CLKREQ_E# R597 0R CLKREQ_E#_R
VSS_PCI SRC_7#/CLKREQ_E# TP12
11 30 SRC9 R524 0R CLK_PCIE_MINI1
VSS_48 SRC_9 CLK_PCIE_MINI1 [17]
15 31 SRC9# R523 0R CLK_PCIE_MINI1#
VSS_I/O SRC_9# CLK_PCIE_MINI1# [17]

s
19 34 SRC10 R593 0R CLK_PCIE_MINI2
VSS_PLL3 SRC_10 CLK_PCIE_MINI2 [17]
23 35 SRC10# R594 0R CLK_PCIE_MINI2#
VSS_SRC_1 SRC_10# CLK_PCIE_MINI2# [17]
29 33 CLKREQ_H# R557 0R CLK_MINI2_OE#
VSS_SRC_2 SRC_11/CLKREQ_H# CLK_MINI2_OE# [17]
42 32 CLKREQ_G# R522 0R CLK_MINI1_OE#

e
VSS_SRC_3 SRC_11#/CLKREQ_G# CLK_MINI1_OE# [17]
52 VSS_CPU
58 VSS_REF
R130 2.2K CLKBSEL0
[7] CLK_BSEL0

d
R154 0R CLKBSEL1 ICS9LPRS365BG
[7] CLK_BSEL1
M-TSSOP64-05M

i
R174 10K_1 CLKBSEL2
[7] CLK_BSEL2

B B

v
Reserved for ICS9LPRS365

o
0 = Pin17/18 LCDCLK & DOT_96 for internal 0 = Overclocking of CPU and SRC allowed
+3.3V
CPU, MCH Frequency Selection Table graphic controller support 1 = Overclocking of CPU and SRC NOT

r
FSLC FSLB FSLA Host Clock SRC PCI REF USB DOT 1 = Pin17/18 27M & 27M_SS & SRC_0 for allowed
BSEL2 BSEL1 BSEL0 Frequency MHz MHz MHz MHz MHz MHz external graphic controller support

1 0 1 100 PIC_4/LCDCK_SEL R560

P
0 0 1 133 @10K_1

0 1 1 166 PCI_2/TIME
0 1 0 200 100 33.3 14. 48 96 R574
10K_1
0 0 0 266 318
1 0 0 333 R561
10K_1
1 1 0 400
1 1 1 Reserved
0= Pin46/47 SRC output.
1= Pin46/47 ITP output.
A A

CPU / SRC / Function / REQ# Table PCIF_5/ITP_EN

SRC CPU_0 CPU_1 SRC0/DOT_96 SRC1/LCDCLK SRC2/SATAT SRC3 SRC4 SRC6 SRC7 SRC8 SRC9 SRC10
R521
ECS COMPUTER CORP.
CLK_REQ# NC NC NC NC CR#_A NC CR#_B NC NC CR#_F CR#_G CR#_H 10K_1
Title
CLOCK GENERATOR
Function CPU CLK_CPU NB CLK_MCH NB DREFCLK NB DREFSS SB CLK_PCIE SB CLK_PCIE NB CLK_PCIE SB CLK_PCIE NC SB CLK_PCIE SB CLK_PCIE SB CLK_PCIE
Size Document Number Rev
_BCLK _BCLK CLK _SATA _1394 _3GPLL _ICH _NC _MINI1 _MINI2 A
3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 13 of 36
5 4 3 2 1
5 4 3 2 1

#4 #3
+3.3V_RTC C512 10pF/50V_NP0

3
1
R118 D1 C502
499R_1 BAT54 1uF/10V_0603_X5R 32.768KHz Crystal
AUX_RTC A C R565 Y2

c
+3.3V_AUX
10M_0603 32.768K-12.5-20-S-CM200
PCB Silksceen.

4
2
D R120 D2 D
CN30 1K_1 BAT54 C499 C524 10pF/50V_NP0
CM_BAT CM_RTC A 1uF/10V_0603_X5R

n
1 C
2 #1 #2
CON-WTB-85205-02001-ACE C175 J2

e
85205-02L 1uF/10V_0603_X5R JUMPER OPEN
1 2 U26A
RTC_X1 C23 K5 LPC_AD0
RTCX1 FWH0/LAD0 LPC_AD0 [23,24]
J1 RTC_X2 C24 K4 LPC_AD1

r
RTCX2 FWH1/LAD1 LPC_AD1 [23,24]
JUMPER OPEN L6 LPC_AD2
FWH2/LAD2 LPC_AD2 [23,24]
1 2 R531 20K_1 RTC_RST# A25 K2 LPC_AD3
RTCRST# FWH3/LAD3 LPC_AD3 [23,24]

RTC
LPC
R170 20K_1 SRTC_RST# F20 SRTCRST#

e
R577 1M SM_INTRUDER# C22 K3 LPC_FRAME#
INTRUDER# FWH4/LFRAME# LPC_FRAME# [23,24]
B22 J3 LPC_DRQ#0
INTVRMEN LDRQ0# LPC_DRQ#0 [23]

f
+3.3V_RTC R558 332K_1 Z1401 A22 J1 LPC_DRQ#1 R242 @10K_1 +3.3V
LAN100_SLP LDRQ1#/GPIO23 R369 8.2K
GLAN_CLK E25 N7 H_A20GATE
[20] GLAN_CLK GLAN_CLK A20GATE H_A20GATE [24]
AJ27 H_A20M# R543 @56R +1.05V

e
A20M# H_A20M# [5]
LAN_RSTSYNC C13
[20] LAN_RSTSYNC LAN_RSTSYNC
DPRSTP# AJ25 H_DPRSTP#_R R136 0R H_DPRSTP#
H_DPRSTP# [5,7,27]
LAN_RXD0 F14 AE23 H_DPSLP#_R R143 0R H_DPSLP#

LAN / GLAN
[20] LAN_RXD0 LAN_RXD0 DPSLP# H_DPSLP# [5]

r
LAN_RXD1 G13
[20] LAN_RXD1 LAN_RXD1
LAN_RXD2 D14 R559 @56R +1.05V
[20] LAN_RXD2 LAN_RXD2
FERR# AJ26 H_FERR#_R R134 56R H_FERR#
H_FERR# [5]
LAN_TXD0 D13
[20] LAN_TXD0 LAN_TXD0
LAN_TXD1 D12 AD22 H_PWRGD R534 56R +1.05V

le
[20] LAN_TXD1 LAN_TXD1 CPUPWRGD H_PWRGD [5]
LAN_TXD2 E13 AF25 H_IGNNE#
[20] LAN_TXD2 LAN_TXD2 IGNNE# H_IGNNE# [5]

CPU
+3.3V R213 @1K_1 HDA_SDOUT
+3.3VS R196 10K_1 ICH_GPIO56 B10 AE22 H_INIT#
GPIO56 INIT# H_INIT# [5]
C R166 @1K_1 AG25 H_INTR C
[15] ICH_TP3 INTR H_INTR [5]
B28 L3 H_RCIN#
GLAN_COMPI RCIN# H_RCIN# [24]
@22pF/50V_NP0 C187 +1.5V R121 24.9R_1 Z1402 B27 AF23 H_NMI
GLAN_COMPO NMI H_NMI [5]
R238 10K_1

t
XOR Chain Entrance Strap - to be updated +3.3V
HDA_BIT_CLK R201 0R HDA_BIT_CLK_R AF6 AF24 H_SMI#_R R140 0R H_SMI#
[22] HDA_BIT_CLK HDA_BIT_CLK SMI# H_SMI# [5]
ICH9_TP3 HDA_SDOUT Description HDA_SYNC R216 0R HDA_SYNC_R AH4 Layout:
[22] HDA_SYNC HDA_SYNC
STPCLK# AH27 H_STPCLK# H_STPCLK# [5] Place close to
0 0 RSVD HDA_RST# AE7 ICH9M pin AG26.
[22] HDA_RST# HDA_RST#

n
0 1 Enter XOR Chain @22pF/50V_NP0 C209 AG26 H_THERMTRIP_R R137 54.9R_1 PM_THRMTRIP#
THRMTRIP# PM_THRMTRIP# [5,7]
1 0 Normal Operation DEFAULT HDA_SDIN0 AF4
[22] HDA_SDIN0 HDA_SDIN0
1 1 Set PCIE port config bit 1 HDA_SDIN1 AG4 AG27 ICH_TP12 R542 56R +1.05V
[22] HDA_SDIN1 HDA_SDIN1 TP12 TP7

IHDA
I
AH3 HDA_SDIN2
HDA_SDIN3 AE5
TP18 HDA_SDIN3
AH11 Layout:
HDA_SDOUT SATA4RXN
[22] HDA_SDOUT AG5 AJ11 Distance between the ICH9-M and cap on the "P"
+3.3VS HDA_SDOUT SATA4RXP
SATA4TXN AG12 signal should be identical distance between the
+3.3V R209 @8.2K HDA_DOCK_EN# AG7 AF12 ICH9-M and cap on the "N" signal for same pair.
HDA_DOCK_EN#/GPIO33 SATA4TXP

s
NOTE: C125 100nF/10V_X7R AE8 HDA_DOCK_RST#/GPIO34 SATA_RXN5
Buffer to reduce loading on PLT_RST#. AH9 SATA_RXN5 [23]
SATA5RXN
5

R211 @10K_1 ICH_SATA_LED# AG8 AJ9 SATA_RXP5


SATALED# SATA5RXP SATA_RXP5 [23]
1 AE10 SATA_TXN5_R C179 10nF/25V_X7R SATA_TXN5

e
SATA5TXN SATA_TXN5 [23]
BUF_PLT_RST# 4 SATA_RXN0 AJ16 AF10 SATA_TXP5_R C183 10nF/25V_X7R SATA_TXP5
[7,17,21,23,24] BUF_PLT_RST# [17] SATA_RXN0 SATA0RXN SATA5TXP SATA_TXP5 [23]
2 PLT_RST# SATA_RXP0 AH16
[17] SATA_RXP0

SATA
SATA_TXN0 C169 10nF/25V_X7R SATA_TXN0_R AF17 SATA0RXP
[17] SATA_TXN0 SATA0TXN SATA_CLKN AH18 CLK_PCIE_SATA# CLK_PCIE_SATA# [13]
U5 SATA_TXP0 C167 10nF/25V_X7R SATA_TXP0_R AG17 AJ18 CLK_PCIE_SATA
[17] SATA_TXP0 CLK_PCIE_SATA [13]
3

SATA0TXP SATA_CLKP

d
R122 100K_1 74AHC1G08
M-SC70-5 SATA_RXN1 AH13 AJ7 SATA_RBIAS_PN R199 24.9R_1
[17] SATA_RXN1 SATA1RXN SATARBIAS#
NC7SZ08P5X SATA_RXP1 AJ13 AH7

i
[17] SATA_RXP1 SATA1RXP SATARBIAS
SATA_TXN1 C178 10nF/25V_X7R SATA_TXN1_R AG14 Layout:
[17] SATA_TXN1 SATA1TXN
R614 @0R SATA_TXP1 C176 10nF/25V_X7R SATA_TXP1_R AF14 Place close to
[17] SATA_TXP1 SATA1TXP
Layout: ICH9M pin AJ7/
B ICH9M REV 1.0 B
Distance between the ICH9-M and cap on the "P" AH7.

v
signal should be identical distance between the PBGA676_ICH9
+3.3V ICH9-M and cap on the "N" signal for same pair.
U26B
R650 8.2K PCI_FRAME# D11 F1 PCI_REQ#0
AD0 REQ0#

o
R228 8.2K PCI_IRDY# PCI_GNT#0
R219 8.2K PCI_TRDY#
C8
D9
AD1 PCI GNT0# G4
B6 PCI_REQ#1 NOTE:
R220 8.2K PCI_STOP# AD2 REQ1#/GPIO50
E12 A7 SST, PECI, PWM[2:0] are called TP in the
R241 8.2K PCI_SERR# AD3 GNT1#/GPIO51 PCI_REQ#2
E9 F13 ICH9M symbol since they are not

r
R653 8.2K PCI_DEVSEL# AD4 REQ2#/GPIO52
C9 AD5 GNT2#/GPIO53 F12 supported on Montevina Mobile Platform. A16 swap override Strap / Top-Block Swap Override
R658 8.2K PCI_PERR# E10 E6 PCI_REQ#3 TACH[3:0] pins are also not supported on
R231 8.2K PCI_LOCK# B7
AD6 REQ3#/GPIO54
F6 PCI_GNT#3 jumper
AD7 GNT3#/GPIO55 the Montevina Platform.
R246 8.2K PCI_REQ#0 C7
R648 8.2K PCI_REQ#1 AD8
C5 D8 PCI_GNT#3 Low = A16 swap override/Top-Block Swap

P
R188 8.2K PCI_REQ#2 AD9 C/BE0#
G11 AD10 C/BE1# B4 Override enabled.
R644 8.2K PCI_REQ#3 F8 D6
R222 @8.2K PCI_CBE#3 AD11 C/BE2# PCI_CBE#3 DEFAULT
F11 AD12 C/BE3# A5 High = Default. (Jumper 1-X)
R227 @8.2K PCI_PAR E7
R666 @8.2K PCI_PME# AD13 PCI_IRDY#
A3 AD14 IRDY# D3
D2 E3 PCI_PAR
AD15 PAR PCI_RST# PCI_GNT#3 R656 @1K_1
F10 AD16 PCIRST# R1 PCI_RST# [23]
R243 8.2K INT_PIRQA# D5 C6 PCI_DEVSEL#
R248 8.2K INT_PIRQB# AD17 DEVSEL# PCI_PERR#
D10 AD18 PERR# E4
R205 8.2K INT_PIRQC# B3 C2 PCI_LOCK#
R225 8.2K INT_PIRQD# AD19 PLOCK# PCI_SERR# PCI_GNT#0 R249 @1K_1
F7 AD20 SERR# J4
R244 8.2K INT_PIRQE# C3 A4 PCI_STOP#
R204 8.2K INT_PIRQF# AD21 STOP# PCI_TRDY# SPI_CS#1 R152 @1K_1
F3 AD22 TRDY# F5 [15] SPI_CS#1
R247 8.2K INT_PIRQG# F4 D7 PCI_FRAME#
R245 8.2K INT_PIRQH# AD23 FRAME#
C1 AD24
G7 AD25 PLTRST# C14 PLT_RST#
A H7 AD26 PCICLK D4 CLK_PCIF_ICH CLK_PCIF_ICH [13] A
D1 AD27 PME# R2 PCI_PME# NOTE:
G5 GNT#0 and SPI_CS#1 have a weak internal pull up 20K.
AD28
H6 AD29
G1 AD30
H3 AD31
Boot BIOS Strap ECS COMPUTER CORP.
INT_PIRQA# J5
Interrupt I/F H4 INT_PIRQE# PCI_GNT#0 SPI_CS#1 Boot BIOS Location
INT_PIRQB# PIRQA# PIRQE#/GPIO2 INT_PIRQF# Title
E1 PIRQB# PIRQF#/GPIO3 K6
INT_PIRQC#
INT_PIRQD#
J6 PIRQC# PIRQG#/GPIO4 F2 INT_PIRQG#
INT_PIRQH#
0 1 SPI SB ICH9M 1 of 3
C4 PIRQD# PIRQH#/GPIO5 G2 1 0 PCI
1 1 LPC DEFAULT Size Document Number Rev
A
ICH9M REV 1.0
PBGA676_ICH9
3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 14 of 36
5 4 3 2 1
5 4 3 2 1

U26D
PCIE_RXN3_NC R498 0R_0603 PCIE_RXN1_R N29 V27 DMI_RXN0_R R513 0R DMI_RXN0
[19] PCIE_RXN3_NC PERN1 DMI0RXN DMI_RXN0 [7]
PCIE_RXP3_NC R499 0R_0603 PCIE_RXP1_R N28 V26 DMI_RXP0_R R512 0R DMI_RXP0
+3.3V [19] PCIE_RXP3_NC PERP1 DMI0RXP DMI_RXP0 [7]
PCIE_TXN3_NC C490 100nF/25V_0603_X7R PCIE_TXN1_C P27 U29 DMI_TXN0_R R501 0R DMI_TXN0

Direct Media Interface


[19] PCIE_TXN3_NC PETN1 DMI0TXN DMI_TXN0 [7]
PCIE_TXP3_NC C491 100nF/25V_0603_X7R PCIE_TXP1_C P26 U28 DMI_TXP0_R R500 0R DMI_TXP0
[19] PCIE_TXP3_NC PETP1 DMI0TXP DMI_TXP0 [7]
HDA_SPKR R203 @1K_1
PCIE_RXN2_MINI2 R496 0R_0603 PCIE_RXN2_R L29 Y27 DMI_RXN1_R R515 0R DMI_RXN1
[17] PCIE_RXN2_MINI2 PERN2 DMI1RXN DMI_RXN1 [7]
PCIE_RXP2_MINI2 R497 0R_0603 PCIE_RXP2_R L28 Y26 DMI_RXP1_R R514 0R DMI_RXP1
[17] PCIE_RXP2_MINI2 PERP2 DMI1RXP DMI_RXP1 [7]

e
No Reboot Strap PCIE_TXN2_MINI2 C488 100nF/25V_0603_X7R PCIE_TXN2_C M27 W29 DMI_TXN1_R R503 0R DMI_TXN1
[17] PCIE_TXN2_MINI2 PETN2 DMI1TXN DMI_TXN1 [7]
PCIE_TXP2_MINI2 C489 100nF/25V_0603_X7R PCIE_TXP2_C M26 W28 DMI_TXP1_R R502 0R DMI_TXP1
[17] PCIE_TXP2_MINI2 PETP2 DMI1TXP DMI_TXP1 [7]

PCI-Express
HDA_SPKR Low = Default. DEFAULT PCIE_RXN1_MINI1 R494 0R_0603 PCIE_RXN3_R J29 AB27 DMI_RXN2_R R517 0R DMI_RXN2

c
[17] PCIE_RXN1_MINI1 PERN3 DMI2RXN DMI_RXN2 [7]
High = No Reboot. PCIE_RXP1_MINI1 R495 0R_0603 PCIE_RXP3_R J28 AB26 DMI_RXP2_R R516 0R DMI_RXP2
[17] PCIE_RXP1_MINI1 PERP3 DMI2RXP DMI_RXP2 [7]
PCIE_TXN1_MINI1 C486 100nF/25V_0603_X7R PCIE_TXN3_C K27 AA29 DMI_TXN2_R R505 0R DMI_TXN2
[17] PCIE_TXN1_MINI1 PETN3 DMI2TXN DMI_TXN2 [7]
D PCIE_TXP1_MINI1 C487 100nF/25V_0603_X7R PCIE_TXP3_C K26 AA28 DMI_TXP2_R R504 0R DMI_TXP2 D
[17] PCIE_TXP1_MINI1 PETP3 DMI2TXP DMI_TXP2 [7]
PCIE_RXN4_1394 R492 0R_0603 PCIE_RXN4_R AD27 DMI_RXN3_R R519 0R DMI_RXN3

n
[21] PCIE_RXN4_1394 G29 PERN4 DMI3RXN DMI_RXN3 [7]
PCIE_RXP4_1394 R493 0R_0603 PCIE_RXP4_R G28 AD26 DMI_RXP3_R R518 0R DMI_RXP3
[21] PCIE_RXP4_1394 PERP4 DMI3RXP DMI_RXP3 [7]
D16 BAT54 PCIE_TXN4_1394 C484 100nF/25V_0603_X7R PCIE_TXN4_C H27 AC29 DMI_TXN3_R R507 0R DMI_TXN3
[21] PCIE_TXN4_1394 PETN4 DMI3TXN DMI_TXN3 [7]
NC_WAKE_UP# C A PCIE_TXP4_1394 C485 100nF/25V_0603_X7R PCIE_TXP4_C H26 AC28 DMI_TXP3_R R506 0R DMI_TXP3
[19] NC_WAKE_UP# [21] PCIE_TXP4_1394 PETP4 DMI3TXP DMI_TXP3 [7]

e
R163 @0R PCIe LANE 6 SELECTION PCIE_RXN5 R490 0R_0603 PCIE_RXN5_R E29 T26 CLK_PCIE_ICH#
TP4 PERN5 DMI_CLKN CLK_PCIE_ICH# [13]
Layout: PCIE_RXP5 R491 0R_0603 PCIE_RXP5_R E28 T25 CLK_PCIE_ICH
TP3 PERP5 DMI_CLKP CLK_PCIE_ICH [13]
D15 BAT54 Lane 6 can be connected to LAN or Slot 5 depending PCIE_TXN5 C482 100nF/25V_0603_X7R PCIE_TXN5_C F27

r
TP6 PETN5
MINICD1_WAKE# C A on the stuffing option described below. PCIE_TXP5 C483 100nF/25V_0603_X7R PCIE_TXP5_C F26 AF29 DMI_IRCOMP_R R135 24.9R_1 +1.5V
[17] MINICD1_WAKE# TP5 PETP5 DMI_ZCOMP
Placed the components such that CAP1 (0603) Pad2 & CAP2 Pad1 DMI_IRCOMP AF28
R155 @0R are next to each other as shown above. PCIE_RXN6_LAN R489 0R_0603 PCIE_RXN6_R C29
[20] PCIE_RXN6_LAN PERN6/GLAN_RXN

e
The Placement is such that a 0603 Capacitor can be placed there. PCIE_RXP6_LAN R488 0R_0603 PCIE_RXP6_R C28
[20] PCIE_RXP6_LAN PERP6/GLAN_RXP
D3 BAT54 Similar placement followed for CAP3 and CAP4. This approach is PCIE_TXN6_LAN C481 100nF/25V_0603_X7R PCIE_TXN6_C D27 AC5 USB_PN0
[20] PCIE_TXN6_LAN PETN6/GLAN_TXN USBP0N USB_PN0 [23]
MINICD2_WAKE# C A PCIE_TXP6_LAN C480 100nF/25V_0603_X7R PCIE_TXP6_C D26 AC4 USB_PP0 USB Ports Table
[17] MINICD2_WAKE# same for RX Path also. [20] PCIE_TXP6_LAN PETP6/GLAN_TXP USBP0P USB_PP0 [23]

f
AD3 USB_PN1
USBP1N USB_PN1 [19]
R151 @0R PCIE_WAKE# HDCP_CLK R128 @15R SPI_CLK_R D23 AD2 USB_PP1 USBP0 M/B eSATA
SPI_CLK USBP1P USB_PP1 [19]
+3.3VS SPI_CS#0 R127 @15R SPI_CS#0_R D24 AC1 USB_PN2
D4 @BAT54 SPI_CS#1 R160 15R SPI_CS#1_R SPI_CS0# USBP2N USB_PP2
USB_PN2 [19] USBN0 USB_0
F23 AC2

e
[14] SPI_CS#1 SPI_CS1#/GPIO58/CLGPIO6 USBP2P USB_PP2 [19]
LAN_WAKE# C A LAN_WOL_EN PM_RI# R182 10K_1 AA5 USB_PN3 USBP1 DC-IN BD
[20] LAN_WAKE# USBP3N USB_PN3 [19]
HDCP_MOSI R129 @15R SPI_MOSI_R USB_PP3
R180 @0R SMB_CLK_ME R186 10K_1 HDCP_MIOS R126 @15R SPI_MISO_R
D25
E23
SPI_MOSI SPI USBP3P AA4
AB2 USB_PN4
USB_PP3 [19] USBN1 USB_1
SPI_MISO USBP4N USB_PN4 [17]

r
SMB_DATA_ME R606 10K_1 AB3 USB_PP4 USBP2 DC-IN BD
USBP4P USB_PP4 [17]
R235 10K_1 USB_OC#0 N4 AA1 USB_PN5
PCIE_WAKE# R156 1K_1
+3.3VS
R226 10K_1 USB_OC#1 OC0#/GPIO59 USBP5N USB_PP5
USB_PN5 [17] USBN2 USB_2
N5 OC1#/GPIO40 USBP5P AA2 USB_PP5 [17]
R452 +3.3V R218 10K_1 USB_OC#2 USB_PN6 WEBCAM
N6 OC2#/GPIO41 USB
USBP6N W5 USB_PN6 [19] USBP3
PM_BATLOW# R190 8.2K @4.7K R215 10K_1 USB_OC#3 P6 W4 USB_PP6
USB_3

le
OC3#/GPIO42 USBP6P USB_PP6 [19] USBN3
HDCP_WP# R663 10K_1 USB_OC#4 M1 Y3 USB_PN7
OC4#/GPIO43 USBP7N USB_PN7 [23]
LANPHY_EN R200 @10K_1 R664 10K_1 USB_OC#5 N2 Y2 USB_PP7 USBP4 MINI CARD_1
OC5#/GPIO29 USBP7P USB_PP7 [23]
R237 10K_1 USB_OC#6 M4 W1 USB_PN8
C Z1503 R181 100R_1 ICH_GPIO13 R171 @10K_1 R236 10K_1 USB_OC#7 OC6#/GPIO30 USBP8N USB_PP8
USB_PN8 [19] USBN4 USB_4 C
+3.3V
U21
512K R442 R234 10K_1 USB_OC#8
M3 OC7#/GPIO31 USBP8P W2 USB_PP8 [19]
N3 OC8#/GPIO44 USBP9N V2 USBP5 MINI CARD_2
ICH_GPIO28 R214 @43K @4.7K R665 10K_1 USB_OC#9 N1 V3
R191 2.2K R175 4.7K R221 10K_1 USB_OC#10 OC9#/GPIO45 USBP9P USBN5 USB_5

t
+3.3V +3.3V 1 8 P5 U5
G

AMT_RST# R187 10K_1 CS# VCC HDCP_HOLD# R229 10K_1 USB_OC#11 OC10#/GPIO46 USBP10N
2 DOUT HOLD# 7 P3 OC11#/GPIO47 USBP10P U4 USBP6 NEW CARD
3 6 HDCP_CLK U1 USB_PN11
SMB_CLK SB_SMB_CLK WP# CLK HDCP_MOSI R232 22.6R_1 USBRBIAS USBP11N USB_PP11
TP14 USBN6 USB_6
D S SB_SMB_CLK [8,11,17] 4 GND DIN 5 AG2 USBRBIAS USBP11P U2 TP15
+3.3V Finger PR
AG1 USBRBIAS# USBP7

n
Q16 FET-2N7002E
100nF/10V_X7R C130 C444 ICH9M REV 1.0 USBN7 USB_7
@AMT25F512A
Z1504 R206 100R_1 +3.3V M-SOP8B @100nF/10V_X7R PBGA676_ICH9 USBP8 Bluetooth

5
+3.3V

I
VCORE_CLK_EN# USBN8 USB_8
1
+3.3V R212 2.2K R198 4.7K +3.3V 4 VR_PWRGD_CLKEN SATA Device Status CLK_SATA_OE# R239 10K_1 USBP9
G

2 PM_THRM# R555 8.2K N/A


+3.3V Presence = Pull Low. INT_SERIRQ R202 10K_1 USBN9
VR_PWRGD_CLKEN [24]
SMB_DATA D S SB_SMB_DATA U4 SATA PORT0 Remove = Pull High. DEFAULT PM_CLKRUN# R240 8.2K USBP10
SB_SMB_DATA [8,11,17]
3

s
@7SZ00P5X R141 43K EC_EXTSMI# R144 @10K_1 N/A
Q19 FET-2N7002E M-SC70-5 R162 43K Presence = Pull Low. EC_EXTSCI# R564 10K_1 USBN10
SATA PORT1 Remove = Pull High. DEFAULT PM_SYSRST# R153 10K_1 USBP11
U26C SUS_CLK R233 @10K_1 N/A

e
SMB_CLK G16 AH23 SATA_DET#0 R138 @0R Presence = Pull Low. DEFAULT ICH_GPIO18 R661 @10K_1 USBN11
SMB_DATA SMBCLK SATA0GP/GPIO21
A13 SMBDATA SATA1GP/GPIO19 AF19 SATA_DET#1 R168 @0R SATA PORT4 Remove = Pull High. ICH_GPIO22 R150 10K_1
+3.3VS R184 10K_1 ICH_GPIO60 E17 AE21 SATA_DET#4 R149 10K_1 PM_SYNC# R349 @10K_1
SATA
GPIO
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36
SMB

SMB_CLK_ME C17 AD20 SATA_DET#5 R159 @0R Presence = Pull Low. SATA_DET#4 R142 @43K
SMLINK0 SATA5GP/GPIO37

d
SMB_DATA_ME B18 SATA PORT5 Remove = Pull High. DEFAULT SATA_DET#5 R164 43K
SMLINK1
CLK14 H1 CLK_REF_ICH CLK_REF_ICH [13]
PM_RI# F19 AF3 CLK_USB48
Clocks

i
RI# CLK48 CLK_USB48 [13]
LPCPD# R667 0R LPCPD#_R R4 P1 SUS_CLK
[24] LPCPD# SUS_STAT#/LPCPD# SUSCLK
PM_SYSRST# G19 +3.3VS
B SYS_RESET# B
C16 SLP_S3#_R R610 0R PM_SLP_S3#

v
SLP_S3# PM_SLP_S3# [24]
PM_SYNC# M6 E16 SLP_S4#_R R189 0R PM_SLP_S4# C122 @100nF/10V_X7R
[7] PM_SYNC# PMSYNC#/GPIO0 SLP_S4# PM_SLP_S4# [24]
SLP_S5# G17 SLP_S5#_R R179 0R PM_SLP_S5#
TP13
R115 @10K_1 +3.3V

5
+3.3V R197 @10K_1 +3.3VS R177 10K_1 SMB_ALERT# A17 SMBALERT#/GPIO11
S4_STATE#/GPIO26 C10 SLP_S4_STATE# R634 @0R PM_SLP_S4# 1 +1.5V_PWRGD
+1.5V_PWRGD [30]

o
PM_STPPCI# R616 0R PM_STPPCI_ICH# A14 ALL_SYS_PWRGD 4
[13] PM_STPPCI# STP_PCI#
PM_STPCPU# R165 0R PM_STPCPU_ICH# E19 G20 PM_ICH_PWROK +1.05V_PWRGD
SYS GPIO

[13] PM_STPCPU# STP_CPU# PWROK 2 +1.05V_PWRGD [30]


R161 @10K_1 +3.3V
C126 100nF/10V_X7R M2 PM_DPRSLPVR_R R662 0R PM_DPRSLPVR U3

r
PM_DPRSLPVR [7,27]

3
PM_CLKRUN# DPRSLPVR/GPIO16 @74AHC1G08 R117 @10K_1
L4 CLKRUN# +3.3V
R133 10K_1 PCIE_WAKE# E20 B13 PM_BATLOW# M-SC70-5
Power MGT

+3.3V WAKE# BATLOW#


INT_SERIRQ M5 NC7SZ08P5X
[23,24] INT_SERIRQ SERIRQ
PM_THRM# AJ23 R3 PM_PWRBTN#
D

[5,8] PM_THRM# THRM# PWRBTN# PM_PWRBTN# [24]


VCORE_CLK_EN#

P
VR_PWRGD_CLKEN D21 D20 PM_LAN_RST# R167 0R PM_LAN_ENABLE
VRMPWRGD LAN_RST# PM_LAN_ENABLE [20,24]
G
Q15 R125 ICH_TP11 A20 D22 PM_RSMRST#_R R124 0R PM_RSMRST# +3.3VS
TP11 PM_RSMRST# [24]
S

FET-2N7002E TP11 RSMRST#


EC_EXTSCI# AG19 R5 CLK_PWRGD R123 10K_1 R511 C121 @100nF/10V_X7R R116 @10K_1
[24] EC_EXTSCI# GPIO1 CK_PWRGD CLK_PWRGD [13]
100K_1 EC_EXTSMI# AH21 0R
[24] EC_EXTSMI# GPIO6

5
AG21 R6 MPWROK
VCORE_CLK_EN# [27] GPIO7 CLPWROK MPWROK [7,24]
A21 1 ALL_SYS_PWRGD
GPIO8 ALL_SYS_PWRGD [24]
LANPHY_EN C12 B16 PM_SLP_M# PM_ICH_PWROK 4
[20] LANPHY_EN GPIO12 SLP_M# PM_SLP_M# [24]
ICH_TM_OFF# R169 0R ICH_GPIO13 C21 2 DELAY_VR_PWRGOOD
[17] ICH_TM_OFF# GPIO13 DELAY_VR_PWRGOOD [7,27]
AE18 GPIO17 CL_CLK0 F24 CL_CLK0 CL_CLK0 [7]
ICH_FP_EN R660 @0R ICH_GPIO18 K1 B19 CL_CLK1 AMT_CLK U2
[23] ICH_FP_EN AMT_CLK [17]

3
GPIO18 CL_CLK1 R178 0R R114 @10K_1 @74AHC1G08 R113 @2K_1
AF8 GPIO20 +3.3V
SATA_DET#1 R172 @0R ICH_GPIO22 AJ22 F22 CL_DATA0 M-SC70-5
SCLOCK/GPIO22 CL_DATA0 CL_DATA0 [7]
A9 C19 CL_DATA1 AMT_DAT
AMT_DAT [17]
NC7SZ08P5X
GPIO
Controller Link

ODD_PWR_EN R217 0R ICH_GPIO28 GPIO27 CL_DATA1 R173 0R


[17] ODD_PWR_EN D19 GPIO28
CLK_SATA_OE# L1 C25 CL_VREF0_ICH_R
A [13] CLK_SATA_OE# SATACLKREQ#/GPIO35 CL_VREF0 A
AE19 SLOAD/GPIO38 CL_VREF1 A19 CL_VREF1_ICH_R ALL_SYS_PWRGD R119 0R DELAY_VR_PWRGOOD
AG22 SDATAOUT0/GPIO39
AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST#0 CL_RST#0 [7]
+3.3VS R639 @10K_1 AH24 D18 CL_RST#1 AMT_RST#
GPIO49 CL_RST1# AMT_RST# [17]
R638 100K_1 ICH_GPIO57 A8 R183 0R
GPIO57/CLGPIO5
HDA_SPKR M7
MEM_LED/GPIO24 A16
C18 SUS_PWR_ACK
C504 100nF/10V_X7R
ECS COMPUTER CORP.
[22] HDA_SPKR SPKR GPIO10/SUS_PWR_ACK SUS_PWR_ACK [24]
MCH_ICH_SYNC# MCH_ICH_SYNC_R# AJ24 C11 AC_PRESENT R545 453R_1
[7] MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT AC_PRESENT [24] Title
ICH_TP3 B21 R544 3.24K_1 +3.3V
[14] ICH_TP3 TP3
R139 TP_ICH_PWM0 AH20 R588 3.24K_1 SB ICH9M 2 of 3
MISC

TP10 TP8 +3.3VS


0R TP_ICH_PWM1 AJ20 C20 LAN_WOL_EN R586 100K_1 +3.3VS R592 453R_1
TP9 TP9 WOL_EN/GPIO9 Size Document Number Rev
TP_ICH_PWM2 AJ21 R590 @100K_1
TP8 TP10 A
ICH9M REV 1.0
C542 100nF/10V_X7R 3931
Custom F30II0
PBGA676_ICH9 Date: Monday, November 05, 2007 Sheet 15 of 36
5 4 3 2 1
5 4 3 2 1

U26E
AA26 VSS[1] VSS[107] H5
AA27 VSS[2] VSS[108] J23
D17 BAT54 +3.3V_RTC AA3 J26
U26F VSS[3] VSS[109]
+3.3V A C 80 mil / 1.8A AA6 VSS[4] VSS[110] J27
8 mil / 0.1A A23 VCCRTC VCC1_05[1] A15 +1.05V AB1 VSS[5] VSS[111] AC22
+5V R647 10R_1 B15 AA23 K28
VCC1_05[2] VSS[6] VSS[112]
A6 V5REF VCC1_05[3] C15 AB28 VSS[7] VSS[113] K29

e
100nF/10V_X7R C584 C532 C530 D15 C160 C186 AB29 L13
100nF/10V_X7R 100nF/10V_X7R VCC1_05[4] 100nF/10V_X7R 100nF/10V_X7R VSS[8] VSS[114]
AE1 V5REF_SUS VCC1_05[5] E15 AB4 VSS[9] VSS[115] L15
VCC1_05[6] F15 AB5 VSS[10] VSS[116] L2
AA24 L11 AC17 L26

c
D5 BAT54 VCC1_5_B[1] VCC1_05[7] VSS[11] VSS[117]
AA25 VCC1_5_B[2] VCC1_05[8] L12 AC26 VSS[12] VSS[118] L27
+3.3VS A C +V5S_ICH_VCC5REF AB24 L14 10 mil / 0.2A L15 AC27 L5
VCC1_5_B[3] VCC1_05[9] Z1601 VSS[13] VSS[119]
D 8 mil / 0.1A AB25 VCC1_5_B[4] VCC1_05[10] L16 +1.5V AC3 VSS[14] VSS[120] L7 D
+5VS R250 10R_1 +V5A_ICH_VCC5REF_SUS AC24 L17 HCB1608KF-600T30_0603 AD1 M12
VCC1_5_B[5] VCC1_05[11] VSS[15] VSS[121]

n
AC25 VCC1_5_B[6] VCC1_05[12] L18 AD10 VSS[16] VSS[122] M13
100nF/10V_X7R C215 AD24 M11 C127 C123 AD12 M14
VCC1_5_B[7] VCC1_05[13] 10nF/25V_X7R 10uF/6.3V_0805_X5R VSS[17] VSS[123]
AD25 VCC1_5_B[8] VCC1_05[14] M18 AD13 VSS[18] VSS[124] M15
AE25 VCC1_5_B[9] VCC1_05[15] P11 AD14 VSS[19] VSS[125] M16

e
L58 50 mil / 1A AE26 P18 AD17 M17
+V1.5S_PCIE_ICH VCC1_5_B[10] VCC1_05[16] VSS[20] VSS[126]
+1.5V AE27 VCC1_5_B[11] VCC1_05[17] T11 AD18 VSS[21] VSS[127] M23
HCB1608KF-600T30_0603 AE28 T18 10 mil / 0.2A L17 AD21 M28
VCC1_5_B[12] VCC1_05[18] Z1602 VSS[22] VSS[128]
AE29 U11 AD28 M29

r
VCC1_5_B[13] VCC1_05[19] +1.05V VSS[23] VSS[129]
C138 C152 C135 HCB1608KF-600T30_0603

CORE
F25 VCC1_5_B[14] VCC1_05[20] U18 AD29 VSS[24] VSS[130] N11
10uF/6.3V_0805_X5R 10uF/6.3V_0805_X5R 2.2uF/10V_0603_X5R G25 V11 AD4 N12
VCC1_5_B[15] VCC1_05[21] C151 VSS[25] VSS[131]
H24 VCC1_5_B[16] VCC1_05[22] V12 AD5 VSS[26] VSS[132] N13

e
H25 V14 4.7uF/10V_0805_X5R AD6 N14
VCC1_5_B[17] VCC1_05[23] VSS[27] VSS[133]
J24 VCC1_5_B[18] VCC1_05[24] V16 AD7 VSS[28] VSS[134] N15
J25 VCC1_5_B[19] VCC1_05[25] V17 AD9 VSS[29] VSS[135] N16

f
K24 VCC1_5_B[20] VCC1_05[26] V18 AE12 VSS[30] VSS[136] N17
+ K25 VCC1_5_B[21] 10 mil / 0.2A AE13 VSS[31] VSS[137] N18
C124 L23 R29 +1.05V AE14 N26
@100uF/6.3V_3528_NEC VCC1_5_B[22] VCCDMIPLL VSS[32] VSS[138]
L24 AE16 N27

e
VCC1_5_B[23] VSS[33] VSS[139]
L25 VCC1_5_B[24] VCC_DMI[1] W23 AE17 VSS[34] VSS[140] P12
M24 Y23 C150 C149 C180 AE2 P13
VCC1_5_B[25] VCC_DMI[2] 100nF/10V_X7R 100nF/10V_X7R 4.7uF/10V_0805_X5R VSS[35] VSS[141]
M25 VCC1_5_B[26] AE20 VSS[36] VSS[142] P14

r
N23 VCC1_5_B[27] V_CPU_IO[1] AB23 AE24 VSS[37] VSS[143] P15
N24 VCC1_5_B[28] V_CPU_IO[2] AC23 AE3 VSS[38] VSS[144] P16
N25 VCC1_5_B[29] AE4 VSS[39] VSS[145] P17
P24 VCC1_5_B[30] AE6 VSS[40] VSS[146] P2
P25 +3.3V AE9 P23

le
VCC1_5_B[31] VSS[41] VSS[147]

VCCA3GP
R24 VCC1_5_B[32] 20 mil / 0.4A AF13 VSS[42] VSS[148] P28
R25 AG29 C195 100nF/10V_X7R AF16 P29
VCC1_5_B[33] VCC3_3[1] VSS[43] VSS[149]
R26 VCC1_5_B[34] AF18 VSS[44] VSS[150] P4
C R27 AJ6 C161 100nF/10V_X7R AF22 P7 C
VCC1_5_B[35] VCC3_3[2] VSS[45] VSS[151]
T24 VCC1_5_B[36] AH26 VSS[46] VSS[152] R11
T27 AC10 C194 100nF/10V_X7R AF26 R12
L66 VCC1_5_B[37] VCC3_3[7] VSS[47] VSS[153]

t
8 mil / 0.1A T28 VCC1_5_B[38] AF27 VSS[48] VSS[154] R13
+1.5V +V1.5S_APLL_ICH T29 AD19 C210 100nF/10V_X7R AF5 R14
FCM1608KF-221T05_0603 VCC1_5_B[39] VCC3_3[3] VSS[49] VSS[155]
U24 AF20 AF7 R15

VCCP_CORE
VCC1_5_B[40] VCC3_3[4] C191 100nF/10V_X7R VSS[50] VSS[156]
U25 VCC1_5_B[41] VCC3_3[5] AG24 AF9 VSS[51] VSS[157] R16
C523 C531 V24 AC20 AG13 R17
VCC1_5_B[42] VCC3_3[6] VSS[52] VSS[158]

n
10uF/6.3V_0805_X5R 1uF/6.3V_X5R V25 AG16 R18
VCC1_5_B[43] VSS[53] VSS[159]
U23 VCC1_5_B[44] AG18 VSS[54] VSS[160] R28
W24 B9 C181 100nF/10V_X7R AG20 T12
VCC1_5_B[45] VCC3_3[8] VSS[55] VSS[161]

I
W25 VCC1_5_B[46] VCC3_3[9] F9 AG23 VSS[56] VSS[162] T13
K23 VCC1_5_B[47] VCC3_3[10] G3 AG3 VSS[57] VSS[163] T14
Y24 G6 C182 @100nF/10V_X7R AG6 T15

PCI
VCC1_5_B[48] VCC3_3[11] VSS[58] VSS[164]
Y25 VCC1_5_B[49] VCC3_3[12] J2 AG9 VSS[59] VSS[165] T16
VCC3_3[13] J7 AH12 VSS[60] VSS[166] T17
AJ19 K7 C128 @100nF/10V_X7R AH14 T23
VCCSATAPLL VCC3_3[14] VSS[61] VSS[167]

s
70 mil / 1.5A 10 mil / 0.2A AH17 VSS[62] VSS[168] B26
+1.5V AC16 VCC1_5_A[1] VCCHDA AJ4 +3.3V AH19 VSS[63] VSS[169] U12
AD15 VCC1_5_A[2] AH2 VSS[64] VSS[170] U13
AD16 C185 100nF/10V_X7R AH22 U14

e
VCC1_5_A[3] VSS[65] VSS[171]
C177 AE15 VCC1_5_A[4] ARX 10 mil / 0.2A AH25 VSS[66] VSS[172] U15
1uF/6.3V_X5R AF15 AJ3 VCCSUSHDA3_3A R230 0R +3.3VS AH28 U16
VCC1_5_A[5] VCCSUSHDA VSS[67] VSS[173]
AG15 VCC1_5_A[6] AH5 VSS[68] VSS[174] U17
AH15 C213 100nF/10V_X7R AH8 AD23
VCC1_5_A[7] VSS[69] VSS[175]

d
AJ15 VCC1_5_A[8] AJ12 VSS[70] VSS[176] U26
AJ14 VSS[71] VSS[177] U27
AC11 AC8 VCCSUS1_05_ICH C170 @100nF/10V_X7R AJ17 U3

i
VCC1_5_A[9] VCCSUS1_05[1] VSS[72] VSS[178]
AD11 VCC1_5_A[10] VCCSUS1_05[2] F17 AJ8 VSS[73] VSS[179] V1
AE11 VCC1_5_A[11] B11 VSS[74] VSS[180] V13
ATX

C172 AF11 AD8 VCCSUS1_5_ICH C188 @100nF/10V_X7R B14 V15


B 1uF/6.3V_X5R VCC1_5_A[12] VCCSUS1_5[1] VSS[75] VSS[181] B
AG10 B17 V23

v
VCC1_5_A[13] VCCSUS1_5_INT_ICH C165 100nF/10V_X7R VSS[76] VSS[182]
AG11 VCC1_5_A[14] VCCSUS1_5[2] F18 B2 VSS[77] VSS[183] V28
AH10 VCC1_5_A[15] B20 VSS[78] VSS[184] V29
AJ10 VCC1_5_A[16] 20 mil / 0.4A B23 VSS[79] VSS[185] V4
VCCSUS3_3[1] A18 +3.3VS B5 VSS[80] VSS[186] V5

o
VCCPSUS

AC9 VCC1_5_A[17] VCCSUS3_3[2] D16 B8 VSS[81] VSS[187] W26


AC18 D17 C196 100nF/10V_X7R C26 W27
VCC1_5_A[18] VCCSUS3_3[3] VSS[82] VSS[188]
AC19 VCC1_5_A[19] VCCSUS3_3[4] E22 C27 VSS[83] VSS[189] W3
C192 AC21 E11 Y1

r
1uF/6.3V_X5R VCC1_5_A[20] VSS[84] VSS[190]
G10 VCC1_5_A[21] E14 VSS[85] VSS[191] Y28
G9 VCC1_5_A[22] VCCSUS3_3[5] AF1 E18 VSS[86] VSS[192] Y29
C201 AC12 E2 Y4
100nF/10V_X7R VCC1_5_A[23] C211 100nF/10V_X7R VSS[87] VSS[193]
AC13 VCC1_5_A[24] VCCSUS3_3[6] T1 E21 VSS[88] VSS[194] Y5
AC14 T2 E24 AG28

P
VCC1_5_A[25] VCCSUS3_3[7] VSS[89] VSS[195]
VCCSUS3_3[8] T3 E5 VSS[90] VSS[196] AH6
AJ5 T4 C193 22nF/16V_X7R E8 AF2
L19 VCCUSBPLL VCCSUS3_3[9] VSS[91] VSS[197]
20 mil / 0.5A VCCSUS3_3[10] T5 F16 VSS[92] VSS[198] B25
+V1.5S_USB AA7 T6 F28
VCC1_5_A[26] VCCSUS3_3[11] VSS[93]
USB CORE

FCM1608KF-221T05_0603 AB6 U6 C214 22nF/16V_X7R F29 A1


VCC1_5_A[27] VCCSUS3_3[12] VSS[94] VSS_NCTF[1]
AB7 VCC1_5_A[28] VCCSUS3_3[13] U7 G12 VSS[95] VSS_NCTF[2] A2
C200 AC6 V6 G14 A28
100nF/10V_X7R VCC1_5_A[29] VCCSUS3_3[14] VSS[96] VSS_NCTF[3]
AC7 VCC1_5_A[30] VCCSUS3_3[15] V7 G18 VSS[97] VSS_NCTF[4] A29
VCCSUS3_3[16] W6 G21 VSS[98] VSS_NCTF[5] AH1
VCCPUSB

A10 VCCLAN1_05[1] VCCSUS3_3[17] W7 G24 VSS[99] VSS_NCTF[6] AH29


VCCLAN1_05_INT_ICH A11 Y6 G26 AJ1
C564 100nF/10V_X7R VCCLAN1_05[2] VCCSUS3_3[18] VSS[100] VSS_NCTF[7]
VCCSUS3_3[19] Y7 G27 VSS[101] VSS_NCTF[8] AJ2
10 mil / 0.2A VCCSUS3_3[20] T7 G8 VSS[102] VSS_NCTF[9] AJ28
C212 100nF/10V_X7R A12 H2 AJ29
VCCLAN3_3[1] VSS[103] VSS_NCTF[10]
B12 VCCLAN3_3[2] H23 VSS[104] VSS_NCTF[11] B1
+3.3V VCCCL1_05 G22 VCCCL1_05_INT_ICH H28 VSS[105] VSS_NCTF[12] B29
A
L57 10 mil / 0.2A H29 A
+V1.5S_ICH_GLANPLL_R VSS[106]
+1.5V A27 VCCGLANPLL VCCCL1_5 G23 VCCCL1_5_INT_ICH
FCM1608KF-221T05_0603 ICH9M REV 1.0
10 mil / 0.2A PBGA676_ICH9
GLAN POWER

C495 C501 +V1.5S_PCIE_ICH D28 C155 C148 C156


10uF/6.3V_0805_X5R 2.2uF/10V_0603_X5R VCCGLAN1_5[1] @1uF/6.3V_X5R @100nF/10V_X7R 100nF/10V_X7R
D29 VCCGLAN1_5[2]
4.7uF/10V_0805_X5R C131
E26
E27
VCCGLAN1_5[3] ECS COMPUTER CORP.
VCCGLAN1_5[4]
10 mil / 0.2A
A24 Title
VCCCL3_3[1] +3.3V
+3.3V A26 VCCGLAN3_3 VCCCL3_3[2] B24
C198 @100nF/10V_X7R
SB ICH9M 3 of 3
ICH9M REV 1.0 Size Document Number Rev
A
PBGA676_ICH9 3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 16 of 36
5 4 3 2 1
5 4 3 2 1

MINI CARD_WLAN SATA HDD +5V


L29
+5V_HDD

CN20 HCB2012KF-300T30_0805
+3.3VS LAYOUT: Place caps close to MINI +3.3VS_MINI1 LAYOUT: Place caps close to MINI CARD_CON +1.5V P1

NC1
NC2
V33_1
CARD_CON along +3.3VS power shape. along +3.3VS_Mini1 and +1.5V power shape. V33_2 P2
S1 GND V33_3 P3

e
SATA_TXP0 S2 P4 LAYOUT: HDD Power
[14] SATA_TXP0 TA+ GND
C450 C438 C447 C455 C448 C494 C492 C427 C435 C479 C461 P5
10uF/6.3V_0805_X5R 4.7uF/10V_0805_X5R 100nF/10V_X7R 100nF/10V_X7R 100nF/10V_X7R 10uF/6.3V_0805_X5R 100nF/10V_X7R 100nF/10V_X7R 4.7uF/10V_0805_X5R 100nF/10V_X7R 100nF/10V_X7R SATA_TXN0 GND
S3 P6 +5V_HDD: 80 mil / 2.0A

c
[14] SATA_TXN0 TA- GND
P7 +5V_HDD
V5_1
S4 GND V5_2 P8
D
V5_3 P9 + D
SATA_RXN0 C255 10nF/25V_X7R SATA_RXN0_R S5 P10 C231 C227 C229
[14] SATA_RXN0 RB- GND Z1702 100nF/10V_X7R 10uF/6.3V_0805_X5R 330uF/6.3V_6*7_SACAP

n
RSV P11
L50 SATA_RXP0 C242 10nF/25V_X7R SATA_RXP0_R S6 P12
[14] SATA_RXP0 RB+ GND
HCB1608KF-600T30_0603
+3.3VS +3.3VS_MINI1 S7 GND V12_1 P13

GND1
GND2
+3.3VS P14
CN27 V12_2 R260
V12_3 P15
PCIe Mini Card v1.1 approved ECN LAYOUT: MINI CARD Power @0R
51 52 CON-C16645-ALL

r
AMT_RST# Reserved +3.3Vaux c16617-x22xx-x
[15] AMT_RST# 49 Reserved/C-Link_RST GND 50 +3.3VS: 70 mil / 1.65A
AMT_DAT 47 48 +1.5V: 20 mil / 0.5A
[15] AMT_DAT Reserved/C-Link_DAT +1.5V
AMT_CLK 45 46 +3.3V_Mini1: 45 mil / 1.1A
[15] AMT_CLK Reserved/C-Link_CLK LED_WPAN#

e
43 GND LED_WLAN# 44
41 42 +5V
+3.3Vaux LED_WWAN#
39 +3.3Vaux GND 40 LAYOUT: HDD Power

f
37 38 MINI1_USB_PP R451 0R USB_PP4 +5V_HDD: 80 mil / 2.0A
35
GND USB_D+
36 MINI1_USB_PN R453 0R USB_PN4
USB_PP4 [15]
USB_PN4 [15] SATA ODD_BB

S
PCIE_TXP1_MINI1 GND USB_D- ODD_PWR_EN#
[15] PCIE_TXP1_MINI1 33 PETp0 GND 34 G
PCIE_TXN1_MINI1 31 32 MINI1_SMB_DATA R457 @0R SB_SMB_DATA

D
[15] PCIE_TXN1_MINI1 PETn0 SMB_DATA SB_SMB_DATA [8,11,15]
29 30 MINI1_SMB_CLK R461 @0R SB_SMB_CLK Q22
GND SMB_CLK SB_SMB_CLK [8,11,15]
27 28 @FET-AO3413

D
PCIE_RXP1_MINI1 GND +1.5V ODD_PWR_EN
25 26 G

G
[15] PCIE_RXP1_MINI1 PERp0 GND [15] ODD_PWR_EN

r
PCIE_RXN1_MINI1 23 24 Q20 R224 Q21
[15] PCIE_RXN1_MINI1

S
PERn0 +3.3Vaux BUF_PLT_RST# R223 @220K @FET-2N7002E @56K @FET-AO3413
21 GND PERST# 22 BUF_PLT_RST# [7,14,21,23,24]
19 20 RF_ON S D
UIM_C4/Reserved W_DISABLE#
17 UIM_C8/Reserved GND 18
R472 22K CN32 +5V L80
+3.3VS

le
R480 @0R HCB2012KF-300T30_0805

NC18
NC17
NC16
NC15
NC14
NC13
Mechanical Key
2 1 +5V_ODD

D
GND1 GNDA1
15 GND UIM_VPP 16
C CLK_PCIE_MINI1 13 14 SATA_TXP1 4 3 +5V_ODD C
[13] CLK_PCIE_MINI1 REFCLK+ UIM_RESET [14] SATA_TXP1 A+ VCC1
CLK_PCIE_MINI1# 11 12 G RF_OFF#
[13] CLK_PCIE_MINI1# REFCLK- UIM_CLK RF_OFF# [24]
9 10 SATA_TXN1 6 5 +
[14] SATA_TXN1

S
CLK_MINI1_OE# GND UIM_DATA Q60 A- VCC2 C520 C541 C583

t
[13] CLK_MINI1_OE# 7 CLKREQ# UIM_PWR 8 RF_OFF# = Low, Enable WLAN.
5 6 FET-2N7002E 8 7 100nF/10V_X7R 10uF/6.3V_0805_X5R 100uF/6.3V_3528_NEC
COEX2/BT_CHCLK +1.5V +1.5V RF_OFF# = High, Disable WLAN. GND2 VCC3
3 COEX1/BT_DATA GND 4
MINICD1_WAKE# 1 2 +3.3VS_MINI1 SATA_RXN1 C143 10nF/25V_X7R SATA_RXN1_R 10 9
[15] MINICD1_WAKE# WAKE# +3.3Vaux [14] SATA_RXN1 B- GNDA2
GND1 GND1 GND2 GND2

n
SATA_RXP1 C144 10nF/25V_X7R SATA_RXP1_R 12 11
[14] SATA_RXP1 B+ GNDA3
CON-PCI-1775838-1-TYC
AS0B22X-S80X-XXA 14 13 ODD_MD R556 @10K_1 +3.3V
GND3 MD

I
+3.3V R540 @10K_1 ODD_DP 16 15 R541 @220K
DP GNDA4

NC12
NC11
NC10
NC8
NC7
NC6
NC5

NC9
NC4
NC3
NC2
NC1
s
CON-XP90-03X37 XP90-03X37-16T1BA
MINI CARD_Turbo Memory

e
+3.3VS LAYOUT: Place caps close to MINI +3.3VS_MINI2 LAYOUT: Place caps close to MINI CARD_CON +1.5V CPU FAN CN21
CARD_CON along +3.3VS power shape. along +3.3VS_Mini1 and +1.5V power shape. 30 mil / 0.75A 30 mil / 0.75A

d
+5V E C +5V_FAN 3 NC1
3 NC1
2 2
Q38 1 NC2

i
+5V + 1 NC2
C235 C236 C234 C24 C233 C22 C23 C7 C232 C222 C225 TR-2SA1797Q-MPT3 C274 C257

B
10uF/6.3V_0805_X5R 4.7uF/10V_0805_X5R 100nF/10V_X7R 100nF/10V_X7R 100nF/10V_X7R 10uF/6.3V_0805_X5R 100nF/10V_X7R 100nF/10V_X7R 4.7uF/10V_0805_X5R 100nF/10V_X7R 100nF/10V_X7R SOT89_BCE 33uF/6.3V_3528_OxiCAP 1uF/10V_0603_X5R CON-WTB-3801-F03N-05R-E&T
R302 1K_1 85205-03L
B Z1704 B

v
R304 +3.3V
C295 22R FAN_SPEED
L3 R303 100nF/10V_X7R

o
HCB1608KF-600T30_0603 100R_1 Z1707 R313
5.11K_1 +5V
+3.3VS +3.3VS_MINI2

8
+3.3VS R280
CN4 3 Z1708 10K_1

r
+
PCIe Mini Card v1.1 approved ECN LAYOUT: MINI CARD Power Z1705 1
51 52 2 FAN_SPEED#
Reserved +3.3Vaux - FAN_SPEED# [24]
49 50 +3.3VS: 70 mil / 1.65A U9A R279

D
Reserved/C-Link_RST GND LM358DR R316 4.7K
47 48 +1.5V: 20 mil / 0.5A

4
Reserved/C-Link_DAT +1.5V C325 M-SO8 10K_1
45 46 +3.3V_Mini2: 45 mil / 1.1A

P
Reserved/C-Link_CLK LED_WPAN# 100nF/10V_X7R
43 GND LED_WLAN# 44 G
41 42 Q36

S
+3.3Vaux LED_WWAN# FET-2N7002E
39 +3.3Vaux GND 40
37 38 MINI2_USB_PP R20 0R USB_PP5 C258
GND USB_D+ USB_PP5 [15]
35 36 MINI2_USB_PN R19 0R USB_PN5 Z1706 R322 100K_1 FAN_CTRL0 100nF/10V_X7R
GND USB_D- USB_PN5 [15] FAN_CTRL0 [24]
PCIE_TXP2_MINI2 33 34
[15] PCIE_TXP2_MINI2 PETp0 GND
PCIE_TXN2_MINI2 31 32 MINI2_SMB_DATA R18 @0R SB_SMB_DATA R323 100K_1 0~3.3V
[15] PCIE_TXN2_MINI2 PETn0 SMB_DATA
29 30 MINI2_SMB_CLK R17 @0R SB_SMB_CLK
GND SMB_CLK
27 GND +1.5V 28
PCIE_RXP2_MINI2 25 26
[15] PCIE_RXP2_MINI2 PERp0 GND
PCIE_RXN2_MINI2 23 24
[15] PCIE_RXN2_MINI2 PERn0 +3.3Vaux
21 22 BUF_PLT_RST# EC_CPUISENSE
GND PERST# BUF_PLT_RST# [7,14,21,23,24] [24] EC_CPUISENSE
19 20 TM_ON R295 12K_1 Z1709
UIM_C4/Reserved W_DISABLE#
17 UIM_C8/Reserved GND 18
R15 22K +3.3VS
Mechanical Key R16 @0R R294

8
@0R
D

A A
15 16 5 POUT
GND UIM_VPP + POUT [27]
CLK_PCIE_MINI2 13 14 CPUISENSE 7
[13] CLK_PCIE_MINI2 REFCLK+ UIM_RESET
CLK_PCIE_MINI2# 11 12 G ICH_TM_OFF# 6
[13] CLK_PCIE_MINI2# REFCLK- UIM_CLK ICH_TM_OFF# [15] -
9 10 U9B
S

CLK_MINI2_OE# GND UIM_DATA Q3 LM358DR


[13] CLK_MINI2_OE# 7 8 TM_OFF# = Low, Enable Turbo Memory.

4
CLKREQ# UIM_PWR
5
3
COEX2/BT_CHCLK +1.5V 6
4
+1.5V FET-2N7002E
TM_OFF# = High, Disable Turbo Memory. C291
100nF/10V_X7R
M-SO8
R296
ECS COMPUTER CORP.
MINICD2_WAKE# COEX1/BT_DATA GND 1K_1
[15] MINICD2_WAKE# 1 WAKE# +3.3Vaux 2 +3.3VS_MINI2
GND1 GND2 Title
GND1 GND2
CON-PCI-1775838-1-TYC
FAN/MINI CARD/ODD_BB/HDD CON
AS0B22X-S80X-XXA Size Document Number Rev
A
3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 17 of 36
5 4 3 2 1
5 4 3 2 1

L33
+5V_DVI +5V_DVI +5V
HCB1608KF-600T30_0603

C297 100nF/10V_X7R C300


100nF/10V_X7R

e
100nF/10V_X7R C34 DVI

c
100nF/10V_X7R C33 +3.3V

14

15
D D
1 CN7
CRT_VSYNC

n
4

GND (+5V.H.S)
+5V POWER
[8] CRT_VSYNC
2 DVI_B_DATA2# 1 GND1 DVI_GND_L
[12] DVI_B_DATA2# TMDS DATA 2- GND1
U10 DVI_B_DATA2 2 NC1
[12] DVI_B_DATA2 TMDS DATA 2+ NC1
74AHC1G08 +5V_DVI R292 2.2K DVI_DDC_CLK

3 e
M-SC70-5 R297 2.2K DVI_DDC_DATA 3
R26 @0R TMDS 2/4 Shield
4 L8
TMDS DATA 4-
5

r
100nF/10V_X7R C31 Layout: TMDS DATA 4+ HCB1608KF-600T30_0603
100pF/50V_NP0 C312 Resistor / Caps / Bead close to DVI_CON. C313 100pF/50V_NP0 DVI_DDC_CLK 6
[12] DVI_DDC_CLK DDC Clk
100nF/10V_X7R C30 +3.3V DVI_DDC_DATA 7
[12] DVI_DDC_DATA DDC Data

e
100pF/50V_NP0 C331 C330 100pF/50V_NP0

5
DVI_VSYNC 8 V SYNC
1

f
CRT_HSYNC 4 DVI_B_DATA1# 9
[8] CRT_HSYNC [12] DVI_B_DATA1# TMDS DATA 1-
2 DVI_B_DATA1 10
[12] DVI_B_DATA1 TMDS DATA 1+
U11
74AHC1G08 CRT_VSYNC_R R25 33R DVI_VSYNC 11

e
3
M-SC70-5 TMDS DATA 1/3 Shield
R325 @0R CRT_HSYNC_R R42 33R DVI_HSYNC 12 TMDS DATA 3-
13 TMDS DATA 3+

r
CRT_RED L6 FCB1608K-300T07_0603 DVI_RED
[8] CRT_RED
DVI_HDP# 16
[12] DVI_HDP# HOT PLUG DETECT
CRT_GREEN L7 FCB1608K-300T07_0603 DVI_GREEN
[8] CRT_GREEN
DVI_B_DATA0# 17
[12] DVI_B_DATA0# TMDS DATA 0-
CRT_BLUE L5 FCB1608K-300T07_0603 DVI_BLUE DVI_B_DATA0 18

le
[8] CRT_BLUE [12] DVI_B_DATA0 TMDS DATA 0+
19 TMDS DATA 0/5 Shield
C R30 R41 R33 C318 C326 C320 C319 C327 C321 20 C
150R_1 150R_1 150R_1 @10pF/50V_NP0 @10pF/50V_NP0 @10pF/50V_NP0 15pF/50V_NP0 15pF/50V_NP0 15pF/50V_NP0 TMDS DATA 5-
21 TMDS DATA5+

t
22 TMDS CLK Shield
DVI_B_CLK 23
[12] DVI_B_CLK TMDS CLK +
DVI_B_CLK# 24
[12] DVI_B_CLK# TMDS Clk -

n
DVI_RED C1
DVI_GREEN RED
C2 GREEN
DVI_BLUE C3 BLUE

I
DVI_HSYNC C4 H SYNC
DP1 C5 NC2
A GND1 NC2 DVI_GND_R
4 3 C6 A GND2 GND2 GND2

s
+5V_DVI R329 @100K_1 Z1802 5 2 L4
CON DVI-I RA
6 1 C16203-329XX-Y HCB1608KF-600T30_0603

e
@SRV05-4
LCD_VCC TSOP6

d
Layout:
L1 Place ESD near DVI Con.
80 mil / 2A HCB1608KF-600T30_0603 80 mil / 2A
LCD_LVDS

i
+3.3V S D Z1803 +3.3V_LCD
L2
B R1 Q2 C2 C3 HCB1608KF-600T30_0603 B
80 mil / 2A

v
G

56K FET-AO3413 10uF/6.3V_0805_X5R 1uF/10V_0603_X5R +3.3V_LCD +3.3V_LCDEDID +3.3V


Z1804
CN15 C5 100nF/10V_X7R
100nF/10V_X7R C4
D

1 2

o
R3 LVDSA_DATA#1
3 4 LVDSA_DATA#1 [8]
300K_1 LVDSA_DATA#0 LVDSA_DATA1
[8] LVDSA_DATA#0 5 6 LVDSA_DATA1 [8]
LVDS_VDD_EN LCD_EN G LVDSA_DATA0
[8] LVDS_VDD_EN [8] LVDSA_DATA0 7 8
Q1 LVDSB_DATA#0

r
LVDSB_DATA#0 [8]
S

FET-2N7002E LVDSA_CLK# 9 10 LVDSB_DATA0


[8] LVDSA_CLK# 11 12 LVDSB_DATA0 [8]
C1 LVDSA_CLK
[8] LVDSA_CLK 13 14
R251 100nF/10V_X7R LVDSB_DATA#2
15 16 LVDSB_DATA#2 [8]
100K_1 LVDSA_DATA#2 LVDSB_DATA2
[8] LVDSA_DATA#2 17 18 LVDSB_DATA2 [8]
LVDSA_DATA2

P
[8] LVDSA_DATA2 19 20 LVDSB_DATA#1
21 22 LVDSB_DATA#1 [8]
LVDSB_CLK# LVDSB_DATA1
[8] LVDSB_CLK# 23 24 LVDSB_DATA1 [8]
LVDSB_CLK LCD_SEL2#
[8] LVDSB_CLK 25 26
LCD_SEL1# LCD_SEL0#
LVDS_DDC_CLK 27 28 LVDS_DDC_DATA
[8] LVDS_DDC_CLK 29 30 LVDS_DDC_DATA [8]
NC1 NC1 NC3 NC3
NC2 NC4
INVERTER NC2 NC4
CON-WTB-3760-F30C-51R-E&T
87216-30BB
LCD Panel SELECT
C216 100nF/25V_0603_X7R C221 100nF/25V_0603_X7R LCD_SEL2# LCD_SEL1# LCD_SEL0# +3.3V R7 @10K_1 LCD_SEL0#
100nF/10V_X7R C220 +3.3V R5 @10K_1 LCD_SEL1#
L25 L L L reserved R6 @10K_1 LCD_SEL2#
A
R8 100K_1 40 mil / 1A HCB2012KF-300T30_0805 CN18 A
5

VIN VIN_LCD L L H 1024X768 R4 2.2K LVDS_DDC_CLK


L_BKLT_EN 1 R2 2.2K LVDS_DDC_DATA
[8] L_BKLT_EN 1 2
4 BKL_ON HCB1608KF-600T30_0603 L24 Z1801 L H L 1400X1050
BKL_EC BRIGHTNESS HCB1608KF-600T30_0603 L23 Z1805 3
[24] BKL_EC 2 [24] BRIGHTNESS 4
5 NC1 L H H 1280X800
U7 Inverter Conn. Pin 4. ECS COMPUTER CORP.
3

74AHC1G08 6 NC2
PWM Level:3.3V max, Duty:100%~20% H L L reserved
M-SC70-5 CON-87212-06G0-ACE
C218 C219 87212-06L H L H 1680X1050 Title
100nF/10V_X7R 100nF/10V_X7R DVI/LCD CON
H H L 1920X1200 Size Document Number Rev
A
H H H 1440X900 3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 18 of 36
5 4 3 2 1
5 4 3 2 1

NEW CARD CN10


NEW CARD POWER USB_PN6 R413 0R NC_USBPN
1 GND NC1 NC1
[15] USB_PN6 2 USBD- NC2 NC2
USB_PP6 R417 0R NC_USBPP 3
[15] USB_PP6 USBD+

e
NC_CPPE# R424 0R NC_CPUSB# 4
[24] NC_CPPE# CPUSB#
5 RESERVED1
+3.3V +3.3V_NC +1.5V +1.5V_NC +3.3VS +3.3VS_NC 6 RESERVED2
7

c
SMBCLK
55 mil / 1.3A 55 mil / 1.3A 30 mil / 0.65A 30 mil / 0.65A 16 mil / 0.275A 16 mil / 0.275A 8 SMBDATA
S D S D S D +1.5V_NC 30 mil / 0.65A R455 @0R_0603 Z1905 9 +1.5V
D 10 +1.5V D
NC_WAKE_UP# 11
[15] NC_WAKE_UP# WAKE#
Q52 Q55 Q51 16 mil / 0.275A

n
+3.3VS_NC 12

G
FET-AO3413 FET-AO3413 FET-AO3413 NC_PERST# +3.3VS(+3.3VAUX)
[24] NC_PERST# 13 PERST#
Z1901 Z1903 +3.3V_NC 14 +3.3V
55 mil / 1.3A 15 +3.3V

e
R470 LAYOUT: NEW CARD Power R444 CLK_NC_OE# R483 0R NC_CLKREQ# 16
[13] CLK_NC_OE# CLKREQ#
56K R481 56.2R_1 Z1902 56K R445 56.2R_1 Z1904 NC_CPPE# 17
CLK_PCIE_NC# CPPE#
+3.3V: 30 mil / 0.65A 18

D
[13] CLK_PCIE_NC# REFCLK-
+3.3VS: 16 mil / 0.275A CLK_PCIE_NC 19

r
[13] CLK_PCIE_NC REFCLK+
+1.5V: 55 mil / 1.3A 20 GND
NC_PWRON G Q53 NC_PWRONS G Q49 PCIE_RXN3_NC 21
[24] NC_PWRON [24] NC_PWRONS [15] PCIE_RXN3_NC PERn0
FET-2N7002E FET-2N7002E PCIE_RXP3_NC 22
[15] PCIE_RXP3_NC

S
PERp0

e
23 GND GND1 GND1
R469 220K R400 220K PCIE_TXN3_NC 24 GND2
[15] PCIE_TXN3_NC PETn0 GND2
PCIE_TXP3_NC 25
[15] PCIE_TXP3_NC PETp0

f
26 GND

+3.3VS_NC +1.5V_NC +3.3V_NC CON-NEW-C-1759535-2-TYC

e
PT07-072-1

r
C453 C456 C462 C457 C470 C460 Layout:
4.7uF/10V_0805_X5R 100nF/10V_X7R 10uF/6.3V_0805_X5R 100nF/10V_X7R 4.7uF/10V_0805_X5R 100nF/10V_X7R
Caps close to NEW CARD_CON

EXT_USB +1.5V_NC / +3.3V_NC /

le
+3.3VS_NC power pin.
Q39
C FET-AO3413 C
60 mil / 1.5A L36
+5V_AUX S D Z1906 +5V_EXTUSB
HCB2012KF-300T30_0805

t
C324 60 mil / 1.5A
G

R333 56K Z1907 4.7uF/10V_0805_X5R

n
R336 100R_1 Z1912

Z1908 4 5 6 R345
@100K_1 C342 100nF/10V_X7R

I
DP2
D

@SRV05-4 C343 4.7uF/10V_0805_X5R


TSOP6
EC_USB2 G
[24] EC_USB2 3 2 1
Q41 CN23
S

s
R355 220K FET-2N7002E
1 NC1 NC1
2

e
USB_PP1 R357 0R EXT_USB_PP1 3
[15] USB_PP1 4
USB_PN1 R358 0R EXT_USB_PN1 Z1910 D S
[15] USB_PN1 5 Q63

G
USB_PP2 R362 0R EXT_USB_PP2 6 R583 @FET-AO3413 Q65
[15] USB_PP2 7

d
USB_PN2 R366 0R EXT_USB_PN2 NC2 @56K @FET-2N7002E
[15] USB_PN2

G
8 NC2
S D
BT_PW_EN R587 @220K

i
CON-WTB-85205-08001-ACE 20 mil / 0.5A L59
85205-08L +5V +5V_BT C496 100nF/10V_X7R
B HCB1608KF-600T30_0603 B

v
L60
4 R2I R2O 3

o
1 2 CN28
Web Camera R1I R1O
@WCM3216F2S-900T04
1 NC1 NC1

r
USB_PN8 R532 0R BT_USBN 2
[15] USB_PN8 3
USB_PP8 R537 0R BT_USBP
[15] USB_PP8 4
Z1909 D S
Q26 5
G

R266 @FET-AO3413 Q25 6

P
@56K @FET-2N7002E BT_EN R585 0R BT_PW_EN 7
[24] BT_EN NC2
G

8 NC2
S D
WEBCAM_EN R256 @220K
BT_EN = High, Enable BT.
20 mil / 0.5A L30 CON-WTB-87212-08G0-ACE
+5V_WC C226 100nF/10V_X7R
BT_EN = Low, Disable BT. 87212-08L
+5V
HCB1608KF-600T30_0603

L27
4
1
R2I R2O
R1I R1O
3
2
USB Dongle
USB_PP3
@WCM3216F2S-900T04

R259 0R WEBCAM_USBP
CN16 (Bluetooth)
[15] USB_PP3 1
USB_PN3 R258 0R WEBCAM_USBN
[15] USB_PN3 2
A 3 A

R257 @220K Z1911 4


WEBCAM_EN R255 0R WEBCAM_PW_EN 5 NC1
[24] WEBCAM_EN 6 NC2
CON-85205-06001-ACE
WEBCAM_EN = High, Enable Webcam. 85205-06R
ECS COMPUTER CORP.
WEBCAM_EN = Low, Disable Webcam.
WEBCAM_GND Title

L26
WEB CAM/BT/NEW CARD/EXT_USB
Size Document Number Rev
A
HCB1608KF-600T30_0603 3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 19 of 36
5 4 3 2 1
5 4 3 2 1

CN24
DA+ DB+
DA- 1 2 DB-
LAN_X1 3 4
DC+ 5 6 DD+
Y4
LAN_X2 DC- 7 8 DD-
9 10

e
LAYOUT: Place these LAN_AVDD18
25M-6-30-KT-D Place crystal less than
components close to NC3 NC4
82567LM, and use R106 @1M
0.75 inches from LAN NC1 NC2

c
ground guard for Controller(82567LM). CON-WTB-87216-1004-06
LAN_VDD33 LAN_DVDD10 LAN_ATEST_P 87216-10B
LAN_X1 and LAN_X2.
D C111 C116 D
27pF/50V_NP0 27pF/50V_NP0 LAN_ATEST_N R454 @0R

n
LAN_AVDD18

e
L13

10

11

12

13

14
1

9
U20 LAN_AVDD18 V_DAC
HCB1608KF-600T30_0603

LED2

LED1
r
LED0
VCC3_3-1

VCC1_0-1

VCC1_0-2

XTAL2

XTAL1

VCC1_8-1

VCC1_8-2
JTAG_TDO

JTAG_TDI

IEEE_TEST_P

IEEE_TEST_N
57 Place close to C104
GND

e
100nF/10V_X7R
PCIE_TXN6_LAN RES_COMP R435 4.99K_1
PT1 GST5009
[15] PCIE_TXN6_LAN 56 GLAN_RXN REST 15

f
PCIE_TXP6_LAN 55 16
[15] PCIE_TXP6_LAN GLAN_RXP MDI_MINUS[3]
因應 82567LM 跑線,
LAN_AVDD18 54 VCC1_8-10 MDI_PLUS[3] 17 這四組的排列是有改變的。

e
PCIE_RXN6_LAN C475 100nF/10V_X7R HSON 53 18 PT1
[15] PCIE_RXN6_LAN GLAN_TXN VCC1_8-3
PCIE_RXP6_LAN C474 100nF/10V_X7R HSOP 52 19 LAN_AVDD18 MDI3- 12 13 DD-
[15] PCIE_RXP6_LAN GLAN_TXP VCC1_8-4 TD4- MX4-

r
MDI3+ 11 14 DD+
V_DAC TD4+ MX4+ Z2001
51 RESERVED_NC MDI_MINUS[2] 20 10 TCT4 MCT4 15
MDI2- 9 16 DC-
LAN_RSTSYNC MDI2+ TD3- MX3- DC+
[14] LAN_RSTSYNC 50 JRSTSYNC MDI_PLUS[2] 21 8 TD3+ MX3+ 17
V_DAC 7 18 Z2002

le
LAN_RXD2 MDI1- TCT3 MCT3 DB-
[14] LAN_RXD2 49 JRXD2 MDI_MINUS[1] 22 6 TD2- MX2- 19
MDI1+ 5 20 DB+
LAN_RXD1 V_DAC TD2+ MX2+ Z2003
[14] LAN_RXD1 48 JRXD1 MDI_PLUS[1] 23 4 TCT2 MCT2 21
C MDI0- 3 22 DA- C
LAN_RXD0 MDI0+ TD1- MX1- DA+
[14] LAN_RXD0 47 JRXD0 VCC1_8-5 24 2 TD1+ MX1+ 23
V_DAC 1 24 Z2004
TCT1 MCT1

t
LAN_VDD33 46 VCC3_3-3 VCC1_8-6 25 LAN_AVDD18
GLAN_CLK R486 33R GLAN_CLK_R 45 26 GST5009
[14] GLAN_CLK JKCLK MDI_MINUS[0] GST5009
LAN_TXD2 44 27 C422 10nF/25V_X7R
[14] LAN_TXD2 JTXD2 MDI_PLUS[0]

n
LAN_DISABLE_N
LAN_TXD1 43 28 LAN_VDD33 C424 10nF/25V_X7R R87 R86 R85 R84
[14] LAN_TXD1 JTXD1 VCC3_3-2

DIS_REG1_0
75R_1 75R_1 75R_1 75R_1

JTAG_TRST
JTAG_TMS
JTAG_TCK

Place GLAN_CLK series resistor C425 10nF/25V_X7R


VCC1_8-9

VCC1_0-4

VCC1_0-3

VCC1_8-8

VCC1_8-7

I
TEST_EN

CTRL10

CTRL18
close to LAN Controller(82567LM)
JTXD0

C423 10nF/25V_X7R Z2005

82567LF LAYOUT: Place caps close to C100 C101


42

41

40

39

38

37

36

35

34

33

32

31

30

29

s
QFN56_8MA @1nF/50V_X7R 1nF/2KV_1808
PT1 GST5009 pin 1, 4, 7, 10.

LAN_TXD0 LAN_CTRL18

e
[14] LAN_TXD0

LAN_AVDD18
R109 @220K +3.3VS R110 10K_1

d
LAN_DVDD10 LAN_DVDD10
PM_LAN_ENABLE R108 @0R LAN_DIS

i
[15,24] PM_LAN_ENABLE
LAN_AVDD18
LANPHY_EN R107 @0R
[15] LANPHY_EN
B B

v
DIS_REG1P0 R460 1K_1

LAN_TEST_EN R462 10K_1


LAN_VDD33

o
R428 C443 C446
5.11K_1 100nF/10V_X7R 10uF/6.3V_0805_X5R

r
+3.3VM_ON#

3
D14
D

@BAT54 LAN_CTRL18 1 Q48 C110 C476 C477 C454


Q14 BCP69 100nF/10V_X7R 100nF/10V_X7R 100nF/10V_X7R 100nF/10V_X7R
G

+3.3VM_ON A C G Q12 @FET-AO3413 M-SOT223

P
[24] +3.3VM_ON
@FET-2N7002E DECOUPLING

4
S

S D R418
0R_0603 20 mil / 0.4A
LAN_WAKE# R111 Z2006 LAN_AVDD18
[15] LAN_WAKE# LAN_AVDD18
@220K L14 LAYOUT: Place >60mils metal trace.
+3.3VS LAN_VDD33
LAN_VDD33
HCB1608KF-600T30_0603 C109 C445 C441 C442 C472 C113 C437
470pF/50V_X7R 470pF/50V_X7R 100nF/10V_X7R 100nF/10V_X7R 4.7uF/10V_0805_X5R 10uF/6.3V_0805_X5R 10uF/6.3V_0805_X5R
C120 C119 C118
S D 10uF/6.3V_0805_X5R 4.7uF/10V_0805_X5R 100nF/10V_X7R

Q13
G

R112 @56K +3.3VM_ON# @FET-AO3413

A LAYOUT: Place 100nF caps close to U21 82567LM A


LAN_DVDD10 is internal regulator produce LAN_DVDD10 power pin 5, 8, 33, 38.

20 mil / 0.5A
LAN_DVDD10 LAN_DVDD10
ECS COMPUTER CORP.
C115 C466 C468 C459 C114 C469 C117
100nF/10V_X7R 100nF/10V_X7R 100nF/10V_X7R 100nF/10V_X7R 4.7uF/10V_0805_X5R 4.7uF/10V_0805_X5R 10uF/6.3V_0805_X5R Title
GLAN-82567LF
Size Document Number Rev
A
3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 20 of 36
5 4 3 2 1
5 4 3 2 1

Q64 Q33 Q32


FET-SI4800BDY FET-SI4800BDY D7 FET-3LP01C
M-SO8 200 mil / 5.0A M-SO8 200 mil / 5.0A 8 mil / 0.1A BAV99-7-F
+3.3V_AUX 8 1 +3.3V +5V_AUX 8 1 +5V VIN_SW 2 1 Z2513 D S VIN
7 2 7 2

e
6 3 6 3 R262

3
5 S 5 S 100K_1

G
D +5V_LDO D +5V_LDO Z2514
G R578 G R267

c
100R_0603 100R_0603

4
Z2501 C511 Z2504
D @100nF/25V_0603_X7R Z2503 Z2507 C230 R269 D
R562 R265 @100nF/25V_0603_X7R 150K_1

D
R538 56K R270 56K

n
R539 100R_1 R271 100R_1
100K_1 +V_OFF G Q66 100K_1 Z2506 G Q27 Z2515
VIN_SW Z2502 FET-2N7002E VIN_SW Z2505 FET-2N7002E

D
S

S
e
D

D
R575
10R_1 G +5V_ON
+5V_ON [24]
C510 G G +3.3V_ON +5V_ON C237 G PWR_KEEP G

r
[24,31] PWR_KEEP

S
100nF/25V_0603_X7R 100nF/25V_0603_X7R Q29 Q28
S

S
Q61 Q62 Q31 FET-2N7002E FET-2N7002E
FET-2N7002E FET-2N7002E C514 100nF/25V_0603_X7R FET-2N7002E R264

e
220K

f
Q68 Q35
FET-SI4800BDY FET-AO3413
M-SO8 240 mil / 6.0A 12 mil / 0.3A

e
+3.3V_AUX 8 1 +3.3VS +5V_AUX S D +5VS
7 2
6 3 Z2512

r
5 S

G
D +5V_LDO Z2511 R273
G R604 100R_0603

D
100R_0603 R272
4

Z2508 C534 56K

D
le
@100nF/25V_0603_X7R Z2509 G +VS_OFF
R613 D

S
R584 56K +5VS_ON G Q34
[24] +5VS_ON
C R580 100R_1 Q30 FET-2N7002E C

S
100K_1 +VS_OFF G Q69 FET-2N7002E
VIN_SW Z2510 FET-2N7002E
S

R268

t
D

R603 220K
10R_1
C533 G G +3.3VS_ON +5VS_ON
100nF/25V_0603_X7R
S

n
Q67 Q70
FET-2N7002E FET-2N7002E C544 100nF/25V_0603_X7R

s I Straddle plans the capacitance


H4 H5 H7 H13 H17 H28
C237D91 C237D91 C237D91 C237D91 C237D91 C158D158 H18 H20 H21
C276D158-UW C276D158-UW C276D158-UW

e
VIN +5V +5V +5V +5VS +5V_AUX +5V_AMP

CPU

d
C6 C27 C28 C458 C412 C45 C207
10nF/25V_X7R 10nF/25V_X7R 10nF/25V_X7R 10nF/25V_X7R 10nF/25V_X7R 10nF/25V_X7R 10nF/25V_X7R

i
H1 H6 H12 H30 H3 H29
U237X237D91 U237X237D91 U237X237D91 C158D158 C315D126 C158D158
CODEC_GND
B B

v
H19 +5V_AMP +5V_AMP +3.3V +3.3V +3.3V +1.05V +1.05V
C276D158-UW

o
H8
U315X315D106
H9
U315X315D106
H10
U315X315D106
H11
U315X315D91
H15
U315X315D106
H16
U315X315D106
NB C562
10nF/25V_X7R
C588
10nF/25V_X7R
C395
10nF/25V_X7R
C55
10nF/25V_X7R
C478
10nF/25V_X7R
C65
10nF/25V_X7R
C112
10nF/25V_X7R

r
CODEC_GND CODEC_GND

+GFX_CORE +CPU_CORE +CPU_CORE +CPU_CORE

P
H26 H2 H14 H27 M1 M2 H24 H22 C102 C29 C32 C86
U315X315D91 C98D98 C98D98 C158D158 M-MARK1 M-MARK1 C197B158D63-UW C197B158D63-UW 10nF/25V_X7R 10nF/25V_X7R 10nF/25V_X7R 10nF/25V_X7R

WLAN
+3.3V_AUX +3.3V_AUX +3.3V_AUX +3.3V +3.3V +1.05V +1.05V

M3 M4 M5 M6 M7 M8
M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 C87 C316 C132 C97 C197 C159 C48
10nF/25V_X7R 10nF/25V_X7R 10nF/25V_X7R 10nF/25V_X7R 10nF/25V_X7R 10nF/25V_X7R 10nF/25V_X7R
A A

H23 H25 +3.3V +1.8V_DDR +1.5V +3.3VS +3.3VS +1.5V +V1.05M_A_SM


C237D63 C237D63

M9 M10 M11 M12 M13 M14


ODD ECS COMPUTER CORP.
M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1 M-MARK1
BB Title
POWER SWITCH
Size Document Number Rev
A
3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 25 of 36
5 4 3 2 1
5 4 3 2 1

PL3 240mil
815_VIN
VIN
HCB4516KF-600T60_1806

e
120mil PC24 PC21

4.7uF/25V_1206_X5R

4.7uF/25V_1206_X5R
c
PQ11

5
6
7
8
FET-AO4468

D
D 40mil M-SO8 D

PR83 815_HDR2 Z2615 +3.3V_AUX

n
Output Voltage =[ Vref x R2/(R1+R2) ] x 2 4

G
0R

S
815_ON PR19 0R_0603
R1

3
2
1
e
815_VIN
R2
PC28 +3.3V_VSET CS2N PL12
100nF/10V_X7R CS2P 40mil 380mil PJ7
PR82 815_LX2 1 2 +3.3V_Out 1 2

r
54.9K_1
PR87 PC34 PQ12 PQ13 4.7uH/8A_105 OPEN_6A

5
6
7
8

5
6
7
8
815_AGND 84.5K_1 1nF/50V_0603_X7R FET-AO4468 FET-AO4468 PD21 PR90

C
e

D
Vout= 3.334V M-SO8 M-SO8 @2.2R_0603 PR94 PC49 PC42 PC55 PC50 PC52 PC143
+ +3.3V/9.5A

1N5819
PR17 100K_1

1uF/10V_0603_X5R

1nF/50V_X7R

4.7uF/10V_0805_X5R

4.7uF/10V_0805_X5R

4.7uF/10V_0805_X5R

560uF/4V_8*8_OSCON
0R_0603 815_LDR2 4 4 PK=14A

G
815_AGND 40mil

S
815_AGND 815_AGND Z2613

A
PR92
OCP:16A

3
2
1

3
2
1
+5V_LDO 815_HDR2 PC37 PC40 PC41 PC125 21.5K_1 PR86

e
220nF/25V_0603_X7R 2.2nF/50V_0603_X7R 2.2nF/50V_0603_X7R @1nF/50V_0603_X7R 51.1R_1
PD7

25

24
23
22
21
20
19
+5V_LDO

r
PR16 PU2 A C PC129
22R CS2P CS2N

VSET2

PGD2
LX2
HDR2
GNDA

CS2N
CS2P
BAT54 +5V_LDO 15nF/16V_X7R
Z2608 815_VIN PC132

le
+3.3_AUX_ON 1 18 815_BST2 Z2611 22pF/50V_NP0 PC127
Z2609 ON/SKIP2 BST2 815_LDR2 2.2nF/50V_X7R
2 VIN LDR2 17
2.75V 3 16 +5V_LDO PR23 PC38
815_VREF VREF VDDP

1uF/10V_0603_X5R
C PR18 4 15 0R_0603 120mil PC23 PC20 C
0R TSET GNDP 815_LDR1 815_AGND 815_AGND
5 VDDA OZ815 LDR1 14

4.7uF/25V_1206_X5R

4.7uF/25V_1206_X5R
815_ON +5_AUX_ON 6 13 815_BST1
ON/SKIP1 BST1 PQ10

t
PR22 FET-AO4468

VSET1

PGD1

HDR1
CS1N
CS1P
0R_0603 M-SO8

5
6
7
8
LX1
PC30 PC31
1uF/25V_0603_X5R

1uF/10V_0603_X5R

D
PC32 R1 PC27 +5V_LDO A C Z2612 40mil
100nF/10V_X7R

n
@100nF/10V_X7R OZ815

7
8
9
10
11
12
QFN24_4X4X0_75 PD6 BAT54 815_HDR1 Z2616 4

G
PC39
+5V_AUX

S
PR88 100nF/10V_X7R PR20 0R_0603

I
815_AGND 10K_1 PC36

3
2
1
815_HDR1 220nF/25V_0603_X7R
PL11
+5V_VSET 40mil 240mil PJ4
R2 815_LX1 1 2 +5V_Out 1 2

s
PC33
PQ9 4.7uH/8A_105 OPEN_6A

5
6
7
8
470pF/50V_X7R

815_PGD FET-AO4468 PR21 PR95 +5V/6A

D
PR85 CS1P M-SO8 PD5 @2.2R_0603 100K_1 PC121 PC133 PC135 PC26 + PC123

e
C
120K_1 CS1N
PK=8.5A

1N5819

1nF/50V_X7R

1uF/10V_0603_X5R

4.7uF/10V_0805_X5R

4.7uF/10V_0805_X5R

390uF/6.3V_8*10.5_OSCON
815_LDR1 4
PJP4 PR93

G
PR81 40mil

S
PR91 0R Z2614
2 1 OCP:9A

d
210K_1

3
2
1

A
815_AGND 815_AGND CLOSE PC25 PC35 48.7K_1
Z2610 2.2nF/50V_0603_X7R @1nF/50V_0603_X7R PR89

i
Z2618 815_AGND 51.1R_1
PC130 8.2nF/25V_X7R
D

Vout= 5.021V CS1P CS1N


B PC29 PR80 B

v
Z2617 G 22nF/16V_X7R @51K_1
[24] SMARTVOL
PQ31
S

PR84 FET-2N7002E EC_SKIP Mode Select Table PC134 PC128


1K_1_0603 22pF/50V_NP0 2.2nF/50V_X7R

o
815_AGND 815_AGND S0 S1 S3 S4 S5
PR96
"High"= 4.863V PC124 220K Adapter High High Low High High
"Low" = 5.077V 100nF/10V_X7R 815_AGND 815_AGND
Output Voltage =[ Vref x R2/(R1+R2) ] x 2

r
815_AGND Battery Low Low Low Low Low

PR103 @0R_0603 EC_SKIP = High, OZ815 PWM Mode.


+5V_LDO
EC_SKIP = Low, OZ815 Skip Mode.

P
815_AGND
AUX_ON PR102 0R_0603
[31] AUX_ON

SMARTVOL Mode Select Table Z2601

S0 S1 S3 S4 S5
Adapter Low Low Low Low Low PR77 PR101
56K_0603 150K_1
Battery High High High High High PR79
10K_1
D

PC120 AUX_OFF# 815_ON


[5] AUX_OFF#
SMARTVOL = High => 4.863V. 1uF/10V_0603_X5R
Z2619 Z2620 G PR100
SMARTVOL = Low => 5.077V. 0R
D

PQ30 PR99
A
FET-2N7002E 51K_1 A
815_PGD G
Z2602

D
S

PQ29 PR78 PR104


FET-2N7002E 510K_0603 0R
EC_SKIP Z2603 G
[24] EC_SKIP
PQ32
ECS COMPUTER CORP.

S
EC_SKIP +3V/+5V_ON Voltage Mode FET-2N7002E
EC_SKIP = High, OZ815 PWM Mode. PC141
H 2.1V > 815_ON > 0.6V PWM 815_AGND 815_AGND 815_AGND 470pF/50V_X7R Title
EC_SKIP = Low, OZ815 Skip Mode.
L >2.1V SKIP +3.3V_AUX/+5V_AUX (OZ815)
Size Document Number Rev
A
815_AGND 815_AGND 3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 26 of 36
5 4 3 2 1
1 2 3 4 5

VIN_CPU
+5V

e
120mil PL5 240mil
VIN

A
PR113 HCB4516KF-600T60_1806

c
10R_1 PC58 PC138 PC44 PC48 PC45 PC46
PD23 +

10uF/6.3V_0805_X5R

10uF/25V_8*9_OSCON

4.7uF/25V_1206_X5R

4.7uF/25V_1206_X5R

1uF/25V_0805_X7R

100nF/25V_0603_X7R
A @BAT54 A

C
8770VCC

n
8771BST1

5
6
7
8
PC149 VIN_CPU

e
2.2uF/10V_0603_X5R 9

PR132 Z2727 4
8770_AGND 0R_0603 PC158 PQ14

r
PR121 220nF/25V_0603_X7R FET-RQW130
+3.3V 200K_1 M-PSOP8 +CPU_CORE/44A

19

25
e
PU6
Z2716 PR110
PK=50A
8 Panasonic

VCC

VDD

3
2
1
TON 0R_0603

f
+CPU_CORE
R286
PR130
100K_1 BST1 30 8771BST1_R 0.36uH/1.1mOhms
@0R 28 8771LX1 1 2
DELAY_VR_PWRGOOD CPU_PWRGD LX1
[7,15] DELAY_VR_PWRGOOD 2

e
PWRGD 8771DH1 PL14
29

C
VCORE_CLK_EN# DH1 PR123 0.36uH/30A_104
[15] VCORE_CLK_EN# 1 CLKEN
26 8771DL1 @2.2R_0603 + PC157 PC59 + PC64 + PC61
DL1

5
6
7
8

5
6
7
8
r
PD8

820uF/2.5V_8*9_NPCAP

4.7uF/10V_0805_X5R

@330uF/2V_7343_SPCAP

330uF/2V_7343_SPCAP
[12] CPU_VID0 CPU_VID0 PR135 0R Z2701 31 27 9 9 SK34A
CPU_VID1 PR136 0R Z2702 D0 PGND1 Z2722
[12] CPU_VID1 32

A
CPU_VID2 PR137 0R Z2703 D1 PR118
[12] CPU_VID2 33 D2 4 4
CPU_VID3 PR138 0R Z2704 34 PR115 PC146 4.7K_1

le
[12] CPU_VID3 D3
CPU_VID4 PR139 0R Z2705 35 @3.48K_1 @4.7nF/50V_X7R PC152
[12] CPU_VID4 D4
CPU_VID5 PR140 0R Z2706 36 Z2718 PC53 @1nF/50V_0603_X7R PR112 PR111
[12] CPU_VID5 D5
CPU_VID6 PR141 0R Z2707 37 @2.2nF/50V_0603_X7R Z2724
B
[12] CPU_VID6 D6 B
Z2717 PR106 PQ15 4.02K_1 10K_NTC

3
2
1

3
2
1
100R_1 FET-RQW200
H_PSI# PR128 0R Z2708 Z2719 M-PSOP8

t
[5] H_PSI# 3 PSI FB 12 VCCSENSE [6]
PR109 PC147 220nF/25V_0603_X7R distribute evenly between N side and S
[24] +CPU_CORE_ON +CPU_CORE_ON PR142 10K_1 Z2709 38 3.48K_1 PQ18 8771CSP1 side, preferably on secondary side.
SHDN PC145 FET-RQW200
[5,7,14] H_DPRSTP# H_DPRSTP# PR134 0R Z2710 40 1nF/50V_X7R PR24 M-PSOP8
DPRSTP

n
@10R Use differential routing away from switch nodes
PM_DPRSLPVR PR133 499R_1 Z2711 39 120mil 8771LX1 and 8771LX2
[7,15] PM_DPRSLPVR DPRSLPVR PC153 8770_AGND +CPU_CORE VIN_CPU
Z2720 Z2721

I
CCI 10
8770_AGND PC155 470pF/50V_X7R Z2712 9 PR107 20K_1 PC43 PC51 PC47 PC57 PC54
CCV 470pF/50V_X7R

4.7uF/25V_1206_X5R

4.7uF/25V_1206_X5R

4.7uF/25V_1206_X5R

1uF/25V_0805_X7R

100nF/25V_0603_X7R
5
6
7
8
PR143 220K Z2709 8770_AGND PR126 71.5K_1 Z2713 7 13 Z2726 PR114 100R_1
TIME GNDS VSSSENSE [6]
9

s
17 8771CSP1
8771REF 11 CSP1 +CPU_CORE PC150 PR25 Z2728
8770_AGND REF CSN1 16 4
8770_AGND PC151 220nF/25V_0603_X7R 1nF/50V_X7R @10R PQ17
18 14 8771CSP2 FET-RQW130

e
8770_AGND GND CSP2
41 15 +CPU_CORE M-PSOP8
Z2714 EP CSN2 8770_AGND
8770VCC
PR124 10K_1
8771DH2
6 21 Panasonic

3
2
1
THRM DH2

d
PR119 0R_0603
8771DL2 +CPU_CORE
+3.3V
PR125
@10K_NTC DL2 24 0.36uH/1.1mOhms

i
22 8771LX2 1 2
LX2
5 VRHOT
20 BST2_R PL13

C
C 8770_AGND Z2715 4 BST2 0.36uH/30A_104 C

v
POUT

5
6
7
8

5
6
7
8
PR127 23
10K_1 PGND2 PD9 PR108
9 9 + PC156 PC60 + PC62 + PC63 + PC65
MAX8770 SK34A @2.2R_0603

820uF/2.5V_8*9_NPCAP

4.7uF/10V_0805_X5R

330uF/2V_7343_SPCAP

@330uF/2V_7343_SPCAP

330uF/2V_7343_SPCAP
PR131 QFN40_6X6X0_8 4 4

A
o
EC_PROCHOT PR129 @0R 8770_HOT 10K_1 PR120 Z2723
[5,24] EC_PROCHOT
0R_0603 PC154 PR116
POUT 220nF/25V_0603_X7R 4.7K_1
[17] POUT
PC144

r
@1nF/50V_0603_X7R PR117 PR122
PC159 8771BST2 PC56 PQ16 Z2725

3
2
1

3
2
1
100nF/10V_X7R @2.2nF/50V_0603_X7R FET-RQW200
M-PSOP8 4.02K_1 10K_NTC
C

P
8770_AGND PD22
PJP2 @BAT54 PC148 220nF/25V_0603_X7R
CLOSE 8771CSP2 distribute evenly between N side and S
PQ19 side, preferably on secondary side.
A

2 1 FET-RQW200
M-PSOP8
Add layout note on pins 22 and 28 of MAX8771
controller. These nets have large voltage swings.
Need to route them away from the sensitive areas that 8770_AGND +5V
are trying to detect small changes in voltage, such as Use differential routing away from switch nodes
Sense lines are 18 mil wide, Z0=27.4 Ohm. 8771LX1 and 8771LX2
the voltage sense VccSense VssSense lines. Use differential routing with 7 mil spacing.
Route external layer with solid GND reference
(no split planes).
Use 25 mil separation from any other signal.
D D

ECS COMPUTER CORP.


Title
+CPU_CORE (MAX8770)
Size Document Number Rev
A
3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 27 of 36
1 2 3 4 5
A B C D E F G H

e
VINO PL7 VIN

c
HCB4516KF-600T60_1806

1 1

n
80mil PJ3 80mil
1 2
+3.3V
OPEN_3A

e
PR162 @10K_1 PQ25

5
6
7
8
PR167 @10K_1 FET-AO4468 PC87 PC88 PC180
4.7uF/25V_1206_X5R 4.7uF/25V_1206_X5R 100nF/25V_0603_X7R 0.7V~1.25V

D
PR171 @10K_1 M-SO8
PR180 @10K_1 40 mil 240mil 240mil

r
PR189 @10K_1 Z2805 Z2813 4 +GFX_CORE

G
PL16 @HCB4516KF-600T60_1806 +1.05V

S
PR40 0R_0603

e
PR164 0R 827_VID0 PL17 @HCB4516KF-600T60_1806
[7] GFXVR_VID_0

3
2
1
PR166 0R 827_VID1 PL18
[7] GFXVR_VID_1
PR170 0R 827_VID2 40 mil 360mil PJ8
[7] GFXVR_VID_2

f
PR179 0R 827_VID3 Z2806 1 2 V GMCH 1 2
[7] GFXVR_VID_3
PR188 0R 827_VID4 1.5uH/9A_063
[7] GFXVR_VID_4
OPEN_6A
PQ22 PQ23

C
5
6
7
8

5
6
7
8
PR186 @91K_1 PC174 FET-AO4468 FET-AO4468 PR191 PR190 PR193 +GFX_CORE/9A

D
PR181 @91K_1 220nF/25V_0603_X7R M-SO8 M-SO8 1.5K_1 464R_1 0R_0603
PR172 @91K_1 Z2807 40 mil PR169 Z2814 PC167 PC166

18
17
16
15
14
13
PK=11A

C
r
PR168 @91K_1 PU7 OZ827 4 4 @2.2R_0603 + + PC69 PC160 PC70 PC173 PC68

220uF/6.3V_6*5.7_NPCAP

220uF/6.3V_6*5.7_NPCAP
PR163 @91K_1 PR159 PD24 PD13

VID3
VID2
VID1
VID0
LX
HDR

4.7uF/10V_0805_X5R

4.7uF/10V_0805_X5R

4.7uF/10V_0805_X5R

1nF/50V_X7R

4.7uF/10V_0805_X5R
Z2811

S
2.2R_0603 BAT54 1N5819

3
2
1

3
2
1
+5V PR192

A
le
827_AGND 19 12 Z2808 PC178 10R_1
Z2802 VID4 BST @2.2nF/50V_0603_X7R
20 SLEW VDDP 11
+5V Z2803 21 10
827_CSP 22 VDDA GNDP
2 9 Z2809 2
PR187 827_CSN 23 CSP OZ827 LDR
8 Z2810 PC189
22R 827_RSP 24 CSN PGD 220nF/25V_0603_X7R
RSP ON/SKIP 7
PC175 PC80 PC79

t
COMPV
PC193 PC190 827_CSP

1uF/25V_0603_X5R
25 GNDA @2.2nF/50V_0603_X7R @2.2nF/50V_0603_X7R
VREF
TSET
1uF/25V_0603_X5R 10nF/25V_X7R
RSN
ILIM

VIN
PC191
47nF/16V_X7R

n
827_AGND QFN24_4X4X0_75 827_CSN
1
2
3
4
5
6

827_RSN VINO
Z2812

827_AGND 827_AGND ILIM

I
PC194 PC195
827_VREF 22pF/50V_NP0 2.2nF/50V_X7R
PR165
PR173 TSET 3K_1
+3.3V

s
0R PR175
36K_1 OCP=11A Z2804 PR158 827_AGND 827_AGND
@10K_1
Freq.=300Khz

e
ILIM PC183
TSET 100nF/10V_X7R
PC182 PC179
2.2nF/50V_X7R 2.2nF/50V_X7R

d
PR174 PR182 PC186 PC184
@91K_1 12.7K_1 100nF/10V_X7R
1nF/50V_X7R

i
PR184 PR185
827_AGND 827_AGND 827_AGND 827_AGND 10R_1 10R_1
3 827_AGND 3

v
827_AGND 827_AGND

o
827_RSP VCC_AXG_SENSE
VCC_AXG_SENSE [9]
+GFX_VR_ON SKIP_EN
[24] +GFX_VR_ON
PR183
PR155 560R

r
0R PJP6
PC177 CLOSE PC187
PR161 2 1
220K @1nF/50V_X7R 1nF/50V_X7R

P
827_AGND 827_RSN VSS_AXG_SENSE
VSS_AXG_SENSE [9]
827_AGND 827_AGND PR178
560R

827_VREF

PR176 PR177
@22K 20K_1

4 4

ECS COMPUTER CORP.


Title
+GFX CORE (OZ827)
Size Document Number Rev
A
3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 28 of 36
A B C D E F G H
5 4 3 2 1

PL2
HCB4516KF-600T60_1806
VIN

e
818_HDR
818_CSN PJ1 100mil
VIN_DDR 1 2
818_CSP

c
PR14 PC17 PC16 OPEN_3A
0R_0603

4.7uF/25V_1206_X5R

4.7uF/25V_1206_X5R
D D

5
6
7
8
D
+5VS 818_HDR +5VS +5VS PQ6 15. Del PR13, Net VDDIO_FB (Page.29)

n
FET-AO4468
10 mil Z2905 4 M-SO8 PL9

G
10 mil PD18 40 mil

12
11
10
+1.8V_DDR

9
e

S
PR72 PU4 OZ811LN BAT54 1 2
+1.8V_DDR=2.75*R2/(R1+R2) 22R 1.5uH/9A_063

CSN
CSP
LX
HDR

3
2
1
Z2906
811_VREF = 2.75 V PR59 PL10 450mil

r
C
0R_0603 Z2907 40 mil PJ5
818_VSET 13 8 Z2904 PC109 1 2 818_OUT 1 2
818_VREF VSET BST @1.5uH/10A_104
14 VREF LDR 7

e
818_TSET 15 OZ811LN GNDP 6 220nF/25V_0603_X7R OPEN_6A
TSET

5
6
7
8

5
6
7
8
818_VDDA 16 5 PR58 +1.8V/11A

C
VDDA VDDP

D
PR60 100K_1

ON/SKIP
f
40 mil @1R_0603
PR62 PC114 PD4
PK=16A
17 4 4 + PC119 PC131 PC115 PC126 PC122

PGD
OCT
GNDA

VIN

G
20K_1 PR64 1uF/10V_0603_X5R 1N5819 Z2909
OCP:18A

820uF/2.5V_8*9_NPCAP

1uF/10V_0603_X5R

1nF/50V_X7R

4.7uF/10V_0805_X5R

4.7uF/10V_0805_X5R
S

S
PC110 0R PC118 PR13 18.2K_1

A
100nF/10V_X7R 22nF/25V_0603_X7R QFN16_4X4X0_75

1
2
3
4

3
2
1

3
2
1
Z2901 PC111 PC15 PC14 PC112

2.2nF/50V_0603_X7R
Vout= 1.821V 1uF/10V_0603_X5R 2.2nF/50V_0603_X7R @2.2nF/50V_0603_X7R

r
PR75 @0R_0603 PR12
Z2908 51.1R_1

PR63 VIN_DDR PR73 1K_1_0603 Z2902


PC108 @91K_1 PC113 818_CSP PC106 6.8nF/50V_X7R 818_CSN

le
1nF/50V_0603_X7R 22nF/16V_X7R
PR76 PQ5 PQ4
@51K_0603 PC116 FET-AO4468 FET-AO4468 PC107 @6.8nF/50V_X7R
C 10nF/25V_X7R M-SO8 M-SO8 C
PR61
39.2K_1
DDR_PWROK [7]

t
PC105 PR11 PC104
Z2903 22pF/50V_NP0 7.5K_1 6.8nF/50V_X7R
[10,24] +DDR_ON
PR69 0R R263 12.1K_1 +3.3VS

n
ON Vih = 0.6V PR68
PC117 220K
@10nF/25V_X7R PJP1

I
2 1

CLOSE

811_AGND

d e s
i
B B

ro v layout to PJ5 +1.8V_DDR +1.8V_DDR


layout to DIMM

P
+3.3VS

40mil PR105
0R_0603

Z2912 PU5
1 VIN VCNTL1 5
6 PC139
VCNTL2 1uF/10V_0603_X5R
PC142 Z2913 3 REFEN
VCNTL3
VCNTL4
7
8 +0.9V_DDR
1uF/10V_0603_X5R PR97
10K_1 9 PGND
PJ6 40mil +0.9V/1A
2 4 Z2914 1 2
GND OUTPUT

A
FP6137-2A OPEN_2A A
M-SO8_PPA

PC137 PC136 PC140 C240 C241


100nF/10V_X7R PR98 4.7uF/10V_0805_X5R 4.7uF/10V_0805_X5R 100nF/10V_X7R 100nF/10V_X7R
10K_1
ECS COMPUTER CORP.
Title
+1.8V_DDR(OZ811)/+0.9V(LDO)
Size Document Number Rev
A
3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 29 of 36
5 4 3 2 1
5 4 3 2 1

8138_VREF
PL6
HCB4516KF-600T60_1806
+3.3V

e
PR148 8138_VIN VIN
82.5K_1
80mil 120mil PJ2
1 2

c
Vout= 1.067V +1.05V_SET PR146 PQ33
10K_1 FET-AO4468 PC161 PC163 PC162 OPEN_3A

5
6
7
8
D PC76 M-SO8 D

4.7uF/25V_1206_X5R

4.7uF/25V_1206_X5R
1uF/25V_0603_X5R
D
40mil

1nF/50V_X7R
n
PR145 +1.05V_PWRGD 8138_HDR1 Z3001 4
+1.05V_PWRGD [15]

G
52.3K_1

S
PR144 0R_0603

e
8138_CS1N +1.05V

3
2
1
8138_CS1P PL15
8138_AGND 40mil 450mil PJ9
8138_AGND 8138_LX1 1 2 +1.05V_OUT 1 2

r
1.5uH/9A_063
PQ20 PQ21 OPEN_6A+1.05V/11A

5
6
7
8

5
6
7
8
FET-AO4468 FET-AO4468

C
e

D
M-SO8 M-SO8 PR32 PR30 PR27 PC71 PC74 PC72 PC73 PC164 PC165
8138_AGND 8138_HDR1 PC77 @2.2R_0603 100K_1 51.1R_1
PK=16A
+ +

1nF/50V_X7R

1uF/10V_0603_X5R

4.7uF/10V_0805_X5R

4.7uF/10V_0805_X5R

220uF/6.3V_6*5.7_NPCAP

220uF/6.3V_6*5.7_NPCAP
8138_VIN 220nF/25V_0603_X7R 8138_LDR1 4 4 PD11

f
G

G
40mil 1N5819 Z3007
PD10 OCP:18A

S
8138_CS1P PR26 18.2K_1 8138_CS1N

25

10
11
12

A
7
8
9
+5V A C Z3004

3
2
1

3
2
1
+5V PC67 PC66 PC75

VSET1

PGD1
LX1
HDR1
GNDA

CS1N
CS1P

e
PR33 2.2nF/50V_0603_X7R 2.2nF/50V_0603_X7R @2.2nF/50V_0603_X7R
1K_1_0603 BAT54 PC168 6.8nF/50V_X7R

r
1.05_ON 6 13 8138_BST1 PR31 0R_0603
PR29 Z3003 2 ON/SKIP1 BST1 8138_LDR1
VIN LDR1 14
22R 8138_VREF 2.75V 3 16 +5V +5V
8138_TSET VREF VDDP PC170 PC169 PR28
4 TSET GNDP 15
8138_VDDA 5 17 8138_LDR2 22pF/50V_NP0 2.2nF/50V_X7R 5.36K_1
OZ8138

le
1.5_ON VDDA LDR2 8138_BST2 PR34 0R_0603 8138_VIN
1 ON/SKIP2 BST2 18
PC82
1uF/10V_0603_X5R 40mil
VSET2

PGD2

HDR2
CS2N
CS2P
C 8138_AGND 8138_AGND 8138_AGND C

LX2
PC78 PC83 PR151 PC81 PC84 PQ34
10nF/25V_X7R

1uF/10V_0603_X5R 100nF/10V_X7R 0R 22nF/16V_X7R FET-AO4468 PC192 PC188 PC185

5
6
7
8
PU3 OZ8138 M-SO8

t
PD12
24
23
22
21
20
19

4.7uF/25V_1206_X5R

@4.7uF/25V_1206_X5R
1uF/25V_0603_X5R
D
QFN24_4X4X0_75 40mil
8138_AGND +5V A C Z3005
8138_AGND 8138_AGND 8138_HDR2 Z3002 4

G
BAT54

n
S
PR150 8138_HDR2 PR154 0R_0603 +1.5V
+1.8V_SET

@50K_1

3
2
1
8138_AGND PC85 PL19
220nF/25V_0603_X7R PJ10

I
40mil 160mil
Z3006 1 2 +1.5V_OUT 1 2
8138_AGND 4.7uH/5.5A_063
PR152
8138_CS2P PQ24 OPEN_3A +1.5V/4A

5
6
7
8
8138_VREF 8138_CS2N FET-AO4468 PR36 PR38

C
D
M-SO8 PR35 100K_1 51.1R_1 PC91 PC90 PC92 PC181
PK=5A

s
+1.5V_PWRGD @2.2R_0603 +
62K_1 +1.5V_PWRGD [15]

1nF/50V_X7R

1uF/10V_0603_X5R

4.7uF/10V_0805_X5R

220uF/6.3V_6*5.7_NPCAP
8138_LDR2 4 PD14

G
PC86 40mil @1N5819 Z3008
OCP:7.5A

S
PR153 8138_CS2P PR37 15.8K_1 8138_CS2N

e
A
1nF/50V_X7R

Vout= 1.505V 75K_1 PJP5

3
2
1
PR160 CLOSE PC93 PC89
10K_1 2 1 2.2nF/50V_0603_X7R @2.2nF/50V_0603_X7R
PC176 8.2nF/25V_X7R

d
8138_AGND
8138_AGND

i
+3.3V PC172 PC171 PR39
22pF/50V_NP0 2.2nF/50V_X7R 7.5K_1
B B

v
8138_AGND 8138_AGND 8138_AGND
+1.5V_ON

o
PR149

r
0R

1.05_ON

P
PR147
220K

8138_AGND

+1.5V_ON
[24] +1.5V_ON

PR157
0R

1.5_ON
A A

PR156
220K

ECS COMPUTER CORP.


8138_AGND
Title
+1.05V/+1.5V (OZ8138)
Size Document Number Rev
A
3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 30 of 36
5 4 3 2 1
5 4 3 2 1

+3.3V_AUX

RST_EC

D
PR66
100K_0603 PQ28
G FET-2N7002E
+3.3V_AUX

S
AC_IN [24]

e
+3.3V_AUX
100 mil
PR65 PR74
PR46 56K 56K

c
@10R PR50
BAT IN 20K_1
D D
200 mil PL1 HCB4516KF-600T60_1806 200 mil PD3 200 mil
CN1

n
VIN
VBAT
1 PQ7 SK54
2 Z3101 PR4 FCM1005KF-121T03 SMB_CLK_BAT @FET-FDS4435BZ
3 SMB_CLK_BAT [24]

e
Z3102 PR5 FCM1005KF-121T03 SMB_DATA_BAT 8 1
4 SMB_DATA_BAT [24]
Z3115 7 2
5 Z3103 Z3104
6 BATT_TEMP [24] 6 3
PR45 100R_1 5 S

r
C
7 D M-SO8
Battery_CON G
BTJ-07RO4GA PC4 PC5 PC6 PD1 PC95 PR67

4
e
PIN GND1~2=GND 100nF/25V_0603_X7R 220pF/50V_NP0 220pF/50V_NP0 @UDZS3.6B 220pF/50V_NP0 @330R_0603
Z3105

A
f
PR70
@22K_0603

DC IN

e
VADAP

100 mil

100 mil
CN19 PL4 PR15
PF1 HCB4516KF-600T60_1806 25mR_1_1W_2512 200 mil PD20

r
Z3106 Z3107
1

C
2 5A_6126_M-F6126 SK54
+5V_LDO 3
PQ3 TR-PMBT2907A 4 PD19 PC18 PC22 PR71 PC19 PR2 PR3

le
5 @SK34A 100nF/25V_0603_X7R @10nF/50V_0603 10K_1_0603 100nF/25V_0603_X7R 10R_1 10R_1
E C AUX_ON [26] 6 PQ8

A
@FET-FDS4435BZ
C Z3108 CON-WTB-4501-Q06N-17B 8 1 C
B

4501-06LA 7 2
PR7 6 3
56K PR6 PC3

t
5 S
10K_1 1uF/10V_0603_X5R D M-SO8
G PR41
@220K

4
Z3109

n
M8602IACP

M8602IACM
C A
D

PWR_SW [24]
Z3112
PD17 BAT54 BAT_AUX_ON BAT_AUX_OFF
Z3110

I
G
PQ32 2N7002 Remove Add PR42
S

PQ2 @470K
PWR_KEEP [24,25]
FET-2N7002E PR8
100K_1 PC10 Z3111 VADAP PQ35 2N2907 Remove Add
100nF/25V_0603_X7R Z3113

s
PD16 PR10
DAN202K 100K_0603

D
e
G

S
PR55 PQ26
CHG_V 0R_0603 M8602REF @FET-2N7002E

d
H 16.8V ( 4CELL ) [24] CHG_V
PR44 @0R
12.6V ( 3CELL )

i
L AC_IN [24]
PS1
POLY SWITCH
B Z3118 B

v
CHG_I Ich PC98
2.2uF/10V_0603_X5R PC8 PC7
3.36V 2.8A PR1 PR43

4.7uF/25V_1206_X5R

4.7uF/25V_1206_X5R
PR56 22R_0805 22R_0805

o
3V 2.5A 0R_0603 BATT_AGND PR47
PC99 PC100 PU1 2.2R_0603 Z3120
[24] CHG_I

3
2
1
2.4V 2A 4.7uF/10V_0805_X5R 4.7uF/10V_0805_X5R M8602REF 8 9 M8602VAC

C
REF VAC

S
r
1.2V 1A M8602LV 10 M8602HDR Z3114 PQ1 PD15

G
7 LV HDR 4
PR57 BATT_AGND BATT_AGND FET-FDS4435BZ RLZ24B
0.48V 0.4A @10K_0603 BATT_AGND 6 11 M8602CHIGH M-SO8
GND CHIGH

A
PR52 PC13 Z3117 PR9 M8602COMP 5 12 PC2 PR54

P 5
6
7
8
107K_1 1K_1 COMP ACAV 470nF/25V_0805 40mR_1_1W_2512 100 mil
BATT_AGND 100nF/25V_0603_X7R M8602VSET 4 13 M8602ICHP Z3119 1 2 Z3121
BATT_AGND VSET ICHP PL8
ADAPTOR_I 3 14 M8602ICHM 15uH/3.6A_104
CHG_ON IOUT ICHM
M8602CELLS 2 15 PC101 PC97 PC96 PC102 PC103 PR48
L CHARGER ON CELLS IACM

4.7uF/25V_1206_X5R

4.7uF/25V_1206_X5R

4.7uF/25V_1206_X5R

4.7uF/25V_1206_X5R

1nF/50V_X7R
Z3116 PR53 10R_1 PC1
[24] CHG_ON
56.2K_1 PC12 M8602ISET 1 16
H CHARGER OFF ISET IACP

@4.7uF/25V_1206_X5R
PR49 100nF/10V_X7R PD2
0R_0603 OZ8602 SK54 PC94
M-SOP16P 2.2uF/10V_0603_X5R

BATT_AGND BATT_AGND

M8602IACP
ADAPTOR_I
1A 0.25V M8602IACM
D

A A

1.5A 0.375V BATT_AGND PC9


G
2A 0.5V PQ27 100nF/10V_X7R
S

FET-2N7002E
2.5A 0.625V PR51
30K_1_0603
PJP3 ECS COMPUTER CORP.
3A 0.75V PC11
2 1
Title
3.5A 0.875V 10nF/25V_X7R
CLOSE AC IN & CHARGER (OZ8602)
BATT_AGND Size Document Number Rev
A
[24] ADAPTOR_I BATT_AGND 3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 31 of 36
5 4 3 2 1
5 4 3 2 1

Sch Sch
Rev. PCB Rev. Data REVISION DESCRIPTION Rev. PCB Rev. Data

A.00 37GF30000-A0 2007/xx/xx 1. (Page.x)

c e
D D

re n
re fe
le
C C

In t
d e s
i
B B

ro v
A
P Title

Size Document Number


ECS COMPUTER CORP.

MB REV.HISTORY
Rev
A

A
3931
Custom F30II0
Date: Monday, November 05, 2007 Sheet 32 of 36
5 4 3 2 1

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