CEG2136 Midterm Exam 2018 Université d'Ottawa University of Ottawa Facute de genie Feouty of Engineering cole de scence infomaique ‘Schoo! of Bocteal Enginoering at de onl diectique uOttawa ‘and Gomputer Science [Untvesht canatienne ‘Canada's envy CEG2136: Computer Architecture I! CEG2536: Architecture des Ordinateurs 1 MIDTERM EXAMINATION Professors: Voicu Groza, Fadi Malek and Mohamed Ali Ibrahim Question 1 (20 points) a) (5 points) You have a SRAM memory chip with a capacity of 64k x 8 1) How many data lines does it have? “Answer 1) 8 2) How many address lines does it have? Answer 2) wo. 3) What is its capacity expressed in "bits"? Answer 3) 2'°2° bits = 2" bits = 2° kbits = 512 kbits = 0.5 M bits b) Using D-type flip-flops, design a 3-bit Gray code counter which has the following counting sequence: 000 — OO — O1L + O10 —+ 110 — Il — 101+ 100 a Draw the transition table of the counter and derive the excitation equations of the D flip flops” inputs. | iy | Qo) Foner | init) | Qo) I] Ds TDi I Do ojo 0 0 0 1 ofofi ojo 1 0 1 1 ofiti 0 1 0 1 1 0 if ito 0 i 1 0 1 0 ojfito i 0 0 o 0 o ofofo 1 0 1 1 0 0 ifofo 1 1 0 1 1 1 ififi 1 1 1 1 0 1 ifofti 1 Pe = (01 ® 00)" University of Ottawa, Faculty of Engineering, School of Plectrical Engineering and Computer ScienceCEG2136 Midterm Exam 2018 Question 2 (20 points) Design a 3-bit register whose function is described in the following table, where M and N are two control bits. Using the proper digital components (encoders, decoders, multiplexers, ete.) logic gates, and D flip-flops, draw a detailed diagram of the logic circuit of the register. “N MN _ Operation Next state _D; No change QAO 0 1 Loading external inputs bilo bh Io Decrement by I (count down) Q Qi Qo-1 ? I] Increment by 3 (count up) QrQiQu+3 ? 5 Using the D FF Excitation equation D; = Q/""' for i=0,1,2 0 MN J2\CK 0 1 7 2: om D @ 1 fo hu 1 x cu 1 , 0 2 M D fi u ore. x leuk 1 = ber estty + 5 we University of Ovtawa, Facully of Engineering, School of Electrical Engineering and Computer ScienceCEG2136 Midterm Exam 2018 QxAn+1) ‘Next State Qi(ntl) Excitation Equations x(n) Qi(n) D2 = Q2Q0+Q1) + Q2'Qi'Qo" = Q © (Qi+Qo) Di = Q1'Qo’+ 100 Do= Qo" Dz = Q2'(Qo+Q1) + Q201'Qo’ Q2 B (Qi+ Qo) Qr'Qo'+Oi00 Di Do= Qo" Dz= M'N'Q2+ M'N In + MN’ Q2 © (Qi+Qo) + MN Q2 ® (Qi+Qo) Di=M'N'Qi + MN +MN' (Qi Qo) +MN(Qi © O)=MN'Q1+M'NL+M(Oi © Q) Dy =M'N'Qo+ M'N lo + M Qo’ Implementation with MUX’s and gates (as above) or with gat exclusively. University of Ottawa, Faculty of Engineering, School of Blecirical Engineering and Computer ScienceCEG2136 Midterm Exam 2018 +++ or with MUX’s & adders ss or with adders MN Operation MN 1 term + '2° term +! cy 00 | No change 00 QQ Qos 0 0 OF 0 O1 | Loading bh In ol bh b+{/0 0 040 10 | Decrement by 1 11 | Increment by 3 10 u QQ Qo+it 11 QO Qo+i0 11 MN G0 clockCEG2136 Midterm Exam 2018 Question 3 (30 points) The 2's complement representation is used in an 8-bit register which contains the binary value 11011000. a, What is the decimal value of the number stored initially in the register? 2 2 2 a 2 2 2 2 R [4[4Jo]4]4Jofofo Conversion to decimal 1101 1000 =- x => x = 2°s complement of 1101 1000 = 0010 1000 = 40 => 1101 1000 =~ 40 or 1101 1000= 4264 244 29-198 + 64-4 16+ 8=-128-+ 88 = 240 b, What is the register value after an arithmetic shift right? Give your result both in binary and decimal. 2 2 2 2 2 2 2 2 1[a7TovTi1{[ivTofoyo Ti PT ilT at a agli Sieaued uence cue cima = -y => y = 2's complement of 1110 1100 = 0001 0100 = 20 => 1110 1100 =-20 or ¢. Starting again from the initial number 11011000, determine the register value after an arithmetic shift left, both in binary and decimal, 27 26 2 24 23 22 21 2 1]1[o[1]1Jolo | [4tol1|afololo Conversion to decimal: =a 2= Conversion to +284 8+ DZ 128 + 64 +32 +8 +4 =-128 + 10 s complement of 1011 0000 = 0101 0000 = 64+16 = 80 => 1011 0000 =- 80 27+ 28+ 24=-128 + 32+ 16=-128 +48 =-80 d. What arithmetic pain fe performed by these shifts? e. Is there any overfiow? Justify your answer. University of Ottawa, Facully of Engineering, School of Electrical Engineering and Computer SereneCEG2136 Midterm Exam 2018 Question 4 (30 points) A 3-bit arithmetic circuit takes three control bits, x, y and z, and two 3-bit data inputs, A and B. ‘The operations supported by the arithmetic unit are described in the following table. Draw a detailed logic diagram of the circuit using |-bit full adders and the digital components of your choice (encoders, decoders, multiplexers, etc.) (Note: A’ is the I’s complement of A) T pew FoF iFo 4 a ey z 0 1 x x IB sey 00 +B (add) |F=A+Be1 00 o1 +B F=A-B(ubtract) | 9, 10 [R= A (wansfer) [F= AI Gneremen | | 4 11 [F=A-1 F=A+1 (decrement) Iniversity oT Otiawa, Pacully of Engineering, School of Flconical Engineering and Comparer SoTenoe