COMPUTER ORGANIZATION (20BT30501) UNIT-1 II CSE

 SREE VIDYANIKETHAN ENGINEERING COLLEGE

 (Autonomous)
 Sree Sainath Nagar, A. Rangampet-517102
 COMPUTER SCIENCE AND ENGINEERING

 S
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Name of the Topic
N
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UNIT-I: COMPUTER ARITHMETIC,REGISTER TRANSFER AND MICROOPERATIONS
1. Micro Programmed Control: Control memory,
2. , Address sequencing
3. Design of control unit,

4. Hardwired control
5. Micro programmed control
6. Input-Output Organization: Peripheral devices,

7. Input-Output interface
8. Modes of transfer
9. Priority interrupt Daisy chaining priority
10 Parallel priority interrupt
11 Priority encoder
12 Direct Memory Access
13 Input-Output Processor CPU-IOP communication
14. PCI Express - PCI physical and logical architecture

 Micro Programmed Control: Control Memory

 The control unit in a digital computer initiates sequences of microoperations
 The complexity of the digital system is derived form the number of sequences that are performed
 When the control signals are generated by hardware, it is hardwired
 In a bus-oriented system, the control signals that specify microoperations are groups of bits that select the paths in
multiplexers, decoders, and ALUs.
 The control unit initiates a series of sequential steps of microoperations
 The control variables can be represented by a string of 1‟s and 0‟s called a control word

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 A microprogrammed control unit is a control unit whose binary control variables are stored in memory
 A sequence of microinstructions constitutes a microprogram
 The control memory can be a read-only memory
 Dynamic microprogramming permits a microprogram to be loaded and uses a writable control memory
 A computer with a microprogrammed control unit will have two separate memories: a main memory and a control
memory
 The microprogram consists of microinstructions that specify various internal control signals for execution of register
microoperations
 These microinstructions generate the microoperations to:
 fetch the instruction from main memory
 evaluate the effective address
 execute the operation
 return control to the fetch phase for the next instruction
 The control memory address register specifies the address of the microinstruction
 The control data register holds the microinstruction read from memory
 The microinstruction contains a control word that specifies one or more microoperations for the data processor
 The location for the next microinstruction may, or may not be the next in sequence
 Some bits of the present microinstruction control the generation of the address of the next microinstruction
 The next address may also be a function of external input conditions
 While the microoperations are being executed, the next address is computed in the next address generator circuit
(sequencer) and then transferred into the CAR to read the next microinstructions
 Typical functions of a sequencer are:
 incrementing the CAR by one
 loading into the CAR and address from control memory
 transferring an external address
 loading an initial address to start the control operations
 A clock is applied to the CAR and the control word and next-address
 information are taken directly from the control memory
 The address value is the input for the ROM and the control work is the output
 No read signal is required for the ROM as in a RAM

 The main advantage of the microprogrammed control is that once the hardware configuration is established, there
should be no need for h/w or wiring changes
 To establish a different control sequence, specify a different set of microinstructions for control memory
 Address Sequencing
 Microinstructions are stored in control memory in groups, with each group specifying a routine
 Each computer instruction has its own microprogram routine to generate the microoperations
 The hardware that controls the address sequencing of the control memory must be capable of sequencing the
microinstructions within a routine and be able to branch from one routine to another
 Steps the control must undergo during the execution of a single computer instruction:
 Load an initial address into the CAR when power is turned on in the computer. This address is usually the address of
the first microinstruction that activates the instruction fetch routine – IR holds instruction
 The control memory then goes through the routine to determine the effective address of the operand – AR holds
operand address
 The next step is to generate the microoperations that execute the instruction by considering the opcode and applying
a mapping
 After execution, control must return to the fetch routine by executing an unconditional branch
 The microinstruction in control memory contains a set of bits to initiate microoperations in computer registers and
other bits to specify the method by which the next address is obtained

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 Conditional branching is obtained by using part of the microinstruction to select a specific status bit in order to
determine its condition
 The status conditions are special bits in the system that provide parameter information such as the carry-out of an
adder, the sign bit of a number, the mode bits of an instruction, and i/o status conditions
 The status bits, together with the field in the microinstruction that specifies a branch address, control the branch
logic
 The branch logic tests the condition, if met then branches, otherwise, increments the CAR
 If there are 8 status bit conditions, then 3 bits in the microinstruction are used to specify the condition and provide
the selection variables for the multiplexer


memory into the CAR
 A special type of branch exists when a microinstruction specifies a branch to the first word in control memory where
a microprogram routine is located
 The status bits for this type of branch are the bits in the opcode
 Assume an opcode of four bits and a control memory of 128 locations
 The mapping process converts the 4-bit opcode to a 7-bit address for control memory
 This provides for each computer instruction a microprogram routine with a capacity of four microinstructions

 Subroutines are programs that are used by other routines to accomplish a particular task and can be called from any
point within the main body of the microprogram
 Frequently many microprograms contain identical section of code
 Microinstructions can be saved by employing subroutines that use common sections of microcode
 Microprograms that use subroutines must have a provisions for storing the return address during a subroutine call
and restoring the address during a subroutine return
 A subroutine register is used as the source and destination for the addresses

Control Unit is the part of the computer’s central processing unit (CPU), which directs the operation of the processor. It
was included as part of the Von Neumann Architecture by John von Neumann. It is the responsibility of the Control Unit
to tell the computer’s memory, arithmetic/logic unit and input and output devices how to respond to the instructions that
have been sent to the processor. It fetches internal instructions of the programs from the main memory to the processor
instruction register, and based on this register contents, the control unit generates a control signal that supervises the
execution of these instructions.
A control unit works by receiving input information to which it converts into control signals, which are t hen sent to the
central processor. The computer’s processor then tells the attached hardware what operations to perform. The functions
that a control unit performs are dependent on the type of CPU because the architecture of CPU varies from manufacturer
to manufacturer. Examples of devices that require a CU are:
 Control Processing Units(CPUs)
 Graphics Processing Units(GPUs)

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Functions of the Control Unit –

1. It coordinates the sequence of data movements into, out of, and between a processor’s many sub -units.
2. It interprets instructions.
3. It controls data flow inside the processor.
4. It receives external instructions or commands to which it converts to sequence of control signals.
5. It controls many execution units(i.e. ALU, data buffers and registers) contained within a CPU.
6. It also handles multiple tasks, such as fetching, decoding, execution handling and storing results.
Types of Control Unit –
There are two types of control units: Hardwired control unit and Microprogrammable control unit.
1. Hardwired Control Unit –
In the Hardwired control unit, the control signals that are important for instruction execution control are generated by
specially designed hardware logical circuits, in which we can not modify the signal generation method without
physical change of the circuit structure. The operation code of an instruction contains the basic data for control signal
generation. In the instruction decoder, the operation code is decoded. The instruction decoder constitutes a set of
many decoders that decode different fields of the instruction opcode.
As a result, few output lines going out from the instruction decoder obtains active signal values. These output lines
are connected to the inputs of the matrix that generates control signals for executive units of the computer. This
matrix implements logical combinations of the decoded signals from the instruction opcode with the outputs from the
matrix that generates signals representing consecutive control unit states and with signals coming from the outside of
the processor, e.g. interrupt signals. The matrices are built in a similar way as a programmable logic arrays.

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Control signals for an instruction execution have to be generated not in a single time point but during the entire time
interval that corresponds to the instruction execution cycle. Following the structure of this cycle, the suitable sequence
of internal states is organized in the control unit.
A number of signals generated by the control signal generator matrix are sent back to inputs of the next control state
generator matrix. This matrix combines these signals with the timing signals, which are generated by the timing unit
based on the rectangular patterns usually supplied by the quartz generator. When a new instruction arrives at the
control unit, the control units is in the initial state of new instruction fetching. Instruction decoding allows the control
unit enters the first state relating execution of the new instruction, which lasts as long as the timing signals and other
input signals as flags and state information of the computer remain unaltered. A change of any of the earlier
mentioned signals stimulates the change of the control unit state.
This causes that a new respective input is generated for the control signal generator matrix. When an exte rnal signal
appears, (e.g. an interrupt) the control unit takes entry into a next control state that is the state concerned with the
reaction to this external signal (e.g. interrupt processing). The values of flags and state variables of the computer are
used to select suitable states for the instruction execution cycle.
The last states in the cycle are control states that commence fetching the next instruction of the program: sending the
program counter content to the main memory address buffer register and next, reading the instruction word to the
instruction register of computer. When the ongoing instruction is the stop instruction that ends program execution, the
control unit enters an operating system state, in which it waits for a next user directive.
2. Microprogrammable control unit –
The fundamental difference between these unit structures and the structure of the hardwired control unit is the
existence of the control store that is used for storing words containing encoded control signals mandatory for
instruction execution.
In microprogrammed control units, subsequent instruction words are fetched into the instruction register in a normal
way. However, the operation code of each instruction is not directly decoded to enable immediate control signal
generation but it comprises the initial address of a microprogram contained in the control store.

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 With a single-level control store:
In this, the instruction opcode from the instruction register is sent to the control store address register. Based on
this address, the first microinstruction of a microprogram that interprets execution of this instruction is read to the
microinstruction register. This microinstruction contains in its operation part encoded control signals, normally as
few bit fields. In a set microinstruction field decoders, the fields are decoded. The microinstruction also contains
the address of the next microinstruction of the given instruction microprogram and a control field used to control
activities of the microinstruction address generator.

The last mentioned field decides the addressing mode (addressing operation) to be applied to the address
embedded in the ongoing microinstruction. In microinstructions along with conditional addressing mode, this
address is refined by using the processor condition flags that represent the status of computations in the current
program. The last microinstruction in the instruction of the given microprogram is the microinstruction that
fetches the next instruction from the main memory to the instruction register.
 With a two-level control store:
In this, in a control unit with a two-level control store, besides the control memory for microinstructions, a nano -
instruction memory is included. In such a control unit, microinstructions do not contain encoded con trol signals.
The operation part of microinstructions contains the address of the word in the nano -instruction memory, which
contains encoded control signals. The nano-instruction memory contains all combinations of control signals that
appear in microprograms that interpret the complete instruction set of a given computer, written once in the form
of nano-instructions.

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In this way, unnecessary storing of the same operation parts of microinstructions is avoided. In this case,
microinstruction word can be much shorter than with the single level control store. It gives a much smaller size in
bits of the microinstruction memory and, as a result, a much smaller size of the entire control memory. The
microinstruction memory contains the control for selection of consecutive microinstructions, while those control
signals are generated at the basis of nano-instructions. In nano-instructions, control signals are frequently
encoded using 1 bit/ 1 signal method that eliminates decoding.

Peripheral Devices
Input or output devices that are connected to computer are called peripheral devices. These devices are designed to read
information into or out of the memory unit upon command from the CPU and are considered to be the part of computer
system. These devices are also called peripherals.
For example: Keyboards, display units and printers are common peripheral devices.
There are three types of peripherals:
1. Input peripherals : Allows user input, from the outside world to the computer. Example:
Keyboard, Mouse etc.
2. Output peripherals: Allows information output, from the computer to the outside world.
Example: Printer, Monitor etc
3. Input-Output peripherals: Allows both input(from outised world to computer) as well as,
output(from computer to the outside world). Example: Touch screen etc.
Interfaces
Interface is a shared boundary btween two separate components of the computer system which can be used to attach two or
more components to the system for communication purposes.
There are two types of interface:
1. CPU Inteface
2. I/O Interface
Let's understand the I/O Interface in details,

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Input-Output Interface
Peripherals connected to a computer need special communication links for interfacing with CPU. In computer system, there
are special hardware components between the CPU and peripherals to controlor manage the input-output transfers. These
components are called input-output interface units because they provide communication links between processor bus and
peripherals. They provide a method for transferring information between internal system and input-output devices.
Asynchronous Data Transfer
We know that, the internal operations in individual unit of digital system are synchronized by means of clock pulse, means
clock pulse is given to all registers within a unit, and all data transfer among internal registers occur simultaneously during
occurrence of clock pulse. Now, suppose any two units of digital system are designed independently such as CPU and I/O
interface. And if the registers in the interface(I/O interface) share a common clock with CPU registers, then transfer between
the two units is said to be synchronous. But in most cases, the internal timing in each unit is independent from each other in
such a way that each uses its own private clock for its internal registers. In that case, the two units are said to be
asynchronous to each other, and if data transfer occur between them this data transfer is said to be Asynchronous Data
Transfer.But, the Asynchronous Data Transfer between two independent units requires that control signals be transmitted
between the communicating units so that the time can be indicated at which they send data. This asynchronous way of data
transfer can be achieved by two methods:
1. One way is by means of strobe pulse which is supplied by one of the units to other unit. When transfer has to occur. This
method is known as “Strobe Control”.2. Another method commonly used is to accompany each data item being transferred
with a control signal that indicates the presence of data in the bus.The unit receiving the data item responds with another
signal to acknowledge receipt of the data.This method of data transfer between two independent units is said to be
“Handshaking”. The strobe pulse and handshaking method of asynchronous data transfer are not restricted to I/O transfer.In
fact, they are used extensively on numerous occasion requiring transfer of data between two independent units.So, here we
consider the transmitting unit as source and receiving unit as destination. As an example: The CPU, is the source during an
output or write transfer and is the destination unit during input or read transfer. And thus, the sequence of control during an
asynchronous transfer depends on whether the transfer is initiated by the source or by the destination. So, while discussing
each way of data transfer asynchronously we see the sequence of control in both terms when it is initiated by source or when
it is initiated by destination.In this way, each way of data transfer, can be further divided into parts, source initiated and
destination initiated. We can also specify, asynchronous transfer between two independent units by means of a timing
diagram that shows the timing relationship that exists between the control and the data buses.

 The daisy-chaining
 method of establishing priority consists of a serial connection of all devices that request an interrupt.

The daisy-chaining method of creating priority includes a serial connection of all devices that request an interrupt. The device
with the highest priority is located in the first position, followed by lower-priority devices up to the device with the lowest
priority, which is situated last in the chain. This technique of connection between three devices and the CPU.
The interrupt request line is average to all devices and design a wired logic connection. If some device has its interrupt signal
in the low-level state, the interrupt line goes to the low-level state and enables the interrupt input in the CPU. When no
interrupts are pending, the interrupt line continues in the high-level state and no interrupts are identified by the CPU. This is
similar to a negative logic OR operation.

The CPU responds to an interrupt request by enabling the interrupt to acknowledge the line. This signal is acknowledged by
device 1 at its PI (priority in) input. The acknowledge signal passes on to the next device through the PO (priority out) output
only if device 1 is not requesting an interrupt.
If device 1 has a pending interrupt, it blocks the acknowledge signal from the next device by locating a 0 in the PO output. It
then proceeds to insert its interrupt vector address (VAD) into the data bus for the CPU to use during the interrupt cycle.

A device with a 0 in its PI input generates a 0 in its PO output to inform the next-lower-priority device that the acknowledged
signal has been blocked. A device that is requesting an interrupt and has a 1 in its PI input will intercept the acknowledge
signal by placing a 0 in its PO output.

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If the device does not have pending interrupts, it transmits the acknowledge signal to the next device by placing a 1 in its PO
output. Thus the device with PI = 1 and PO = 0 is the one with the highest priority that is requesting an interrupt, and this
device places its VAD on the data bus.
The daisy chain arrangement provides the highest priority to the device that receives the interrupt acknowledge signal from
the CPU. The farther the device is from the first position, the lower is its priority.
It displays the internal logic that should be included within each device when linked in the daisy-chaining scheme. The
device sets its RF flip-flop when it needs to interrupt the CPU. The output of the RF flip-flop goes through an open-collector
inverter, a circuit that supports the wired logic for the common interrupt line.

Parallel Priority Interrupt

 The parallel priority interrupt method uses a register whose bits are set separately by the interrupt signal from each
device.

 Priority is established according to the position of the bits in the register.

 In addition to the interrupt register, the circuit may include a mask register whose purpose is to control the status of
each interrupt request.

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 The mask register can be programmed to disable lower-priority interrupts while a higher-priority device is being
serviced.

 It can also provide a facility that allows a high-priority device to interrupt the CPU while a lower-priority device is
being serviced.

 The priority logic for a system of four interrupt sources is shown in Fig. 14.

 It consists of an interrupt register whose individual bits are set by external conditions and cleared by program
instructions.

 The magnetic disk, being a high-speed device, is given the highest priority. The printer has the next priority,
followed by a character reader and a keyboard.

 The mask register has the same number of bits as the interrupt register. By means of program instructions, it is
possible to set or reset any bit in the mask register.

 Each interrupt bit and its corresponding mask bit are applied to an AND gate to produce the four inputs to a
priority encoder.

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 In this way an interrupt is recognized only if its corresponding mask bit is set to 1 by the program. The priority
encoder generates two bits of the vector address, which is transferred to the CPU.

 Another output from the encoder sets an interrupt status flip-flop lST when an interrupt that is not masked occurs.
The interrupt enable flip-flop lEN can be set or cleared by the program to provide an overall control over the
interrupt system.

 The outputs of IST ANDed with IEN provide a common interrupt signal for the CPU.

 The interrupt acknowledge INTACK signal from the CPU enables the bus buffers in the output register and a
vector address VAD is placed into the data bus.

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Direct Memory Access (DMA)

 The transfer of data between a fast storage device such as magnetic disk and memory is often limited by the speed
of the CPU.

 Removing the CPU from the path and letting the peripheral device manage the memory buses directly

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 The data formats of peripheral devices differ from memory and CPU data formats. The IOP must structure data
words from many different sources.

 For example, it may be necessary to take four bytes from an input device and pack them into one 32-bit word
before the transfer to memory.

 Data are gathered in the IOP at the device rate and bit capacity while the CPU is executing its own program.

 After the input data are assembled into a memory word, they are transferred from IOP directly into memory by
"stealing" one memory cycle from the CPU.

 Similarly, an output word transferred from memory to the lOP is directed from the IOP to the output device at the
device rate and bit capacity.

 The communication between the IOP and the devices attached to it is similar to the program control method of
transfer. Communication with the memory is similar to the direct memory access method.

 The way by which the CPU and IOP communicate depends on the level of sophistication included in the system.

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 In very-large-scale computers, each processor is independent of all others and any one processor can initiate an
operation. In most computer systems, the CPU is the master while the IOP is a slave processor.

 The CPU is assigned the task of initiating all operations, but 110 instructions are executed in the IOP.

 CPU instructions provide operations to start an 110 transfer and also to test 110 status conditions needed for
making decisions on various 110 activities.

 The IOP, in turn, typically asks for CPU attention by means of an interrupt.

 It also responds to CPU requests by placing a status word in a prescribed location in memory to be examined later
by a CPU program.

 When an 110 operation is desired, the CPU informs the IOP where to find the 110 program and then leaves the
transfer details to the IOP.

 Instructions that are read from memory by an IOP are sometimes called commands, to distinguish them from
instructions that are read by the CPU. Otherwise, an instruction and a command have similar functions.

 Commands are prepared by experienced programmers and are stored in memory. The command words constitute
the program for the IOP.

 The CPU informs the IOP where to find the commands in memory when it is time to execute the 110 program.

CPU-IOP Communication

 The communication between CPU and IOP may take different forms, depending on the particular computer
considered.

 In most cases the memory unit acts as a message center where each processor leaves information for the other.

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 To appreciate the operation of a typical IOP, we will illustrate by a specific example the method by which the
CPU and IOP communicate.

 This is a simplified example that omits many operating details in order to provide an overview of basic concepts.

 The sequence of operations may be carried out as shown in the flowchart of Fig. 20.

 The CPU sends an instruction to test the IOP path.

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 The IOP responds by inserting a status word in memory for the CPU to check.

 The bits of the status word indicate the condition of the IOP and I/O device, such as IOP overload condition,
device busy with another transfer, or device ready for I/O transfer.

 The CPU refers to the status word in memory to decide what to do next. If all is in order, the CPU sends the
instruction to start I/O transfer.

 The memory address received with this instruction tells the IOP where to find its program.

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 The CPU can now continue with another program while the IOP is busy with the I/O program. Both programs refer
to memory by means of DMA transfer.

 When the IOP terminates the execution of its program, it sends an interrupt request to the CPU. The CPU responds
to the interrupt by issuing an instruction to read the status from the IOP.

 The IOP responds by placing the contents of its status report into a specified memory location. The status word
indicates whether the transfer has been completed or if any errors occurred during the transfer.

 From inspection of the bits in the status word, the CPU determines if the I/O operation was completed satisfactorily
without errors.

 The IOP takes care of all data transfers between several I/O units and the memory while the CPU is processing
another program.

 The IOP and CPU are competing for the use of memory, so the number of devices that can be in operation is
limited by the access time of the memory.

 It is not possible to saturate the memory by I/O devices in most systems, as the speed of most devices is much
slower than the CPU.

 However, some very fast units, such as magnetic disks, can use an appreciable number of the available memory
cycles.

 In that case, the speed of the CPU may deteriorate because it will often have to wait for the IOP to conduct memory
transfers.

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