Unit -3

BJT and MOSFET

Introduction
➢ Transistors was invented by Shockley, Bardeen, and Brattain, 1949 Bell Telephone
Laboratories
➢ BJT is a three terminal device
➢ BJT is a bipolar device having both majority and minority carriers.
➢ The term bipolar refers to the fact that both electrons and holes are involved in the operation
of a BJT.
➢ BJT is acurrent control device i.e. output current is controlled by input current.
➢ It is smaller and hence, light in weight.
➢ It can be fabricated with Si , Ge and GaAs.
Physical structure of bipolar junction transistor (BJT)
Both electrons and holes participate in the conduction process for bipolar devices.
BJT consists of two pn junctions constructed in a special way and connected in series,
back to back.
The transistor is a three-terminal device with emitter, base and collector terminals.
➢ The emitter is a medium-sized, heavily doped region whose primary purpose is to
inject its majority carriers (electrons for n-type, holes for p-type), through the base
and into the collector.
➢ The collector is a thick, lightly doped region designed to collect the majority carriers
injected from the emitter.
➢ The base is a thin, medium doped layer whose primary purpose is to provide the
control of the current between the emitter and collector.
From the physical structure, BJTs can be divided into two groups: npn and pnp
transistors.
 The arrow in the circuit symbol always showing the direction of “conventional current
flow” between the base terminal and its emitter terminal.

Modes of operation of transistor

The application of suitable dc voltages across the transistor terminals is called biasing.
Each junction of a transistor may be forward biased or reverse biased
independently.These are following four different ways of biasing a transistor ,which is also
known as modes of transistor operation.
S.No Mode Emitter-base Collector-base Application
Junction Junction
1. Forward-Active Forward Reverse High gain
amplifier
2. Saturation Forward Forward On Switch

3. Cut-off Reverse Reverse Off Switch

4. Reverse ACTIVE Reverse Reverse Low gain

Amplifier

Unbiased transistor
➢ A transistor with three terminals left open is called an unbiased transistor or open
circuited transistor.
➢ Under these conditions diffusion of free electrons across the junction produces two
depletion layers.
➢ Since emitter is heavily doped than base and collector, the emitter depletion width is
smaller than collector base depletion width.

Working of Transistor in the Active Mode

➢ To bias transistor in the active mode, we need to forward bias the emitter base
junction and reverse bias the collector base junction.
➢ Forward biasing the emitter base junction will reduce emitter base junction voltage
and reverse biasing of collector base junction will increase collector base junction
barrier potential. Because of the forward bias on the EBJ,charges can flow across
this junction giving rise to IE. This current is primarily electrons that are injected from
n to p.
➢ The electrons Injected in the base diffuse across the thin base region towards the
collector. Some of the e-recombine in the base, but this region is manufactured to be
thin and lightly doped compared to the emitter so this recombination is kept small.

➢ A small base current IB is present largely due to recombination in the base with the
small amount of injected holes from the base to the emitter.
➢ The electrons that reach the reverse-biased CBJ encounter a large electric field. This
Electric field sweeps them into the collector forming the collector current I C as shown
in Fig. above.

From KCL in the circuit of Fig. :

IE = IB+ IC

The collector current is comprised of two currents:

IC=IC majority + ICO minority
The minority current is called the leakage current and is given by the symbol ICO(ICO
current with emitter terminal open).

Early Effect, or Base-Width Modulation

Under normal operation the emitter-base junction is forward biased, the collector-base
junction is reverse-biased. If the reverse bias across the collector-base junction
increases, so too will the width of the depletion region for this junction —i.e. the depletion
region will extend more into the collector and, in particular, the base. This is illustrated for
a npn device in Fig. . Note that the base is already narrow (~ 1um) to reduce
recombination. This decrease in the effective width of the base region due to
increasing reverse bias of the collector-base junction is termed the Early effect or
base-width modulation and has following consequences:
1.α increases with increasing |VCB| because there is less chance for recombination to
occur in the base region if it is narrower.

2. At high values of |VCB| the depletion region associated with the collector-base
junction can extend right across to the emitter-base junction. This effect is termed
punch-through-a large current flows because the emitter-base energy barrier drops, and
transistor action ceases.

Transistor Configuration
➢ Depending upon the terminals which are used as a common terminal to the input and
output terminals, the transistors can be connected in the following three different
configuration.
1. Common base configuration
2. Common emitter configuration
3. Common collector configuration

1. Common Base configuration

➢ In this configuration base terminal is conncted as a common terminal.
➢ In this circuit the emitter terminal of the transistor serves as the input, the collector
the output, and the base is connected to ground, or "common"
➢ There is no phase reversal between the input and output signals.
1. DC current gain(αdc or hFB)
In the dc mode the levels of IC and IE due to the majority carriers are related by a quantity
called alpha and defined by the following equation:

`
𝑰𝒄
𝛂𝒅𝒄 =
𝑰𝑬
Ideally: α = 1
Practically: α is between 0.9 and 0.998Type equation here.
2. Ac current gain(αac or hfb)
The ac alpha is formally called the common-base, short-circuit, amplification factor.

∆𝑰𝒄
𝛂𝒂𝒄 = ∆𝑰𝒄 ⎜𝑽𝑪𝑩 𝒄𝒐𝒏𝒔𝒕𝒂𝒏𝒕
𝛂𝒂𝒄 = ∆𝑰𝑬 ⎜𝑽𝑪𝑩 𝒄𝒐𝒏𝒔𝒕𝒂𝒏𝒕
∆𝑰𝑬

3. Current equation

IC=IC majority + ICO minority

𝑰𝒄 = 𝜶𝑰𝑬 + 𝑰𝑪𝑩𝑶
ICBO- Leakage current from collector to base in CB configuration when emitter terminal is
open

Input Characterstics

➢ It is plotted between input current(IE) and input voltage(VBE) when output voltage is
constant.
➢ Input characteristics are like a normal forward biased diode.
➢ In the above fig, below the cut in voltage emitter current IE is very small.
➢ After the cut in voltage, the emitter current IE increases rapidly with small increase in
VBE. this indicates input resistance of common base is very small.

𝑉𝐵𝐸
𝑅𝑖 =
𝐼𝐸

➢ With increase in VCB, the curve shift upwards or becomes vertical. Hence input
resistance decreases.
Output charactersticsIt is the curve plotted between output current(IC) and output
voltage(VCB) when input current(IE) is constant.
The output characterstics has three basic regions:

(i) Cut off Region: The region below the curve IE=0 is known as cut off region where
the collector current is nearly zero. In this region emitter base junction and collector
base junction are reverse biased.

𝐈𝐜 = 𝛂𝐈𝐄 + 𝐈𝐂𝐁𝐎
IE=0
IC=ICBO
Saturation Region:In this emitter base junction and base collector junction both are
forward biased. It is defined as that region of the characteristics to the left of VCB= 0
V.Here, IC is independent of IE. IC decreases rapidly as VCB becomes more negative.
(ii) Active Region: For the operation in active region the emitter base junction is
forward biased and collector base junction is reverse biased. In this region collector
current IC is approximately equal to IE and transistor works as an amplifier.

2. Common Emitter Configuration

➢ In this configuration emitter terminal is conncted as a common terminal.
➢ In this circuit the base terminal of the transistor serves as the input, the collector the
output, and the emitter is connected to ground, or "common" .
➢ The most frequently encountered transistor configuration appears in Fig. for the
transistors used as an amplifier.
➢ There is a 180⁰ phase reversal between the input and output signals with the voltage
gain having a negative value.
(I) DC current gain(β,hFE)
 represents the amplification factor of a transistor. ( is sometimes referred to as
hfe, a term used in transistor modeling calculations)

`
𝑰𝒄
𝛃𝒅𝒄 =
𝑰𝑩

Ideally: 𝛃 = 100
Practically: 𝛃 is between 100 and 300
(II) Ac current gain(𝛃 ac or hfe)
The ac beta is formally called the common-emitter, forward current, amplification
factor.

∆𝑰𝒄
𝛃𝒂𝒄 = ∆𝑰𝒄 ⎜𝑽𝑪𝑬 𝒄𝒐𝒏𝒔𝒕𝒂𝒏𝒕
𝛂𝒂𝒄 = ∆𝑰𝑩 ⎜𝑽𝑪𝑩 𝒄𝒐𝒏𝒔𝒕𝒂𝒏𝒕
∆𝑰𝑬

(III) Current equation

IC=IC majority + ICO minority

𝑰𝒄 = 𝜶𝑰𝑬 + 𝑰𝑪𝑩𝑶

IE = IB+ IC

Therefore, 𝑰𝒄 = 𝜶(𝑰𝑩 + 𝑰𝑪 ) + 𝑰𝑪𝑩𝑶

 𝜶𝑰𝑩 𝑰𝑪𝑩𝑶
Rearranging yields, 𝑰𝒄 = +
𝟏−𝜶 𝟏−𝜶

𝑰𝒄 = 𝜷𝑰𝑩 + 𝑰𝑪𝑬𝑶

𝑰𝑪𝑩𝑶
Where, 𝑰𝑪𝑬𝑶 =
𝟏−𝜶
ICEO- Leakage current from collector to base in CE configuration when bse terminal is
open

IC =βIB

and since IE = IC + IB
=βIB + IB
we have
IE =( 1+β)IB
Input Characterstics

➢ It is plotted between input current(IB) and input voltage(VBE) when output voltage is
constant(VCE).
➢ Input characteristics are like a normal forward biased diode.
➢ In the above fig, below the cut in voltage emitter current IB is very small.
➢ After the cut in voltage, the emitter current IE increases rapidly with small increase in
VBE.

𝑉𝐵𝐸
𝑅𝑖 =
𝐼𝐵
➢ With higher values of VCE collector gathers slightly more electrons and therefore base
current reduces. This effect is known as Early effect. This indicates input resistance
of common emitter configuration is more than common base.

Output characterstics

It is the curve plotted between output current(IC) and output voltage(VCE) when input
current(IB) is constant.

The output characterstics has three basic regions:

(iii) Cut off Region: In this region emitter base junction and collector base junction are
reverse biased. Hence, the base current is approximately equal to zero i.e. I B=0.
But collector current is eual to the current flowing from collector to emitter in
reverse direction.
𝑰𝒄 = 𝜷𝑰𝑩 + 𝑰𝑪𝑬𝑶
IB=0
IC=ICEO
(iv) Saturation Region:In this emitter base junction and base collector junction both
are forward biased. Here, IC is independent of IB.
(v) Active Region: For the operation in active region the emitter base junction is
forward biased and collector base junction is reverse biased. In this region collector
current IC mainly depends on IB and transistor works as an amplifier.

𝐈𝒄 = 𝛃𝐈𝑩
3. Common Collector Configuration(Emitter Follower)
➢ In this configuration collector terminal is conncted as a common terminal.
➢ In this circuit the base terminal of the transistor serves as the input, the emitter the
output, and the collector is connected to ground, or "common" .
➢ The common-collector configuration is used primarily for impedance-matching
purposes since it has a high input impedance and low output impedance, opposite to
that of the common-base and common-emitter configurations.
➢ There is no phase reversal between the input and output signals.

I) DC current gain(γ)
𝑰𝑬
`
𝜸𝒅𝒄 =
𝑰𝐵
II) Ac current gain(γac)

∆𝑰𝑬
𝜸𝒂𝒄 =
∆𝑰𝐵

Relationship between α,β and γ

We Know IE = IB+ IC

Divide above equation by IC, we get

𝑰𝑬 𝑰𝑩
= +𝟏
𝑰𝑪 𝑰𝑪
Where,
𝑰𝒄 𝑰𝒄
𝛃𝒅𝒄 = and 𝛂𝒅𝒄 =
𝑰𝑩 𝑰𝑬

Therefore,
𝟏 𝟏
= +𝟏
𝜶 𝜷

𝜷 𝜶
𝜶= 𝜷=
𝜷+𝟏 𝟏−𝜶
Similarly,
IE = IB+ IC

Divide above equation by IB, we get

𝑰𝑬 𝑰𝑪
= 𝟏+
𝑰𝑩 𝑰𝑩
Where,
𝑰𝒄 𝑰𝑬
𝛃𝒅𝒄 = and 𝛄𝒅𝒄 =
𝑰𝑩 𝑰𝑩

Therefore,

𝜸=𝜷+𝟏 𝟏
𝜸=
𝟏−𝜶

Biasing
The process of giving proper supply voltages and resistances for obtaining the desired
Q-Point is called Biasing. The circuits used for getting the desired and proper operating
point are known as biasing circuits. To establish the operating point in the middle of the
active region biasing is required for transistors to be used as an amplifier.

Need of Biasing
1. In order to produce distortion free output in amplifier circuits, the supply voltages and
resistances establish a set of dc voltage VCEQ and ICQ to operate the transistor in
the active region. These voltages and currents are called quiescent values which
determine the operating point or Q-point for the transistor.Often, Q-point is established
near the center of active region of transistor characteristic to allow similar signal
swings in positive and negative directions.
NOTE
➢ For analog circuit operation, the Q-point is placed so the transistor stays in active
mode (does not shift to operation in the saturation region or cut-off region) when
input is applied.
➢ For digital operation, the Q-point is placed so the transistor does the contrary -
switches from "on" to "off" state.
2. Q-point should be stable. In particular, it should be insensitive to variations in transistor
parameters (for example, should not shift if transistor is replaced by another of the
same type), variations in temperature, variations in power supply voltage and so forth.
3. The circuit must be practical: easily implemented and cost-effective.

DC Load Line and Q point

The line drawn using load as a reference, while operating under static or dc conditions
without an application of ac signal is known as load line. The dc load line is drawn on the
output characterstic curves.

DC Load Line for Common Emitter Configuration

n the output circuit, the load equation can be written as

VCE = VCC- IC RC

This equation involves two unknown VCE and IC and therefore can not be solved. To solve this equation output
characteristic ( ICvs VCE) is used.
Rearranging above equation,
𝑽𝑪𝑬 𝑽𝑪𝑪
+𝑰𝑪 = −
𝑹𝑪 𝑹𝑪
The load line equation is same as straight line equation

Y=mX+C
Where, slope
1
𝑚=−
𝑅𝐶
To draw load line, we have to find saturation current and the cutoff voltage. After plotting
these values on the vertical and the horizontal axes, a line is drawn joining these two points,
which represents DC load line. It represents all possible combinations of the collector current
Ic and the collector voltage Vc (or Vce) for the given load resistor Rc.

Saturation point The point at which the load line intersects the characteristic
curve near the collector current axis is referred to as the saturation point. At this
point of time, the current through the transistor is maximum and the voltage across
collector is minimum for a given value of load.
Therefore saturation current is
Ic (sat) =Vcc/Rc when VCE=0
 Cutoff point The point where the load line intersects the cutoff region of the
collector curves is referred as the cutoff point (i.e. end of load line). At this point,
collector current is approximately zero and emitter is grounded for fixed bias circuit.
Therefore,
Vce (cut off) =Vcc when IC=0

The line drawn using these two points on output characterstics is known as dc load
line shown in fig

Intersection of dc load line with output characterstics yields various Quiscient points(Q
point) or operating points.

Bias Stablization
The stability of a system is a measure of the sensitivity of a network to variations in
its parameters.The process of making Q-point independent of temperature variations and
transistor parameters is known as stabilization. Stabilization of operating point is
necessary due to
➢ Temperature dependence of IC
➢ Variations in the transistor parameter of same type such as β.
➢ Thermal runaway
Temperature dependence of IC & Thermal runaway

➢ ICBO is strong function of temperature. A rise of 10oC doubles the I CBO and IC will
increase ( β+1) times of ICBO
➢ The flow of IC produce heat within the transistor and raises the transistor temperature
further and therefore, further increase in ICBO
➢ This effect is cumulative and in few seconds, the IC may become large enough to burn
out the transistor.
➢ The self destruction of an unstablized transistor is known as thermal runaway.

Stability Factor
The rate of change collector current IC with respect to the collector leakage current ICBO
at constant β and IB is called stability factor, denoted by S.
For CE configuration IC is given by

Different biasing schemes

1. Fixed Bias
This form of biasing is also called base bias. The single power source is used for
both collector and base of transistor, although separate batteries can also be
used.

Figure Fixed-bias

Using KVL in the base-emitter loop

VCC – IBRB –VBE = 0 ;

IB = (VCC-VBE)/RB
 IC =βIB
Using KVL in the collector-emitter loop
VCC – ICRC –VCE = 0;
VCE = VCC - ICRC
Stability factor
For CE configuration stability factor is given by

For fixed bias

IB = (VCC-VBE)/RB

𝑑𝐼𝐵
Therefore, =0
𝑑𝐼𝐶
So,
S=1+β

Advantages:
➢ Operating point can be shifted easily anywhere in the active region by merely
changing the base resistor (RB).
➢ A very small number of components are required.
Disadvantages:
➢ Poor stabilization
➢ High stability factor(S=1+β because IB is constant so dIB/dIC =0 ), hence prone to
thermal runaway.

2. Emitter-Stabilized Bias Circuit

➢ Adding a resistor (RE) to the emitter circuit stabilizes the bias circuit.
➢ The fixed bias circuit is modified by attaching an external resistor to the
emitter. This resistor introduces negative feedback that stabilizes the Q-
point.
➢ Stability refers to a condition in which the currents and voltages remain
fairly constant over a wide range of temperatures and transistor Beta ()
values.
Fig Emitter-Stabilized Bias Circuit Dc equivalent

For the dc analysis all the capacitors are open circuit.

Using KVL in the base-emitter loop

VCC - IBRB -VBE - IERE = 0

We know,
IE = (1+β)IB
VCC –IBRB- VBE- (1+β)IBRE = 0

and solving for IB gives

𝑉𝑐𝑐 − 𝑉𝐵𝐸
𝐼𝐵 =
𝑅𝐵 + (1 + 𝛽)𝑅𝐸

IC =βIB

Using KVL in the Collector-emitter loop

𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 − 𝑉𝐶𝐸 − 𝐼𝐸 𝑅𝐸 = 0

𝑉𝐶𝐸 = 𝐼𝐶 𝑅𝐶 + 𝑉𝐶𝐸 + 𝐼𝐸 𝑅𝐸 = 0

Stability factor
For the emitter-bias configuration, an analysis of the network will result in

𝑅
I. For 𝑅𝐵 ≫ (𝛽 + 1) above equation will reduce to the following:
𝐸

𝑅
II. For 𝑅𝐵 ≪ 1 the stability factor will be given by:
𝐸

𝑅
III. For 𝑅𝐵 between 1 and 1+𝛽 , the stability factor will be given by:
𝐸

The results reveal that the emitter-bias configuration is quite stable when the ratio RB/RE is as small as possible
and the least stable when the sameratio approaches (1+β).
Merits:
➢ The circuit has the tendency to stabilize operating point against changes in temperature and β-value.
Disadvantages
➢ In addition to the above, RE causes ac feedback which reduces the voltage gain of the amplifier.

Voltage Divider bias

➢ This is the most widely used method to provide biasing and stabilization to a
transistor.
➢ In this form of biasing, R1 and R2 divide the supply voltage VCC and voltage across
R2 provide fixed bias voltage VB at the transistor base.
➢ Also a resistance RE is included in series with the emitter that provides the
stabilization.
 Fig Voltage divider bias Dc equivalent
Exact Analysis
The Thévenin equivalent network for the network to the left of the base terminal can then be found in the
following manner:
Stability Factor

➢ The emitter bias network had its greatest stability when RE>RB. The corresponding
condition is RE > RTh or RTh/RE should be as small as possible. For the voltage-
divider bias configuration, RTh can be much less than the corresponding RB of the
emitter-bias configuration and still have an effective design.

Approximate Analysis

The input section of the voltage divider configuration can be represented by

the network shown in the fig

Input Network

The emitter resistance REis seen as (+1)RE at the input loop.

If this resistance is much higher compared to R2, then the current IB is much
smaller thanI2through R2. This means,
This makes IB to be negligible.Thus I1 through R1 is almost same as the current I2 through R2.
Thus R1 and R2 can be considered as in series.Voltage divider can be applied to find the voltage
across R2 ( VB)

Once VB is determined, VE is calculated as,

After finding VE, IE is calculated as,

Merits:
• Unlike above circuits, only one dc supply is necessary.
• Operating point is almost independent of β variation.
• Operating point stabilized against shift in temperature.
Demerits:
• As β-value is fixed for a given transistor, this relation can be satisfied either by keeping RE
fairly large, or making R1||R2 very low.
• If RE is of large value, high VCC is necessary. This increases cost as well as precautions
necessary while handling.
DC bias with voltage feedback(Collector Feedback)

Input Loop

Applying KVL for Input Loop

If the collector current increases due to increase in temperature or the transistor is replaced by
one with higher , the voltage drop across RC increases.
- So, less VCE and less IB, to compensate increase in Ic i.e., greater stability
Output loop

Neglecting the base current, and applying KVL to the output loop results in,

In this circuit, improved stability is obtained by introducing a feedback path from

collector to base.
Sensitivity of Q point to changes in beta or temperature variations is normally less than
that encountered for the fixed bias or emitter biased configurations.

Small signal Model (AC Model)

• A small signal model is a linear model which is independent of amplitude. It may or may
not have time dependence.
• Consider a BJT with bias voltages VBE and VCC as shown in fig.These produce quiescent
collector and base current IB and IC and device is in forward active region.

 Effect of small signal input voltage applied to BJT

 A small input voltage vi is applied in series with VBE .
 It produces a small variation in base current ib and ic.
 The carrier concentrations in the base of the transistor corresponding to the circuit diagram of small
signal model is shown on next slide.
 Application of small signal voltage vi causes np(0) to increase at the emitter edge of the base this
concentration is shown by dotted lines.
Transconductance

Input Resistance of Small signal model

Output Resistance of Small signal model

Simple Small Signal model of BJT

 Implementing the following relationships into schematic model

ic = βib
The small-signal equivalent circuit of the bipolar transistor in Figure uses this parameter. The parameters in this figure
are also given as phasors. This circuit can also be inserted in the ac equivalent circuit given in Figure .Either equivalent
circuit, Figure may be ued.
Figure BJT small-signal equivalent circuit using the common-emitter current gain. The
ac signal currents and voltages are shown

Steps to Draw Small signal Equivalent

1. Setting all dc sources to zero and replacing them by a short-circuit equivalent
2. Replacing all capacitors by a short-circuit equivalent
3. Removing all elements bypassed by the short-circuit equivalents introduced by steps 1 and 2
4. Redrawing the network in a more convenient and logical form

COMMON-EMITTER AMPLIFIER FIXED-BIAS CONFIGURATION

Figure Common-emitter fixed-bias configuration Figure Network of Figure

following
the removal of the effects of VCC,
C1, and C2.
Figure: Substituting the re model into the network of Fig.

Zi: Figure clearly reveals that

Zo: Recall that the output impedance of any system is defined as the impedance Zo
determined when Vi _ 0. For Fig. , when Vi = 0, Ii =Ib = 0, resulting in an open-
circuit equivalence for the current source.

Av: The resistors ro and RC are in parallel,

Ai: The current gain is determined in the following manner: Applying the current-
divider rule to the input and output circuits,
VOLTAGE-DIVIDER BIAS(CE)

Fig Small signal equivalent of VDB

Av: Since RC and ro are in parallel,

Phase relationship: The fact that Av is a positive number reveals that Vo and Vi
are out of phase for the common-emitter configuration.

EMITTER-FOLLOWER CONFIGURATION
 Small signal equivalent

Phase relationship: The fact that Av is a positive number reveals that Vo and Viare
in phase for the common-collector configuration.

COMMON-BASE CONFIGURATION
Fig: CB configuration Fig : Small Signal Model

Phase relationship: The fact that Av is a positive number reveals that Vo and Vi
are in phase for the common-base configuration.

FET(Field Effect Transistor)

Field Effect Transistor (FET) is a voltage controlled device. i.e. the output characteristics of this
device are controlled by the input voltage and not by the input current.

FET is unipolar device. i.e. the operation of FET depends upon the flow of majority carriers
only. For the FET, an electric field is established by the charges present that will control the
conduction path of the output circuit without the need for direct contact between the controlling
and controlled quantities.

1.Unipolardevice i. e. operation depends on only one type of charge carriers (hor e)

2.Voltage controlled Device (gate voltage controls drain current)
3.Very high input impedance (≈109-1012 Ω)
4.Source and drain are interchangeable in most Low-frequency applications
5.Low Voltage Low Current Operation is possible (Low-power consumption)
6.Less Noisy as Compared to BJT
7.No minority carrier storage (Turn off is faster)
8.Self limiting device
9.Very small in size, occupies very small space in ICs
10.Low voltage low current operation is possible in MOSFETS
11.Zero temperature drift of output is possible
 BJT JFET
Unipolar device (current conduction is Bipolar device (current condition, by both
only due to one type of majority carrier types of carriers, i.e. majority and
either electron or hole). minority-electrons and hole).

BJT is not a symmetrical device FET is a symmetrical device

Voltage controlled device. The current Current controlled device. The current
through the two terminals is controlled by through the two terminals is controlled by
a voltage at the third terminal (gate). a current at the third terminals (base).

Low noise level. High noise level.

High input impedance (due to reverse Low input impedance (due to forward
bias). bias).

Classification of FET
Depletion MOSFET(N-Channel)

Basic Construction

The basic construction of the n-channel depletion-type MOSFET is provided in Fig. A slab of p-
type material is formed from a silicon base and is referred to as the substrate. The source and drain
terminals are connected through metallic contacts to n-doped regions linked by an n-channel as
shown in the figure. The gate is also connected to a metal contact surface but remains insulated
from the n-channel by a very thin silicon dioxide (SiO2) layer. The fact that the SiO2 layer is an
insulating layer reveals the following fact:

There is no direct electrical connection between the gate terminal and the channel of a
MOSFET.It is the insulating layer of SiO2 in the MOSFET construction that accounts for the
very desirable high input impedance of the device.

The insulating layer between the gate and channel has resulted in another name for the device:
insulated gate FET or IGFET, although this label is used less and less in current literature.

Working
Case-1- VGS = 0 V and VDS > 0 the result is an attraction for the positive potential at the
drain by the free electrons of the N-channel and a current similar to that established through the
channel of the JFET.
Case-2- VGS = -ve and VDS > 0 In this case, electrons move towards P-type substrate &
attracts holes from P-type substrate.
Depending on the magnitude of the negative bias established by VGS, a level of recombination
between electrons and holes will occur that will reduce the number of free electrons in the N-
channel available for conduction. The resulting level of drain current is therefore reduced with
increasing negative bias for VGS.

Case-3- VGS = +ve and VDS > 0 For +ve value of VGS , the positive gate will draw
additional electrons (free carriers ) from the p-type substrate due to the reverse leakage current
and established new carriers through the collisions resulting between accelerating particles.
 Transfer and Drain characteristics for an n-channel depletion-type MOSFET

P-Channel Depletion Type MOSFET

Fig: Drain & Transfer Characteristics of P-Channel Depletion type MOSFET

Symbol: Depletion (D) Type MOSFET

 Depletion MOSFET vs Enhancement MOSFET

Depletion MOSFET Enhancement MOSFET

Channel is not present between source and Channel is present between source and drain
drain

It operates in enhancement and depletion It operates only in enhancement mode

mode

Normally ON device Normally OFF device

Symbol of N-channel Symbol of N-channel

Enhancement MOSFET(N-channel)

This MOSFET operates only in the enhancement mode and has no depletion mode. It operates
with large positive gate voltage only. It does not conduct when the gate-source voltage VGS = 0.
This is the reason that it is called normally-off MOSFET. In these MOSFET’s drain current ID
flows only when VGS exceeds VGST [gate-to-source threshold voltage].

N-Channel- the N-channel enhancement type MOSFET consists of a lightly doped P-type
substrate into which two highly doped N-regions are diffused. The absence of a channel between
the two N-doped region.
Working

Case-1- VGS= 0 V If VGS is set at 0 V and a voltage applied between the drain and source of
the device, the absence of an N-channel will result in a current (ID) effectively 0 A.

Case-2- When both VGS > 0 V and VDS> 0 V when both VGS and V DS have been set at
positive voltage greater than 0V., establishing the drain and gate at a positive potential with respect
to the source. As the positive potential is applied between gate & source due to the presence of
SiO2 layer which acts as a dielectric, is attracts the charge carriers (electrons) from substrate. As
VGS increases in magnitude the concentration of electrons near the SiO2 surface increases until
eventually the induced N-type region can support a measurable flow between drain & source,
resulting the formation of inversion layer, this inversion layer. This inversion layer is formed when
a certain gate to source voltage (VGS) is applied. Thus, the minimum value of gate voltage at
which inversion of semiconductor surface takes place is known as threshold voltage (VT).

Since the channel is no-existent with VGS= 0V and “enhanced” by the application of a
positive gate to source voltage. This type of MOSFET is called Enhancement type MOSFET.
Drain and Transfer Characteristics of EMOSFET(N-Channel)

Drain characteristics of an N-channel E-MOSFET are shown in figure. The lowest curve is the
VGST curve. When VGS is lesser than VGST, ID is approximately zero. When VGS is greater than
VGST, the device turns- on and the drain current ID is controlled by the gate voltage. The
characteristic curves have almost vertical and almost horizontal parts. The almost vertical
components of the curves correspond to the ohmic region, and the horizontal components
correspond to the constant current region.

The above Figure shows a typical transconductance curve. The current IDSS at VGS <=0 is very
small, being of the order of a few nano-amperes. When the VGS is made positive, the drain current
ID increases slowly at first, and then much more rapidly with an increase in VGS.

AC Analysis of JFET

FET AC Equivalent Circuit

Now that the important parameters of an ac equivalent circuit have been introduced
and discussed, a model for the FET transistor in the ac domain can be constructed.
The control of Id by Vgs is included as a current source gmVgs connected from drain
to source as shown in Fig. The current source has its arrow pointing from drain to
source to establish a 180° phase shift between output and input voltages as will occur
in actual operation.
 FET ac equivalent circuit.

Transconconductance

Common Source Amplifier

Fig: Small signal model of CS JFET

Av:Voltage gain
Phase Relationship: The negative sign in the resulting equation for Av clearly
reveals a phase shift of 180° between input and output voltages.

Common Drain amplifier(Source Follower)

Fig: Small signal Model

Phase Relationship: Since Av is a positive quantity, Vo and Vi are in phase for the
JFET source-follower configuration.

Common Gate Amplifier

Fig: CG configuration Fig : Small Signal Model

Phase Relationship: The fact that Av is a positive number will result in an in

phase relationship between Vo and Vi for the common-gate configuration.