1.Design suitable circuits to verify Boolean theorems using basic logic gates and verify the outputs.

Tabulation/
Aim/Principle/Appar Calculation
Circuit/Program/ Viva-Voce Record Total
atus required/Procedure & Results
Drawing
20Marks 30Marks 30Marks 10 Marks 10 Marks 100 Marks

INTERNAL EXAMINER EXTERNAL EXAMINER

2.Design a combinational circuit with minimum number of inputs using K map reduction technique for the
given function F = Σm (0, 2, 5, 6, 8, 10, 13, 14).

Aim/Principle/Appa Tabulation/
Calculation
ratus Circuit/Program/ Viva-Voce Record Total
& Results
required/Procedure Drawing
20Marks 40Marks 20Marks 10 Marks 10 Marks 100 Marks

INTERNAL EXAMINER EXTERNAL EXAMINER