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  • Ravi Kukretis Resume

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    SELVAKUMAR S
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    Ravi Kukreti has an M.Tech in Embedded and VLSI from NSIT Delhi with a 7.67 CGPA. He has experience with Truechip Solutions in hardware verification using Verilog and SystemVerilog. His projects include designing an 8b9b encoder and optimizing transistor sizing for CMOS logic circuits. He has skills in Verilog, SystemVerilog, and CAD tools like ELD and Questa Sim. He held a teaching assistant position at NSIT and has published papers on probability implementation and CMOS logic optimization.

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    Ravi Kukreti has an M.Tech in Embedded and VLSI from NSIT Delhi with a 7.67 CGPA. He has experience with Truechip Solutions in hardware verification using Verilog and SystemVerilog. His projects include designing an 8b9b encoder and optimizing transistor sizing for CMOS logic circuits. He has skills in Verilog, SystemVerilog, and CAD tools like ELD and Questa Sim. He held a teaching assistant position at NSIT and has published papers on probability implementation and CMOS logic optimization.

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    2 views1 page

    Ravi Kukretis Resume

    Uploaded by

    SELVAKUMAR S
    Ravi Kukreti has an M.Tech in Embedded and VLSI from NSIT Delhi with a 7.67 CGPA. He has experience with Truechip Solutions in hardware verification using Verilog and SystemVerilog. His projects include designing an 8b9b encoder and optimizing transistor sizing for CMOS logic circuits. He has skills in Verilog, SystemVerilog, and CAD tools like ELD and Questa Sim. He held a teaching assistant position at NSIT and has published papers on probability implementation and CMOS logic optimization.

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    RAVI KUKRETI

    ravik.ev.17@nsit.net.in | 7906305118

    EDUCATION EXPERIENCE
    NSIT (DELHI UNIVERSITY) TRUECHIP SOLUTIONS | TRAINING
    M.TECH IN EMBEDDED AND VLSI Jan 2019 – Apr 2019 | Noida, UP
    Dwarka, New Delhi • Deep learning of hardware descriptive and verification language using Verilog
    Cum. GPA: 7.67 and SystemVerilog. understanding of verification environment using UVM
    methodology.
    GRAPHIC ERA UNIVERSITY
    B.TECH IN ECE
    Dehradun | Cum. GPA: 7.4 PROJECT
    ARMY SCHOOL DEHRADUN DESIGN AND VERIFICATION OF 8B9B ENCODER
    HSC May 2019 – July 2019 | Noida, UP
    CLEMENTTOWN | PERCENTAGE: 71 • Encoding 8bit into 9bit and writing DUT using SystemVerilog.
    • A verification environment is created using UVM methodology to verify the
    ARMY SCHOOL DEHRADUN correct functionality of DUT.
    SSC
    CLEMENTTOWN | PERCENTAGE: 73.2 OPTIMUM TRANSISTOR SIZING OF CMOS LOGIC CIRCUIT USING
    LE THEORY AND APSO ALGORITHM
    Jan 2019 – Apr 2019 | Dwarka, New Delhi
    COURSEWORK • Using LE theory transistor Delays are optimized and with the help of nature
    inspired algorithm i.e APSO iteration on transistor size provide minimum area
    GRADUATE and power, hence improved PDAP.
    Digital Integrated Circuit
    Semiconductor Devices and Memories PROGRAMMABLE CIRCUIT USING MEMRISTOR
    Analog Integrated Circuit Aug 2018 – Dec 2018 | Dwarka, New Delhi
    STA(udemy course) • Memristors are used to develop oscillator circuits, RC phase shift oscillator,
    Processor Design Comparator circuit.
    Device Modelling and Circuit simulation
    • With the help of triggering pulse memristor are used as memory devices
    storing logical bit values.

    SKILLS DESIGN AND IMPLEMENTATION OF 8BIT RISC PROCESSOR


    Sep 2017 – Nov 2017 | Dwarka, New Delhi
    PROGRAMMING
    Verilog • Implementation of various unit such as control unit, data path unit and memory
    SystemVerilog unit with the help of Verilog HDL.
    C basics
    TCL (CLI)
    TOOL RESEARCH
    Vim VLSI DESIGN LAB | HEAD POSTGRAD RESEARCH
    Eldo(Mentor Graphics) Jan 2019 – Apr 2019 | Dwarka, New Delhi
    LT- spice Worked with Dr. Kunwar Singh
    Xillinx • Automation of CMOS transistor sizing and improving PDAP.
    Questa Sim

    ACHIEVEMENTS POSITION OF RESPONSIBILITY


    IEEE Conference resarch paper on NSIT- NEW DELHI | TEACHING ASSISTANTSHIP
    Implementation of Probability Using FIR Aug 2017 – Apr 2019 | Dwarka, New Delhi
    filter.(2014) Teaching Assistantship in Embedded and VLSI labs.
    IEEE resarch paper on Performance
    Optimization of Digital CMOS logic
    circuits using LE theory and APSO.(2019)
    GATE Percentile 98.67(2016)
    GATE Percentile 98.53(2018)

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