M54HC04

M74HC04

HEX INVERTER

. HIGH SPEED

. tPD = 6 ns (TYP.) AT VCC = 5 V

LOW POWER DISSIPATION

. ICC = 1 µA (MAX.) AT TA = 25 °C
HIGH NOISE IMMUNITY

. VNIH = VNIL = 28 % VCC (MIN.)

OUTPUT DRIVE CAPABILITY B1R F1R

. 10 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
(Plastic Package) (Ceramic Package)

. IOH = IOL = 4 mA (MIN.)

BALANCED PROPAGATION DELAYS

. tPLH = tPHL
WIDE OPERATING VOLTAGE RANGE M1R C1R

. VCC (OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE WITH
54/74LS04
(Micro Package)
ORDER CODES :
M54HC04F1R M74HC04M1R
(Chip Carrier)

M74HC04B1R M74HC04C1R

PIN CONNECTIONS (top view)

DESCRIPTION
The M54/74HC04 is a high speed CMOS HEX IN-
VERTER fabricated in silicon gate C2MOS technol-
ogy. It has the same high speed performance of
LSTTL combined with true CMOS low power con-
sumption.
The internal circuit is composed of 3 stages includ-
ing buffer output, which enables high noise im-
munity and stable output. All inputs are equipped
with circuits against static discharge and transient
excess voltage.

INPUT AND OUTPUT EQUIVALENT CIRCUIT

NC =
No Internal
Connection

December 1992 1/9

Free Datasheet http://www.datasheet4u.com/

M54/M74HC04

TRUTH TABLE IEC LOGIC SYMBOL

A Y
L H
H L

PIN DESCRIPTION

PIN No SYMBOL NAME AND FUNCTION

1, 3, 5, 9, 1A to 6A Data Inputs
11, 13
2, 4, 6, 8, 1Y to 6Y Data Outputs
10, 12
7 GND Ground (0V)
14 VCC Positive Supply Voltage

LOGIC DIAGRAM (Per Gate)

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit
VCC Supply Voltage -0.5 to +7 V
VI DC Input Voltage -0.5 to VCC + 0.5 V
VO DC Output Voltage -0.5 to VCC + 0.5 V
IIK DC Input Diode Current ± 20 mA
IOK DC Output Diode Current ± 20 mA
IO DC Output Source Sink Current Per Output Pin ± 25 mA
ICC or IGND DC VCC or Ground Current ± 50 mA
PD Power Dissipation 500 (*) mW
o
Tstg Storage Temperature -65 to +150 C
o
TL Lead Temperature (10 sec) 300 C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnotimplied.
(*) 500 mW: ≅ 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC

2/9
 M54/M74HC04

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit
VCC Supply Voltage 2 to 6 V
VI Input Voltage 0 to VCC V
VO Output Voltage 0 to VCC V
o
Top Operating Temperature: M54HC Series -55 to +125 C
o
M74HC Series -40 to +85 C
tr, tf Input Rise and Fall Time VCC = 2 V 0 to 1000 ns
VCC = 4.5 V 0 to 500
VCC = 6 V 0 to 400

DC SPECIFICATIONS

Test Conditions Value

Symbol Parameter TA = 25 oC -40 to 85 oC -55 to 125 oC Unit
VCC
54HC and 74HC 74HC 54HC
(V)
Min. Typ. Max. Min. Max. Min. Max.
VIH High Level Input 2.0 1.5 1.5 1.5
Voltage 4.5 3.15 3.15 3.15 V
6.0 4.2 4.2 4.2
V IL Low Level Input 2.0 0.5 0.5 0.5
Voltage 4.5 1.35 1.35 1.35 V
6.0 1.8 1.8 1.8
V OH High Level 2.0 1.9 2.0 1.9 1.9
VI =
Output Voltage 4.5 IO=-20 µA 4.4 4.5 4.4 4.4
VIH
V
6.0 or 5.9 6.0 5.9 5.9
4.5 V IL IO=-4.0 mA 4.18 4.31 4.13 4.10
6.0 IO=-5.2 mA 5.68 5.8 5.63 5.60
VOL Low Level Output 2.0 0.0 0.1 0.1 0.1
VI =
Voltage 4.5 IO= 20 µA 0.0 0.1 0.1 0.1
VIH
V
6.0 or 0.0 0.1 0.1 0.1
4.5 V IL IO= 4.0 mA 0.17 0.26 0.33 0.40
6.0 IO= 5.2 mA 0.18 0.26 0.33 0.40
II Input Leakage VI = VCC or GND ±0.1 ±1 ±1 µA
6.0
Current
ICC Quiescent Supply 6.0 VI = VCC or GND 1 10 20 µA
Current

3/9
M54/M74HC04

AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = tf = 6 ns)

Test Conditions Value
o
Symbol Parameter TA = 25 C -40 to 85 oC -55 to 125 oC Unit
VCC
54HC and 74HC 74HC 54HC
(V)
Min. Typ. Max. Min. Max. Min. Max.
tTLH Output Transition 2.0 30 75 95 110
tTHL Time 4.5 8 15 19 22 ns
6.0 7 13 16 19
tPLH Propagation 2.0 27 75 95 110
tPHL Delay Time 4.5 9 15 19 22 ns
6.0 8 13 16 19
CIN Input Capacitance 5 10 10 10 pF
CPD (*) Power Dissipation 22
pF
Capacitance
(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD •VCC •fIN + ICC/6 (per Gate)

SWITCHING CHARACTERISTICS TEST CIRCUIT

TEST CIRCUIT ICC (Opr.)

INPUT WAVEFORM IS THE SAME AS THAT IN CASE OF SWITCHING CHARACTERISTICS TEST.

4/9
 M54/M74HC04

Plastic DIP14 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.51 0.020

B 1.39 1.65 0.055 0.065

b 0.5 0.020

b1 0.25 0.010

D 20 0.787

E 8.5 0.335

e 2.54 0.100

e3 15.24 0.600

F 7.1 0.280

I 5.1 0.201

L 3.3 0.130

Z 1.27 2.54 0.050 0.100

P001A

5/9
M54/M74HC04

Ceramic DIP14/1 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

A 20 0.787

B 7.0 0.276

D 3.3 0.130

E 0.38 0.015

e3 15.24 0.600

F 2.29 2.79 0.090 0.110

G 0.4 0.55 0.016 0.022

H 1.17 1.52 0.046 0.060

L 0.22 0.31 0.009 0.012

M 1.52 2.54 0.060 0.100

N 10.3 0.406

P 7.8 8.05 0.307 0.317

Q 5.08 0.200

P053C

6/9
 M54/M74HC04

SO14 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.75 0.068
a1 0.1 0.2 0.003 0.007
a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45° (typ.)
D 8.55 8.75 0.336 0.344
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 7.62 0.300
F 3.8 4.0 0.149 0.157
G 4.6 5.3 0.181 0.208
L 0.5 1.27 0.019 0.050
M 0.68 0.026
S 8° (max.)

P013G

7/9
M54/M74HC04

PLCC20 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

A 9.78 10.03 0.385 0.395

B 8.89 9.04 0.350 0.356

D 4.2 4.57 0.165 0.180

d1 2.54 0.100

d2 0.56 0.022

E 7.37 8.38 0.290 0.330

e 1.27 0.050

e3 5.08 0.200

F 0.38 0.015

G 0.101 0.004

M 1.27 0.050

M1 1.14 0.045

P027A

8/9
 M54/M74HC04

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.

 1994 SGS-THOMSON Microelectronics - All Rights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A

9/9
 DM7408 Quad 2-Input AND Gates
August 1986
Revised July 2001

DM7408
Quad 2-Input AND Gates
General Description
This device contains four independent gates each of which
performs the logic AND function.

Ordering Code:
Order Number Package Number Package Description
DM7408N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Connection Diagram Function Table

Y = AB
Inputs Output
A B Y
L L L
L H L
H L L
H H H
H = HIGH Logic Level
L = LOW Logic Level

© 2001 Fairchild Semiconductor Corporation DS006498 www.fairchildsemi.com

DM7408
Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
Supply Voltage 7V the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Input Voltage 5.5V
Characteristics tables are not guaranteed at the absolute maximum ratings.
Operating Free Air Temperature Range 0°C to +70°C The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Storage Temperature Range −65°C to +150°C

Recommended Operating Conditions

Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VIH HIGH Level Input Voltage 2 V
VIL LOW Level Input Voltage 0.8 V
IOH HIGH Level Output Current −0.8 mA
IOL LOW Level Output Current 16 mA
TA Free Air Operating Temperature 0 70 °C

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min Max Units
(Note 2)
VI Input Clamp Voltage VCC = Min, II = −12 mA −1.5 V
VOH HIGH Level VCC = Min, IOH = Max
2.4 3.4 V
Output Voltage VIL = Max
VOL LOW Level VCC = Min, IOL = Max
0.2 0.4 V
Output Voltage VIH = Min
II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA
IIH HIGH Level Input Current VCC = Max, VI = 2.4V 40 µA
IIL LOW Level Input Current VCC = Max, VI = 0.4V −1.6 mA
IOS Short Circuit Output Current VCC = Max (Note 3) −18 −55 mA
ICCH Supply Current with Outputs HIGH VCC = Max 11 21 mA
ICCL Supply Current with Outputs LOW VCC = Max 20 33 mA
Note 2: All typicals are at VCC = 5V, TA = 25°C.
Note 3: Not more than one output should be shorted at a time.

Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol Parameter Conditions Min Max Units
tPLH Propagation Delay Time CL = 15 pF
27 ns
LOW-to-HIGH Level Output RL = 400Ω
tPHL Propagation Delay Time
19 ns
HIGH-to-LOW Level Output

www.fairchildsemi.com 2
 DM7408 Quad 2-Input AND Gates
Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea-
body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support
to perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.

3 www.fairchildsemi.com
 DM74LS32 Quad 2-Input OR Gate
June 1986
Revised March 2000

DM74LS32
Quad 2-Input OR Gate
General Description
This device contains four independent gates each of which
performs the logic OR function.

Ordering Code:
Order Number Package Number Package Description
DM74LS32M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS32SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS32N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram Function Table

Y=A+B
Inputs Output
A B Y
L L L
L H H
H L H
H H H
H = HIGH Logic Level
L = LOW Logic Level

© 2000 Fairchild Semiconductor Corporation DS006361 www.fairchildsemi.com

DM74LS32
Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
Supply Voltage 7V the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Input Voltage 7V Characteristics tables are not guaranteed at the absolute maximum ratings.
Operating Free Air Temperature Range 0°C to +70°C The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Storage Temperature Range −65°C to +150°C

Recommended Operating Conditions

Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VIH HIGH Level Input Voltage 2 V
VIL LOW Level Input Voltage 0.8 V
IOH HIGH Level Output Current −0.4 mA
IOL LOW Level Output Current 8 mA
TA Free Air Operating Temperature 0 70 °C

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min Max Units
(Note 2)
VI Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V
VOH HIGH Level VCC = Min, IOH = Max
2.7 3.4 V
Output Voltage VIH = Min
VOL LOW Level VCC = Min, IOL = Max
0.35 0.5
Output Voltage VIL = Max V
IOL = 4 mA, VCC = Min 0.25 0.4
II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA
IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA
IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.36 mA
IOS Short Circuit Output Current VCC = Max (Note 3) −20 −100 mA
ICCH Supply Current with Outputs HIGH VCC = Max 3.1 6.2 mA
ICCL Supply Current with Outputs LOW VCC = Max 4.9 9.8 mA
Note 2: All typicals are at VCC = 5V, TA = 25°C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Switching Characteristics
at VCC = 5V and TA = 25°C
RL = 2 kΩ
Symbol Parameter CL = 15 pF CL = 50 pF Units
Min Max Min Max
tPLH Propagation Delay Time
3 11 4 15 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time
3 11 4 15 ns
HIGH-to-LOW Level Output

www.fairchildsemi.com 2
 DM74LS32
Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A

3 www.fairchildsemi.com
DM74LS32
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D

www.fairchildsemi.com 4
 DM74LS32 Quad 2-Input OR Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea-
body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support
to perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.

5 www.fairchildsemi.com
Higher Institute of Engineering – KMA
Electronics and Communication Eng . Dept

Logic circuits

Dr : Salah Abdelaziz

By : Abdallah Mohammed Khalil Elmadawey

A semiconductor material’s electrical conductivity is somewhere between that of a
conductor, such as metallic copper, and that of an insulator, such as glass. As the temperature
rises, its resistivity reduces, whereas metals have the opposite effect. The conductivity of a
crystal structure can be modified in a favorable way by introducing impurities (doping) to it.
When two separate doped regions in the same crystal exist, a semiconductor junction is
generated. The behavior of charge carriers such as electrons, ions, and electron holes at these
junctions is the foundation of diodes, transistors, and most modern electronics.
Semiconductors include silicon, germanium, gallium arsenide, and elements on the periodic
table’s so-called metalloid staircase. After silicon, gallium arsenide is the second most
common semiconductor, and it’s used in laser diodes, solar cells, microwave-frequency
integrated circuits, and other things. Silicon is a critical component in the manufacture of
nearly all electrical circuits.

Logic Gates
A logic gate is a simple switching circuit that determines whether an input pulse can pass
through to the output in digital circuits.
The building blocks of a digital circuit are logic gates, which execute numerous logical
operations that are required by any digital circuit. These can take two or more inputs but only
produce one output.
The mix of inputs applied across a logic gate determines its output. Logic gates use Boolean
algebra to execute logical processes. Logic gates are found in nearly every digital gadget we
use on a regular basis. Logic gates are used in the architecture of our telephones, laptops,
tablets, and memory devices.

Boolean Algebra
Boolean algebra is a type of logical algebra in which symbols represent logic levels.
The digits(or symbols) 1 and 0 are related to the logic levels in this algebra; in electrical
circuits, logic 1 will represent a closed switch, a high voltage, or a device’s “on” state. An
open switch, low voltage, or “off” state of the device will be represented by logic 0.
At any one time, a digital device will be in one of these two binary situations. A light bulb
can be used to demonstrate the operation of a logic gate. When logic 0 is supplied to the
switch, it is turned off, and the bulb does not light up. The switch is in an ON state when
logic 1 is applied, and the bulb would light up. In integrated circuits (IC), logic gates are
widely employed.
Truth Table: The outputs for all conceivable combinations of inputs that may be applied to
a logic gate or circuit are listed in a truth table. When we enter values into a truth table, we
usually express them as 1 or 0, with 1 denoting True logic and 0 denoting False logic.

Types of Logic Gates

A logic gate is a digital gate that allows data to be transferred. Logic gates, use logic to
determine whether or not to pass a signal. Logic gates, on the other hand, govern the flow of
information based on a set of rules. The following types of logic gates are commonly used:
 1. AND
2. OR
3. NOT
4. NOR
5. NAND
6. XOR
7. XNOR
Basic Logic Gates

AND Gate
An AND gate has a single output and two or more inputs.
1. When all of the inputs are 1, the output of this gate is 1.
2. The AND gate’s Boolean logic is Y=A.B if there are two inputs A and B.
An AND gate’s symbol and truth table are as follows:

Input Output
A B A AND B
0 0 0

0 1 0
1 0 0
1 1 1
Therefore, in And gate, the output is high when all the inputs are high.

OR Gate
Two or more inputs and one output can be used in an OR gate.
1. The logic of this gate is that if at least one of the inputs is 1, the output will be 1.

Input Output
A B A OR B
0 0 0
0 1 1
 1 0 1 2. The OR gate’s output will be given by the following
mathematical procedure if there are two inputs A and B: Y=A+B
1 1 1

Therefore, in the OR gate, the output is high when any of the inputs is high.
NOT Gate
The NOT gate is a basic one-input, one-output gate.
1. When the input is 1, the output is 0, and vice versa. A NOT gate is sometimes
called an inverter because of its feature.
2. If there is only one input A, the output may be calculated using the Boolean
equation Y=A’.

Input Output
A Not A
0 1
1 0

A NOT gate, as its truth table shows, reverses the input signal.

Universal Logic Gates

NOR Gate
A NOR gate, sometimes known as a “NOT-OR” gate, consists of an OR gate followed by a
NOT gate.
1. This gate’s output is 1 only when all of its inputs are 0. Alternatively, when all of
the inputs are low, the output is high.
2. The Boolean statement for the NOR gate is Y=(A+B)’ if there are two inputs A
and B.

Input Output
 A B A NOR B
0 0 1
0 1 0
1 0 0
1 1 0

By comparing the truth tables, we can observe that the outputs of the NOR gate are the polar
opposite of those of an OR gate. The NOR gate is sometimes known as a universal gate since
it may be used to implement the OR, AND, and NOT gates.
NAND Gate
A NAND gate, sometimes known as a ‘NOT-AND’ gate, is essentially a Not gate followed
by an AND gate.
1. This gate’s output is 0 only if none of the inputs is 0. Alternatively, when all of the
inputs are not high and at least one is low, the output is high.
2. If there are two inputs A and B, the Boolean expression for the NAND gate is
Y=(A.B)’

Input Output
A B A NAND B
0 0 1
0 1 1
1 0 1
1 1 0

By comparing their truth tables, we can observe that their outputs are the polar opposite of
an AND gate. The NAND gate is known as a universal gate because it may be used to
implement the AND, OR, and NOT gates.

Other Logic Gates

XOR Gate
The Exclusive-OR or ‘Ex-OR’ gate is a digital logic gate that accepts more than two inputs
but only outputs one value.
1. If any of the inputs is ‘High,’ the output of the XOR Gate is ‘High.’ If both inputs
are ‘High,’ the output is ‘Low.’ If both inputs are ‘Low,’ the output is ‘Low.’
2. The Boolean equation for the XOR gate is Y=A’.B+A.B’ if there are two inputs A
and B.
 Input Output
A B A XOR B
Input Output
0 0 A B 0A XNOR B
0 1 0 0 1 1

1 0 0 1 1 0
1 0 0
1 1 0
1 1 1
Its outputs are based on OR gate logic, as we can see from the
truth table.
XNOR Gate
The Exclusive-NOR or ‘EX-NOR’ gate is a digital logic gate that accepts more than two
inputs but only outputs one.
1. If both inputs are ‘High,’ the output of the XNOR Gate is ‘High.’ If both inputs
are ‘Low,’ the output is ‘High.’ If one of the inputs is ‘Low,’ the output is ‘Low.’
2. If there are two inputs A and B, then the XNOR gate’s Boolean equation is:
Y=A.B+A’B’.

The truth table shows that its outputs are based on NOR gate logic.

Uses of Logic Gates

1. Logic gates are utilized in a variety of technologies. These are components of chips
(ICs), which are components of computers, phones, laptops, and other electronic
devices.
2. Logic gates may be combined in a variety of ways, and a million of these
combinations are necessary to make the newest gadgets, satellites, and even robots.
3. Simple logic gate combinations can also be found in burglar alarms, buzzers,
switches, and street lights. Because these gates can make a choice to start or stop
based on logic, they are often used in a variety of sectors.
4. Logic gates are also important in data transport, calculation, and data processing.
Even transistor-transistor logic and CMOS circuitry make extensive use of logic
gates.