EDA Lecture Logic Synthesis

INSTITUTE FOR ELECTRONIC DESIGN AUTOMATION
TECHNISCHE UNIVERSITÄT MÜNCHEN

PROFESSOR DR.-ING. U. SCHLICHTMANN
Electronic Design Automation

Lecture Notes
Address: Arcisstr. 21
80333 Munich
Germany
Telephone: +49 89 289-23666
Internet: http://eda.ei.tum.de
Contents of Lecture:
Microelectronics overview; design flow for microelectronic systems, design space (Y-Chart),
implementation fabrics;
Logic Synthesis, binary Boolean functions, optimization of combinational circuits (two-level,

multi-level), FSMs, optimization of sequential circuits;
Logic Simulation, event-driven simulation, modelling and simulation using VHDL.

Important Symbols
Symbol Meaning Page
Bn n-dimensional Boolean Space 12

β(x, a, b) Multiplexer function 20
c Cube 13
c Implicant 21
cov Cover 18
D Don’t-care-set 14
F On-set 14
fxi Cofactor w.r.t. xi 15
MC Set of all cubes in B n 13
MI Set of all Implicants 21
mj Minterm, 0-cube 13
MOC Set of all 0-cubes in B n 13
MPI Set of prime implicants 21
p Prime implicant 21
POS Product of sums 18
set(x) Set of variables 14
SOP Sum of products 17
x Variable 9
x̂ Value of the variable (val(x)) 9
I MPORTANT S YMBOLS
Contents
I. Logic Synthesis 3
1 Logic Synthesis Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Binary Boolean Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 Synthesis of Two-Level Combinational Circuits . . . . . . . . . . . . . . . . . 21
4 Heuristic Minimization of Two-Level Combinational Circuits . . . . . . . . . . 34
5 Synthesis of Multi-Level Combinational Circuits . . . . . . . . . . . . . . . . 37
6 OBDD: Ordered Binary Decision Diagram . . . . . . . . . . . . . . . . . . . . 44
7 Synthesis of Sequential Circuits . . . . . . . . . . . . . . . . . . . . . . . . . 48
Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
II. Simulation of Digital Circuits 59
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2 Logic Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3 Simulation methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4 VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
C ONTENTS
1
C ONTENTS
2
I. Logic Synthesis
Task
Behavioral description: Design Requirements:

• Finite State Machine • Cell library data
• Layout design rules
• Boolean equations
• Testability
Optimization targets:
Area
Delay H
Logic synthesis L i
o g
Technology mapping w Power consumption h
Structural description:
• Netlist using components
of the target architecture
Introduction (1)
3
Typical Design Flow Steps

Behavioral Specification
Architectural Manual
Synthesis Tools Entry
RTL Description
Translation Tools
Unoptimized
Logic Description
Module
Generators
Logic
Optimization
Cell Technology
Library Mapping
Custom
Layout
Test Optimized
Generation Logic Description
Physical
Design Tools
Layout
Manufacturing
Testing Integrated Circuit
Introduction (2)
4
Y-Chart
Behavioral System level Structural

Domain Domain
Algorithmic level
System Spec. CPU, Memory

RT level
Algorithm Processor, Subsystem
Logic
Register-Transfer Spec. ALU, Reg., MUX
level
Boolean Eqn. Circuit Gate, Flip-flop
Differential Eqn. level Transistor
Rectangle/Polygon-Group
Standard-Cell / Subcell
Macro-Cell
Block / Chip
Chip / Board
Physical / Geometrical
Domain
Introduction (3)
5
Design Space
Analysis
−Verification
−Extraction
Abstraction levels
1 2 3
System System− System− Chip
specifikation architecture Board
(C) (CPUs, Busses)
4 5 6
Algorithm Algorithms Processor Block
(VHDL, C) Subsystem Chip
7 8 9
RT RT−Specification Modules Macro−Cell
Refinement
Abstraction
(Control−/data− (ALU, Registers,
flow) MUX)
10 11 12
Logic Boolean Gates, Flip−Flops
Cells
Equations (Netlist)
13 14 15
Circuit Differential Transistors Mask Data
Equations (Netlist) Polygons
Behavior Structure Geometry
Synthesis
−Generation
Views
Introduction (4)
6
Combinational Circuit: 7−Segment Decoder
x1
e
x0
c
f
x2
x3
7
g
Introduction (5)
d
b
x3 x2 x1 x0 a b c d e f g x3 x2 x1 x0 a b c d e f g a
0 0 0 0 0 1 1 1 1 1 1 0 8 1 0 0 0 1 1 1 1 1 1 1
1 0 0 0 1 0 1 1 0 0 0 0 9 1 0 0 1 1 1 1 0 0 1 1 f b
2 0 0 1 0 1 1 0 1 1 0 1 10 1 0 1 0 – – – – – – – g
3 0 0 1 1 1 1 1 1 0 0 1 11 1 0 1 1 – – – – – – –
4 0 1 0 0 0 1 1 0 0 1 1 12 1 1 0 0 – – – – – – –
e c
5 0 1 0 1 1 0 1 1 0 1 1 13 1 1 0 1 – – – – – – –
6 0 1 1 0 0 0 1 1 1 1 1 14 1 1 1 0 – – – – – – –
7 0 1 1 1 1 1 1 0 0 0 0 15 1 1 1 1 – – – – – – – d
1 Logic Synthesis Basics

Digital circuits: binary signals
x 0 1 1 0 0
OR 0 1 1 1 0 x+y
y 0 0 1 1 0 Gate
Input signals Processing of signals Output signal
(synchronous to clock) (synchronous to clock)
Logical (Signal-) Variable : x, y, . . .

Value of the Variable : value(x) , val(x) , x̂
x̂ = 0 or x̂ = 1 , x̂ ∈ {0, 1}
Important Logical Operations
Expression Name Gate symbol

x NOT, Negation
x·y AND, Conjunction
x·y NAND, (NOT AND)
x+y OR, Disjunction
x+y NOR, (NOT OR)
x⊕y XOR, (excl. OR, Antivalence)
x⊕y XNOR, (Equivalence)
Truth Table
Value assignment Truth values

x y x y x·y x·y x+y x+y x⊕y x⊕y Operation is
unary: x
0 0 1 1 0 1 0 1 0 1
binary: x · y
0 1 1 0 0 1 1 0 1 0 x+y
..
1 0 0 1 0 1 1 0 1 0 .
1 1 0 0 1 0 1 0 0 1
Logic Synthesis Basics (1)
9
Boolean Algebra
A) Laws of binary Boolean Algebra (Switching Algebra)
BA=({0 , 1}; · , +, )
Principle of duality
(1) x·y = y·x ; x+y = y+x Commutativity
(2) (x · y) · z = x · (y · z) Associativity
(x + y) + z = x + (y + z)
(3) x · (y + z) = x · y + x · z Distributivity
x + y · z = (x + y) · (x + z)
(4) x·x = x ; x+x = x Idempotence
(5) x · (x + y) = x Absorption
x+x·y = x
(6) x·1 = x ; x+0 = x Neutral Element
(7) x·0 = 0 ; x+1 = 1 Dominance
(8) x·x = 0 ; x+x = 1 Negation
(9) x = x Double Negation
(10) x·y = x+y De Morgan

x+y = x·y
10
B) Laws of Set Algebra

MA=(P(G); ∩, ∪, ; G, 0)
/
Principle of duality
Basic set G ; |G| = n
Power set P(G) ; |P(G)| = 2n
(Model of a 2n -valued Boolean algebra)
A, B,C ∈ P(G)
(1) A∩B = B∩A ; A∪B = B∪A Commutativity
(2) (A ∩ B) ∩C = A ∩ (B ∩C) Associativity

(A ∪ B) ∪C = A ∪ (B ∪C)
(3) A ∩ (B ∪C) = (A ∩ B) ∪ (A ∩C) Distributivity

A ∪ (B ∩C) = (A ∪ B) ∩ (A ∪C)
(4) A∩A = A ; A∪A = A Idempotence
(5) A ∩ (A ∪ B) = A Absorption
A ∪ (A ∩ B) = A
(6) A ∩ G = A ; A ∪ 0/ = A Neutral Element
(7) A ∩ 0/ = 0/ ; A ∪ G = G Dominance
(8) A ∩ A = 0/ ; A ∪ A = G Complement
(9) (A) = A Double Complement
(10) A∩B = A∪B De Morgan

A∪B = A∩B
11
Boolean Space
B n : n-dimensional Boolean Space
(Signal-) Variable : x
Value of the variable : val(x) , x̂; x̂ ∈ {0, 1}
Variable-n-tuple : x = (x1 , . . . , xn )
Value assignment-n-tuple : x̂ = (x̂1 , . . . , x̂n )
vertex in B n
B = {0, 1}; x̂ ∈ B n ; |B n | = 2n ; B n = {x̂0 , . . . , x̂2n −1 }
e. g. B 3 = B × B × B = {(0, 0, 0), (0, 0, 1), . . . , (1, 1, 1)}
Notation : (1, 0, 1) , (101) , 101 = x̂5

vector of bits,
bitpattern,
binary word,
binary number
011 111 x1 x2 x3 x1 x2 x3
001 101 x1 x2 x3 x1 x2 x3
010 110 x1 x2 x3 x1 x2 x3
000 100 x1 x2 x3 x1 x2 x3
x3 x2
B 3 : 3-dimensional Boolean Space
x1
Literal li (positive or negative) : xi or xi

Set of indices of literals : I0 = {1, . . . , i, . . . , n}; |I0 | = n
Partial set of indices of literals : Ij ; I j ⊆ I0
Set of literals : L0 = { li | i ∈ I0 }
12
Minterm m j , 0-Cube, : m j = ∏ li , {li ∈ L0 | i ∈ I0 }

AND clause, vertex i∈I0
Cube c j in B n , d-cube, : c j = ∏ li , {li ∈ L0 | i ∈ I j }

Product term, AND clause i∈I j
Dimension d j of cube c j : d j = |I0 | − |I j |

Distance δi j between cubes ci and c j : δi j = {l | l ∈ ci ∧ l ∈ c j }
Example : I0 = {1, 2, 3}; |I0 | = 3

n=3
mκ = x1 · x2 · x3 ; mσ = x1 · x2 · x3 ; dκ = dσ = 0; δκσ = 3
ci = x1 · x3 ; c j = x1 ; di = 1, d j = 2; δi j = 1
Notation : mκ = x1 x2 x3 , {110} ; |mκ | = 2dκ = 20 = 1

ci = x1 x3 , {100, 110} ; |ci | = 2di = 2
c j = x1 , {000, 001, 010, 011} ; |c j | = 2d j = 4
simplified notation:
x1 x2 x3 , {x1 , x2 , x3 } ; {110} , 110

x1 x3 , {x1 , x3 } ; {100, 110} , {1∗0} , 1∗0
x1 , {x1 } ; {000, 001, 010, 011} , {0∗∗} , 0∗∗
∗ or − : Don’t Care Value, DC Value
ci ∈ {0, 1, ∗}n ; |{0, 1, ∗}n | = 3n ; mκ ∈ {0, 1}n ; |{0, 1}n | = 2n
Set MC of all cubes in B n : MC = {c0 , . . . , c j , . . . , c3n −1 }

Set MOC of all 0-cubes in B n : MOC = {m0 , . . . , mκ , . . . , m2n −1 }
MOC ⊆ MC; |MC| = 3n ; |MOC| = 2n
Cube absorption : mκ ⊆ ci ⊆ 1
x1 x2 x3 ⊆ x1 x3 ⊆ 1
x3 110
110 ⊆ 1∗0 ⊆ ∗∗∗ x2
0-cube 1-cube 3-cube 1∗0
x1 100
3-cube (∗∗∗)
13
2 Binary Boolean Functions

(binary switching functions)
f (x) = f (x1 , . . . , xi , . . . , xn )
f : Bn → B f : Bn → Bm
n-dimensional multiple output function
single output function
sup( f ) = set(x) = {x1 , . . . , xi , . . . , xn } : Set of variables

support of f
f = ( f1 , . . . , f j , . . . , fm ) : Function-m-tuple
set( f ) = { f1 , . . . , f j , . . . , fm } : Set of functions
f ∈ set( f ) : f is a component of f
f := {(x̂, ŷ) ∈ B n ×B | f (x̂) = ŷ}

f (x) = y ⇐⇒ (x, y) ∈ f ⇐⇒ x f y ⇐⇒ x 7→ y
on-set( f ) = {x̂ ∈ B n | f (x̂) = 1} : On-set of f

off-set( f ) = {x̂ ∈ B n | f (x̂) = 0} : Off-set of f
Convention: f := on-set( f )
f := {x̂ ∈ B n | f (x̂) = 1}
Incomplete specification of f
f : B n → {0, 1, ∗}
on-set( f ) = F = {x̂ ∈ B n | f (x̂) = 1}
don’t-care-set( f ) = D = {x̂ ∈ B n | f (x̂) = ∗}
off-set( f ) = F ∪ D = {x̂ ∈ B n | f (x̂) = 0}
Convention: F ⊆ f ⊆ F ∪D
Binary Boolean Functions (1)
14
Cofactor (restriction)
Cofactor of f (x1 , . . . , xi , . . . , xn )
w.r.t. xi : f |xi =1 = fxi = f (x1 , . . . , 1, . . . , xn )
w.r.t. xi : f |xi =0 = fxi = f (x1 , . . . , 0, . . . , xn )
Commutativity : ( fxi )x j = ( fx j )xi = fxi x j

Substitution rule : xi · f = xi · fxi , xi · f = xi · fxi
xi + f = xi + fxi , xi + f = xi + fxi
Expansions of f (x) w.r.t. xi
f (x1 , . . . , xi , . . . , xn ) = xi · fxi + xi · fxi Shannon’s (Boole’s) expansion

= (xi + fxi ) · (xi + fxi )
= ( fxi ⊕ fxi ) · xi ⊕ fxi Muller-Reed’s (Davio’s) expansion
f = xi · fxi + xi · fxi
∂f
Boolean difference of f (x) : ∂xi ( f ) = = f[xi ] = fxi ⊕ fxi
∂xi
w.r.t. xi
Consensus of f (x) w.r.t. xi : Cxi ( f ) = fxi · fxi

(universal quantifier)
Smoothing of f (x) w.r.t. xi : Sxi ( f ) = fxi + fxi

(existential quantifier)
f is a tautology : ⇐⇒ ∀
x̂∈B n
[ f (x̂) = 1] , f (x) = 1
f = xi · fxi + xi · fxi = 1 ⇐⇒ fxi = 1 AND f xi = 1
f is a contradiction : ⇐⇒ ∀
x̂∈B n
[ f (x̂) = 0] , f (x) = 0
f = (xi + fxi ) · (xi + fxi ) = 0 ⇐⇒ fxi = 0 AND f xi = 0
f is independent of xi : ⇐⇒ fxi = fxi ⇐⇒ fxi ⊕ fxi = 0

f is dependent on xi : ⇐⇒ fxi 6= fxi ⇐⇒ fxi ⊕ fxi = 1
DUAL( f (x1 , x2 , . . . , xn )) = f (x1 , x2 , . . . , xn )
15
f is positive symmetric w.r.t. : ⇐⇒ f (. . . , xi , . . . , x j , . . .) = f (. . . , x j , . . . , xi , . . .)

xi and x j (positive symmetry) ⇐⇒ fxi x j = fxi x j
f is negative symmetric w.r.t. : ⇐⇒ f (. . . , xi , . . . , x j , . . .) = f (. . . , x j , . . . , xi , . . .)

xi and x j (negative symmetry) ⇐⇒ fxi x j = fxi x j
f is positive unate in xi : ⇐⇒ fxi ⊆ fxi
fxi ⊆ fxi ⇐⇒ fxi = fxi + fxi ⇐⇒ fxi = fxi · fxi ⇐⇒ fxi + fxi = 1
fxi ⊆ fxi ⇐⇒ f = xi · fxi + fxi ⇐⇒ f = xi · fxi · fxi ⊕ fxi
IF fxi ⊆ fxi , THEN f xi ⊆ f
f is negative unate in xi : ⇐⇒ fxi ⊆ fxi
fxi ⊆ fxi ⇐⇒ fxi = fxi + fxi ⇐⇒ fxi = fxi · fxi ⇐⇒ fxi + fxi = 1
fxi ⊆ fxi ⇐⇒ f = xi · fxi + fxi ⇐⇒ f = xi · fxi · fxi ⊕ fxi
IF fxi ⊆ fxi , THEN fxi ⊆ f
f is unate in xi : ⇐⇒ ( fxi ⊆ fxi ) ∨ ( fxi ⊆ fxi )

f is binate in xi : ⇐⇒ ( fxi 6⊆ fxi ) ∧ ( fxi 6⊆ fxi )
f is unate : ⇐⇒ ∀ f is unate in xi
xi ∈set(x)
Additional Comment:
To every set M, M ⊆ G, a binary Boolean function f (x) can be assigned by a coding of its
elements z, z ∈ M:
z := x̂ ; |G| = 2n
z ∈ M ⇐⇒ x̂ ∈ M ⇐⇒ x̂ ∈ on-set( f ) ⇐⇒ f (x̂) = 1
i.e.: M , on-set( f )
f (x) : characteristic function of M
16
Truth table, TT
Example for f (x, y, z)
mκ xyz f (x, y, z) f cκ xyz f f cκ xyz f f

m0 000 1 0 c0 000 1 0
m1 001 0 1 cα 01∗ 1 0 cγ 0∗0 1 0
m2 010 1 0 cβ ∗11 1 0 cβ ∗11 1 0
m3 011 1 0
c1 001 0 1
m4 100 0 1 cρ 10∗ 0 1 cτ ∗01 0 1
m5 101 0 1 cσ 1∗0 0 1 cσ 1∗0 0 1
m6 110 0 1 TT 2 TT 3
m7 111 1 0
reduced truth tables
TT 1
(Implicant tables)
(Canonical) sum of products formula, (C)SOP

(Canonical) disjunctive normal form, (C)DNF
[
CSOP : f = ∑ mκ , mκ ; mκ ⊆ f , mκ ∈ MOC
κ κ
Example (1) : f = m0 + m2 + m3 + m7
TT 1 f (x, y, z) = x·y·z + x·y·z + x·y·z + x·y·z
f = {000} ∪ {010} ∪ {011} ∪ {111}
f = {000, 010, 011, 111}
Additional Comment:
f (x, y, z) = (x + x) · f = x · f + x · f = x · fx + x · fx
= (x + x) · (y + y) · (z + z) · f
f (x, y, z) = x · y · z · f (0, 0, 0) + x · y · z · f (0, 0, 1)

+ x · y · z · f (0, 1, 0) + x · y · z · f (0, 1, 1)
+ x · y · z · f (1, 0, 0) + x · y · z · f (1, 0, 1)
+ x · y · z · f (1, 1, 0) + x · y · z · f (1, 1, 1)
e. g. f (0, 1, 0) = fx·y·z
17
[
SOP : f = ∑ cκ , cκ ; cκ ⊆ f , cκ ∈ MC
κ κ
Example (2) : f = c0 + cα + cβ , c0 ∪ cα ∪ cβ
TT 2 f (x, y, z) = x·y·z + x·y + y·z
f = {000} ∪ {01∗} ∪ {∗11}
f = {000} ∪ {010, 011} ∪ {011, 111}
Example (3) : f = cγ + cβ , cγ ∪ cβ
TT 3 f (x, y, z) = x · z + y · z
f = {0∗0} ∪ {∗11} = {000, 010} ∪ {011, 111}
Definition : A cover of f is a set of product terms

cov( f ) = {c1 , . . . , cκ , . . . , ck }, such that: f = ∑ cκ
cκ ∈cov( f )
(Canonical) product of sums formula, (C)POS

(Canonical) conjunctive normal form, (C)CNF
\
CPOS : f = ∏ mκ , mκ ; mκ ⊆ f , mκ ∈ MOC
κ κ
Example (1) : f = m1 + m4 + m5 + m6
TT 1 f = m1 · m4 · m5 · m6
f (x, y, z) = (x + y + z) · (x + y + z) · (x + y + z) · (x + y + z)
\
POS : f = ∏ cκ , cκ ; cκ ⊆ f , cκ ∈ MC
κ κ
Example (2) : f = c1 · cρ · cσ ; f = c1 + cρ + cσ
TT 2 f (x, y, z) = (x + y + z) · (x + y) · (x + z)
Example (3) : f = cτ · cσ ; f = cτ + cσ
TT 3 f (x, y, z) = (y + z) · (x + z)
f (x, y, z) = x · z + y · z + x · y (SOP)
18
Circuit Implementation
Gate symbols Operation

DIN-Norm Function,
American German
40900 On-set
y = f (x1 , x2 )
AND & f = {11}
= x1 · x2
y = f (x1 , x2 )
OR ≥1 f = {01, 10, 11}
= x1 + x2
y = f (x)
NOT 1 f = {0}
=x
y = f (x1 , x2 )
NAND & f = {00, 01, 10}
= x1 · x2
y = f (x1 , x2 )
NOR ≥1 f = {00}
= x1 + x2
y = f (x1 , x2 )
XOR =1 f = {01, 10}
= x1 ⊕ x2
y = f (x1 , x2 )
XNOR = f = {00, 11}
= x1 ⊕ x2
y = f (x1 , x2 )
Subjunction
≥1 = x1 → x2 f = {00, 01, 11}
(Implication)
= x1 + x2
x β = {001, 011,
a M
x: Selector input y = β(x, a, b)
MUX U y 110, 111}
b X a, b : Data inputs = x·a+x·b
= {0∗1, 11∗}
Example (1) : x y z
w = f (x, y, z) = x · y · z + x · y · z + x · y · z + x · y · z
Literal count : 12
(Effort, area consumption)
Two-level realization w
Number of circuit levels : 2
(Signal delay)

≡
19
Example (2) : Example (3) :
w = f (x, y, z) = x · y · z + x · y + y · z w = f (x, y, z) = x · z + y · z
(7 literals) (4 literals)
x y z
x y z
w w
2 circuit levels 2 circuit levels
Example (MUX) :
x
x a y = β(x, a, b)
a M y = ite(x, a, b)
U y
b X b
x : Selector input
a, b : Data inputs
y = β(x, a, b) = x · a + x · b ; β(1, a, b) = a , β(0, a, b) = b
x · a + x · b ⇐⇒ if x then a , else b
β(x, a, b) , ite(x, a, b)
Multiplexer function β :
y = β(x, a, b) = x·a+x·b
= (x + a) · (x + b)
= (x → a) · (x → b)
= [x · (a ⊕ b)] ⊕ b
f (x1 , . . . , xi , . . . , xn ) = xi · fxi + xi · fxi

= β(xi , fxi , fxi )
20
3 Synthesis of Two-Level Combinational Circuits

Definitions:
a) An implicant c of a function f is a product term c ∈ MC in B n , for which c ⊆ f holds.
Set of implicants : MI = {c ∈ MC | c ⊆ f }
b) A prime implicant p of a function f is an implicant, which is not contained in any

implicant of f .
Set of prime implicants : MPI = {p ∈ MI | p 6⊂ c, for all c ∈ MI}

n
3
|MPI| . ; MPI ⊆ MI ⊆ MC
n
Proposition:
Given p j ∈ MI (p j ⊆ f ) with p j = ∏ li , then:

i∈I j
p j ∈ MPI : ⇐⇒ (p j )li ∈
/ MI, for all li
or pj ∈/ MPI ⇐⇒ (p j )li ∈ MI, for at least one li .
Example (2) : f (x, y, z) = x · y · z + y · z + x · y
(1) y · z ∈ MPI
Reasoning : (y · z)y = z ; (y · z)z = y ;
z∈/ MI AND y ∈ / MI or z 6⊆ f AND y 6⊆ f , since
fz = y + x · y = y 6= 1 AND fy = z + x 6= 1
(2) x · y · z ∈
/ MPI
Reasoning : (x · y · z)y = x · z ;
x · z ∈ MI or x · z ⊆ f , since
fx·z = y + y = 1
c) A minimal SOP (MinSOP) consists of a minimal number of literals.

d) Quine’s theorem about prime implicants:
A MinSOP always consists of prime implicants.
e. g. SOP : f = x · y + y , {10, ∗1}

MinSOP : f = x + y , {1∗, ∗1}
Synthesis of Two-Level Combinational Circuits (1)
21
Quine’s Method to determine all prime implicants of f
Given : SOP or (reduced) truth table

Wanted : All prime implicants (Quine’s PI-Theorem)
Step 1) Determination of CSOP from SOP

(Disadvantage: number of minterms possibly very large, 2n )
e. g. SOP : f (x, y, z) = x · y · z + x · y · (z + z) + y · z · (x + x)
| {z } | {z }
=1 =1
CSOP : f (x, y, z) = x · y · z + x · y · z + x · y · z + x · y · z
Step 2) Determination of all prime implicants of f by exhaustive application of two laws

on the CSOP.
Specialized rule of resolution (R) : x·a+x·a = a

(specialized consensus) β(x, a, a) = a
Law of absorption (A) : a+a·b = a

a·b ⊆ a
Table of prime implicants for example (1):

R
Number of
positive Minterm of f
literals 0-cube A 1-cube A 2-cube A ...
√
0 x · y · z , {000} = m0 x · z , {0∗0} = cγ
√
1 x · y · z , {010} = m2 x · y , {01∗} = cα
√
2 x · y · z , {011} = m3 y · z , {∗11} = cβ
√
3 x · y · z , {111} = m7
Definition: A complete SOP of f consists of all prime implicants of f .
e. g.
CompSOP, : f = x · z + x · y + y · z = p1 + p2 + p3
complete sum of products
prime cover : pcov( f ) = {p1 , p2 , p3 }
22
Quine - McCluskey: Determination of MinSOP from CompSOP by solution of a covering

problem
Example:
CSOP : f = m0 + m2 + m3 + m7 ; CompSOP: f = p1 + p2 + p3
For each minterm For each prime implicant
of f : m ⊆ f of f : p ⊆ f
Condition C for covering all minterms by prime implicants:
For each minterm m at least one prime implicant p must exist in the MinSOP,
such that: m ⊆ p , i. e.
C = (m0 ⊆ p1 ) · ( m2 ⊆ p1 + m2 ⊆ p2 ) · ( m3 ⊆ p2 + m3 ⊆ p3 ) · (m7 ⊆ p3 )
!
C = τ1 ·( τ1 + τ2 )·( τ2 + τ3 )· τ3 = 1
&
C = τ1 · τ3 + τ1 · τ2 · τ3
Absorption
C = τ1 · τ3 ; τν is selection variable for pν ; τν ∈ {0, 1}
MinSOP : f = p1 + p3 = x · z + y · z , compare circuit realization of example (3)
Comment: p1 and p3 must be selected, as they are essential prime implicants.
Covering table:
H m m0 = m2 = m3 = m7 =
HH
p HHH x · y · z x · y · z x · y · z x · y · z
p1 = x · z 1 1 0 0 Selection of p1 : Covering of m0 and m2
p2 = x · y 0 1 1 0
p3 = y · z 0 0 1 1 Selection of p3 : Covering of m3 and m7
Reduction of problem and heuristic selection:
a) Determine of essential prime implicants (only ’1’ in a given column).
b) Cross out minterms (columns), which will be covered when a dominant minterm is
covered.
e. g. m2 is dominated by m0 and
m3 is dominated by m7 .
c) Select prime implicants based on maximal number of ’1’s in rows (greedy algorithm).
23
Determination of all prime implicants using the resolution rule
Given : SOP or (reduced) truth table

Wanted : All prime implicants (Quine’s PI-Theorem)
Determination of all prime implicants of f by exhaustive application of two laws on the SOP
(Determination of CSOP not required!)
Law of absorption (A) : a+a·b = a

a·b ⊆ a
General rule of resolution (R) : x·a+x·b = x·a+x·b + a·b

in disjunctive form a·b
β(x, a, b) = β(x, a, b) + |{z}
(consensus in general) Resolvent
a · b ⊆ β(x, a, b)
With x ∈ sup( f ) , a ∈ MC , b ∈ MC, and: IF a · b 6= 0, THEN δ(x a, x b) = 1.
Special cases of R: 1) β(x, a, a) = x·a+x·a = x·a+x·a+a = a

2) β(x, a, 1) = x·a+x = x·a+x+a = x+a
3) β(x, 1, b) = x+x·b = x+x·b+b = x+b
4) β(x, a, a · b) = x·a+x·a·b = x·a+x·a·b+a·b = x·a+a·b
5) β(x, a · b, a) = x·a·b+x·a = x·a·b+x·a+a·b = x·a+a·b
Resolution method
(Layer algorithm)
a) Example SOP: b) Example SOP:

f (x, y, z) = x · y + x · y · z + x · y · z t(x, y, z) = y · z + x · z + y · z + x · z
f Layer t Layer
lA lA lA lA lA lA
x·y+x·y·z+x·y·z 0 y·z+x·z+y·z+x·z 0
R R
+y · z + x · z 1 +x · y + z + x · y + x · y + z + x · y 1
R
No further resolvents possible. R +y + x + 1 + . . . 2
and A laws have been applied ex- If repeated application of the resolution
haustively. Computation of Comp- rule – starting from an arbitrary SOP –
SOP by determination of all possi- leads to a resolvent 1, then t = 1 has been
ble prime implicants! proven. Tautology proof of t using the
layer algorithm!
24
c) Deduction by the layer algorithm
SOP Layer
...+x·a+x·b+... 0
R
...+a·b+... 1
.. ..
. .
+1 or maximal number n
of prime impli-
cants
Determination of all prime implicants from a conjunctive normal form (POS)
Given : POS or (reduced) truth table

Wanted : All prime implicants
Theorem : f1 · f2 is a CompSOP, IF f1 and f2 are each CompSOPs.
Determination of all prime implicants of f from the POS representation by exhaustive

application of laws of distribution and absorption. All other laws of Boolean algebra are to be
considered (no determination of CPOS required!).
Example (2):
POS : f (x, y, z) = (x + y) · (x + z) · (x + y + z)
| {z } | {z } | {z }
CompSOP CompSOP CompSOP
l l
= (x + x · z + x · y + y · z) · (x + y + z)
= (x + y · z) · (x + y + z)
| {z } | {z }
CompSOP CompSOP
l
= x·x+x·y+x·z+x·y·z+y·z+y·z·z
CompSOP: f (x, y, z) = x · y + x · z + y · z
25
Visualization of logic minimization in the Boolean space B n
a) Karnaugh map
Representation for n = 3
z Segment mν ; mν ∈ MOC , ν = 0 , . . . , 2n − 1
Set of segments: MOC
xyz mµ and mν are neighboring segments, IF δµν = 1
000 001 101 100
xyz y
010 011 111 110
n=2 n=1
x
00 10 0
y x
01 11 1
x
b) Cube graph Gn = (MOC, E)
Representation for n = 3
xyz vertex mν
111
edge k = (mµ , mν )
mµ
011 101 110
set of vertices: MOC
mµ , mν ∈ MOC
001 010 100
set of undirected edges: K
K ⊆ MOC × MOC
x y z 000 (mµ , mν ) ∈ K ⇐⇒ δµν = 1
n=0
n=1
n=2
n
Definition : A cube graph Gn (n-cube) consists of 2n vertices and 2 · 2n edges. Each vertex is
of degree g = n.
26
Worksheet (for copying)
Karnaugh maps and cube graphs for n = 3 and n = 4
z
x y z w 0000 0001 0101 0100
x y z 000 001 101 100 0010 0011 0111 0110

z
y
010 011 111 110 1010 1011 1111 1110
x
x 1000 1001 1101 1100
n=3
y
n=4
xyz
111
011 101 110
001 010 100
xyzw
1111
x y z 000
n=3
0111 1011 1101 1110
0011 0101 0110 1001 1010 1100
0001 0010 0100 1000
x y z w 0000
n=4
27
c) Example (1):
n=3
x·y
z }| {
Given CSOP : f = x·y·z+x·y·z+x·y·z+x·y·z
| {z } | {z }
x·z y · z
xyz
111 1
z
011 1 101 0 110 0
1 0 0 0
x y z 000 001 101 100
001 0 010 1 100 0
1 1 1 0 y
010 011 111 110
x y z 000 1 x
Wanted MinSOP : f = x · z + y · z
f = {0 ∗ 0, ∗11}
xyz
111 1
y·z
z
011 1 101 0 110 0
1 0 0 0
x y z 000 001 101 100
001 0 010 1 100 0
1 1 1 0 y
010 011 111 110
x·y x·z
x y z 000 1 x·z y·z x
28
d) Example (4):
n=4
y·z
z }| {
Given SOP : f = y · z · w + y · z · w +y · z · w + x · y · w
| {z }
y·w x·w
x y z w
w
1 1
0000 0001 0101 0100
y·z·w 1 f
0010 0011 0111 0110
z
1 1
1010 1011 1111 1110
x
1 1 1 x·y·w
1000 1001 1101 1100
y·z·w y
y·z·w 12 literals
xyzw
1111 1
x·y·w
0111 0 1011 1 1101 1 1110 0

y·z·w
0011 1 0101 0 0110 0 1001 1 1010 0 1100 0
0001 1 0010 0 0100 0 1000 1
y·z·w
y·z·w
x y z w 0000 1
29
Wanted MinSOP : f = y · z + y · w + x · w
w x y z w
1 1
0000 0001 0101 0100
f
y·w 1
0010 0011 0111 0110
z
1 1
1010 1011 1111 1110
x
1 1 1 x·w
1000 1001 1101 1100 6 literals
y·z y
xyzw
1111 1
x·w
0111 0 1011 1 1101 1 1110 0
0011 1 0101 0 0110 0 1001 1 1010 0 1100 0
y·w
0001 1 0010 0 0100 0 1000 1
y·z
x y z w 0000 1
30
Synthesis of multiple output functions
Nomenclature for functions with multiple outputs:

Meaning for the output part:
xyz f1 f2 1 : corresponding product term of input part is in on-set of
101 10 this function component
*11 *0 * : corresponding product term of input part is in DC-set of
input output this function component
part part 0 : no statement about the corresponding product term of in-
put part for this function component
Example (5): x f1
y S1 f2 f : B3 → B2
z
Multiple Irredundant
SOP MinSOP
implicant x y z Cover
f1 xyz+yz xz+yz xz+yz+xyz xz+xyz
f2 xy+xyz xy+xz xy+xz+xyz xz+xyz
Literals 10 8 11 7
Steps: 1) Expand 2) Reduce 3) Remove

(implicants) (implicants) (redundant implicants)
xyz f1 f2 xyz f1 f2 xyz f1 f2 xyz f1 f2

101 10 1*1 10 1*1 10 1*1 10
*11 10 *11 10 *11 10
011 11 011 11
01* 01 01* 01 01* 01
000 01 0*0 01 0*0 01 0*0 01
Expand : Implicant covers more minterms / consists of fewer literals

(Minimization of literals)
Reduce : Implicant covers fewer minterms / consists of more literals
(Preference for multiple implicants)
Remove : Removal of redundant implicants from cov( f )
(Minimization of number of cubes)
Definition : An irredundant cover of f does not contain redundant implicants.

Then for each ck ∈ cov( f ) : cov( f )\{ck } 6= cov( f )
31
Realization with 2 MinSOPs Realization with double implicants

x y z x y z
f1 f1
f2 f2
Computation of double implicants from f1 and f2

x·z x·y
z }| { z }| {
f1 = x · y · z + x · y · z +x · y · z f2 = x · y · z + x · y · z +x · y · z
| {z } | {z }
y·z x·z
f1 · f2 = (x · z + y · z) · (x · y + x · z)
= y·z · x·y = x·y·z
= {∗11, 10} · {01∗, 01} = {011, 11}
output part
input part } of a 3-2 value assignment tuple
Comment : SOP representations of Boolean functions (AND-OR-arrays) can be directly im-

plemented in Programmable Logic Devices (PLDs). In case of a standard cell
realization with library gates, NAND and NOR gates are preferred.
Equivalent Gates: Realization with NAND Gates:

xyz
,
f1
,
, f2
32
Synthesis of Circuits from Incompletely Specified Functions
Example (6): x1 y1
x2 S2 y2 f : B3 → B2 ; f (x̂) = ŷ ⇐⇒ (x̂, ŷ) ∈ f ⇐⇒ x̂ 7→ ŷ
x3
F1 ⊆ f1 ⊆ F1 ∪ D1
x̂1 x̂2 x̂3 ŷ1 ŷ2 F1 = {0 ∗ 0, 101} , D1 = {001}
0 * 0 1 0 f1 = x1 · x3 + x1 · x2 · x3 + x1 · x2 · x3
1 0 1 1 0
0 0 1 * 1 F2 ⊆ f2 ⊆ F2 ∪ D2
* 0 1 0 1 F2 = {∗01, 010} , D2 = {011}
0 1 0 0 1 f2 = x2 · x3 + x1 · x2 · x3 + x1 · x2 · x3
0 1 1 0 *
(x̂, ŷ) ∈ B 3 × B 2 | f (x̂) = ŷ

f :=
Convention: tuple (x̂, ŷ) with ŷ = 00 will not be included in the set f .
optional optional
f ={(0 ∗ 0, 10),(101, 10),(001, ∗1), (∗01, 01), (010, 01),(011, 0∗)}
Expand
(001, 10), (001, 01) Expand (011, 01)
| {z } | {z } | {z }
(∗01, 10), (∗01, 01), (01∗, 01)
| {z }
(∗01, 11) multiple prime implicant
x1 x2 x3
y1
y2
33
4 Heuristic Minimization of Two-Level Combinational

Circuits
Exact methods of minimization of combinational circuits with a large number of inputs (e.g.
n > 16) require very high computational effort (time, memory, resources), because the number
of minterms and prime implicants grows exponentially with the number of variables. Therefore,
heuristic methods have been developed for practical industrial application (e.g. ESPRESSO,
MIS, SIS from University of California, Berkeley).
Combinatorial optimization (local search)
Configuration : feasible solution, cov( f )

Solution space (feasible region) : Set H of all configurations (all covers of f )
(solution space search space) H = {1, . . . , i, j, . . . , N} , N < ∞
H is a set of numbers
Cost of a configuration : ϕ(i), e.g. number of literals in cover i
Objective function, cost function : ϕ: H → R+
Configuration j is global minimum : ⇐⇒ ϕ( j) ≤ ϕ(i), for all i ∈ H:
∀ ϕ( j) ≤ ϕ(i)
i∈H
j
Modification : (i, j) , i , ϕ(i) ≥ ϕ( j)
(Transition of configuration from i
to j or from j to i) E.g.: In covi ( f ) one literal is removed from a product
Important: feasibility check! term, or in cov j ( f ) one literal is added to a product
term.
Set of all possible modifications : R ⊆ H × H , R is a binary relation
Configuration graph : G = (H, R) , H : Set of vertices
R : Set of edges
Set of successor configurations of : Γ(i) = { j ∈ H|(i, j) ∈ R}
i∈H
Configuration i is a local minimum : Γ(i) = 0/
Arrow diagram of G = (H, R) : 1 3

2
4 5
i
Heuristic minimization of two-level combinational circuits (1)
34
Modification
Given : cov( f ) or f in SOP-Form, F ⊆ f ⊆ F ∪ D

c ∈ cov( f ) , [cov( f )]\{c} = cov(h)
f = c+h NB: cl = c(l = 1) , cl · l = c
Wanted : successor or predecessor configuration of covi ( f )
1. Expand (removal of a literal l from c)

?
covi ( f ) = {c} ∪ cov(h) −→ {cl } ∪ cov(h) = cov j ( f )
Feasibility conditions: c + h = cl + h
c + h = cl · l + cl · l + h = c + cl · l + h
h = cl · l + h
cl · l ⊆ h
2. Reduce (addition of a literal l to c)

?
covi ( f ) = {c} ∪ cov(h) −→ {c · l} ∪ cov(h) = cov j ( f )
Feasibility conditions: c+h = c·l +h

c·l +c·l +h = c·l +h
c·l +h = h
c·l ⊆ h
3. Remove (removal of a complete product term)

?
covi ( f ) = {c} ∪ cov(h) −→ cov(h) = cov j ( f )
Feasibility conditions: c+h = h
c ⊆ h
Checking for containment (as in 1., 2., and 3.) is very simple in special cases:
Case 1) c ⊆ h, IF p⊆h AND c⊆ p Absorption (A)
Case 2) c ⊆ h, IF l · c1 + l · c2 ⊆ h AND c ⊆ c1 · c2 Resolution (R)
35
Comment on Combinatorial Optimization
The feasibility condition (containment check) can be expressed advantageously as a tautology

check. Thus the problem of combinational optimization is transformed into a sequence of deci-
sion problems.
Proposition:
Let f : B n → B and c ∈ MC or c1 , c2 ∈ MC .
Then : c ⊆ f ⇐⇒ fc ≡ 1 .
And : c1 + c2 ⊆ f ⇐⇒ ( fc1 ≡ 1) AND ( fc2 ≡ 1)
Example : f (x, a, b) = x · a + x · b ; c = a · b
a · b ⊆ f ⇐⇒ fab = 1 ⇐⇒ f (x, 1, 1) = 1 ⇐⇒ x + x = 1
Advantages of transforming a containment check into a tautology check:
a) By cofactoring a function, the function can be represented using fewer resources.
b) Proof of tautology is a standard problem which appears in many applications (SAT,

satisfiability problem). It can be solved e.g. by the layer algorithm of the resolution
method or by using binary decision diagrams (BDDs).
Proof of tautology for a function can recursively be reduced to proof of tautology for the
cofactors of the function:
f (x) = 1 ⇐⇒ ( fxi = 1) AND ( fxi = 1)

( fxi = 1) ⇐⇒ ( fxi x j ) = 1 AND ( fxi x j ) = 1
and so on
If f is unate w.r.t. xi , then the proof of tautology can be simplified:

For fxi ⊆ fxi : f (x) = 1 ⇐⇒ fxi = 1 ,
for fxi ⊆ fxi : f (x) = 1 ⇐⇒ fxi = 1
Example : f (x, y, z) = z · (x · y + x · y) + x + y + x · y
From fz ⊆ fz AND fz = x + y + x · y = 1
it follows f (x, y, z) = 1
36
5 Synthesis of Multi-Level Combinational Circuits
Given : MinSOP of a two-level circuit

Wanted : Multi-level circuit with fewer gates / literals and more advantageous fanin / fanout
structures
“General” representation of a combinational circuit
x1 z4 Gate
x2 g4 Module
z1
x3 g1 fanout g6 y1
z3
x4 g3 z5
g5 y2
z2
x5 g2
x6
x7
1. 2. 3. 4. Level
Primary inputs (PI) : x1 , x2 , x3 , x4 , x5 , x6 , x7

Primary outputs (PO) : y1 , y2
Internal signals (INT) : z1 , z2 , z3 , z4 , z5
z1 = g1 (x2 , x3 , x4 ) ; z4 = g4 (x1 , z1 ) ; y1 = g6 (z4 , z5 )

z2 = g2 (x4 , x5 , x6 ) ; z5 = g5 (z3 , x7 ) ; y2 = g5 (z3 , x7 )
z3 = g3 (z1 , z2 )
Chaining of subfunctions:
e.g. y2 = f2 (x) = g5 (g3 (g1 (x2 , x3 , x4 ), g2 (x4 , x5 , x6 )), x7 )
Synthesis of Multi-Level Combinational Circuits (1)
37
Boolean network BN (of given 4-level circuit)
BN = (V, E) is a directed acyclic graph (dag)

x1 z4
x2 Set of vertices:
z1 y1 V = VPI ∪VINT ∪VPO
x3 z3 VPI = {x1 , . . . , x7 }
x4 z2 VPO = {y1 , y2 }
y2
x5 z5 VINT = {z1 , . . . , z5 }
x6 terminal Set of edges:
x7 internal vertices E = {(x1 , z4 ), . . . , (z5 , y2 )}
vertices
initial vertices
z2 z3
directed edge (z2 , z3 )
initial vertex terminal vertex
(z2 , z3 ) ∈ E ⇐⇒ z2 is input signal and z3 is output signal of the same module
Branch points: x4 , z1 , z5 (fanout stems)
Reconvergence points: z3 , y1
fanin(z3 ) = {z1 , z2 } (predecessor of z3 )
transitive fanin(z3 ) = {z1 , z2 , x2 , x3 , x4 , x5 , x6 } (ancestor of z3 )
(Limited) algebraic methods
y1 = y2 + x1 · x2 + x1 · x3 + x1 · x4
Example (7) : y2 = x2 · x5 · x7 + x2 · x6 · x7 + x3 · x5 · x7 + x3 · x6 · x7 + x4 · x7
By “clever” (systematic) factoring out we obtain:

y1 = y2 + x1 · (x2 + x3 + x4 )
y2 = (x2 + x3 + x4 ) · (x4 + x5 + x6 ) · x7
y1 x1 z4
x2
x3 z1 y1
z3
x4 y2
x5 z5
x6 z2
2-level x7
implementation 4-level implementation
Algebraic methods for synthesis of multi-level circuits have been developed especially at the
University of California at Berkeley. They have been implemented in the tools MIS and SIS.
38
Functional Decomposition – Task
Given : Function f with |v| := |set(v)| = n inputs, and a

w
partitioning of variables v into x and y
f
v1 v2 . . . vn V = B |v| , |V | = 2|v| ; W = B , |W | = 2
X = B |x| , |X| = 2|x| ; Y = B |y| , |Y | = 2|y|
w |X ×Y | = |X| · |Y | = 2|x|+|y| = 2|v|
f
w = f (v) ; f :V →W ; v̂ 7→ ŵ
x y w = f (x, y) f : X ×Y → W ; (x̂, ŷ) 7→ ŵ
w Wanted : Decomposition of function f into functions g and h

g
w = g(h(x), y) ; g : Z ×Y → W , h : X → Z
z
Z = B |z| , |Z| = 2|z|
h
w = g(z, y) z = h(x)
x y
bound free Composition function Decomposition function
variables variables
Assumption : Disjoint partitioning of variables v into x and y
set(x) ∪ set(y) = set(v)
set(x) ∩ set(y) = 0/
Condition for advantageous decomposition: |z| ≤ |x| − 1

|Z| ≤ 12 |X|
Comments:
The task of functional decomposition describes in a general manner the decomposition of com-
binational circuits into interlinked subcircuits (or the decomposition of a Boolean function into
interlinked subfunctions, respectively).
In contrast to algebraic methods, all laws of Boolean algebra are used in functional decomposi-
tion.
The assumption of a disjoint partitioning of the variables does not limit the generality of this
method, since e.g. common variables can be assigned completely to the set of bound variables.
A beneficial partitioning of the variables can be determined e.g. by “quick exploration” using
BDDs.
39
Functional Decomposition – Solution Steps
Example (8) : w = f (x, y) = f (x1 , x2 , x3 , y1 , y2 )

w = x1 x3 · y1 + x3 · y2 + x1 x2 x3 · y1 + x2 x3 · y1 + x1 x2 · y2 + x1 x2 x3 · y1
Step 1 : Evaluate f (x̂i , y) for i = 0, 1, . . . , 23 − 1
(x̂1 , x̂2 , x̂3 )i

(ŷ1 , ŷ2 ) 000 010 100 001 111 011 101 110
00 1 1 1 1 1 1 1 1
01 1 1 1 0 0 0 0 0
10 0 0 0 1 1 1 1 1
11 0 0 0 1 1 0 0 0
f (x̂i , y) y1 y1 + y2 y2
Decomposition matrix for f (x, y)
Equivalence x̂i ∈ X mi ∈ MOC

f (x̂i , y)
class (x̂1 , x̂2 , x̂3 )i mi
X1 000, 010, 100 m0 , m2 , m4 y1
X2 001, 111 m1 , m7 y1 + y2
X3 011, 101, 110 m3 , m5 , m6 y2
Decomposition table for f (x, y)
f (x̂i , y) = f (x̂ j , y) ⇐⇒ x̂i ∼ x̂ j ; x̂i and x̂ j are equivalent, i.e. are elements of an
equivalence class Xk of the partition Π of X.
Π(X) = {X1 , X2 , X3 }
= {{000, 010, 100}, {001, 111}, {011, 101, 110}}
Definition for Π(X) = {X1 , X2 , X3 }

Π(X) ⊆ P(X) is a partition of X 6= 0/ iff
X1 , X2 , X3 6= 0/ , X1 ∪ X2 ∪ X3 = X
and X1 ∩ X2 , X1 ∩ X3 , X2 ∩ X3 = 0/
(pairwise disjoint classes).
Xk ⊆ X , Xk ∈ P(X) ; |Π(X)| = l = 3 ; l is number of equivalence classes
Result of step 1:
w = f (x, y) = (m0 + m2 + m4 ) · y1 + (m1 + m7 ) · (y1 + y2 ) + (m3 + m5 + m6 ) · y2
40
Step 2 : Construct the decomposition function h(x)
z = h(x) , h : X →Z ; X = B 3 , Z = B |z|
Decomposition condition: l ≤ 2|z| ≤ 21 · 2|x|
|z| = 2 , since l = 3 and |x| = 3
z = h(x) , (z1 , z2 ) = (h1 (x), h2 (x))

z1 = h1 (x) , z2 = h2 (x)
value assignment : X → Z
(ẑ1 , ẑ2 )k
X1 000, 010 y1
100
X2 001, 111 y1 + y2
011, 101
X3 y2
110
X h Z w = f (x̂, y)
w = g(ẑ, y)
The mapping of value assignments (ẑ1 , ẑ2 )k with k = 0, 1, 2, 3 , i.e. of 00, 01, 10, 11,
to the available positions in Z is called coding.
Assignment condition:
IF x̂i x̂ j , THEN h(x̂i ) 6= h(x̂ j )

IF x̂i x̂ j , THEN ẑk 6= ẑr , k, r = 0, 1, 2, 3
x̂i x̂ j : x̂i and x̂ j are not equivalent
Number of possible assignments (injective functions): l! , if l = 2|z|
41
Coding 1:
ẑk ∈ Z
x̂i ∈ X z = h(x) g(ẑk , y)
(ẑ1 , ẑ2 )k
000, 010, 100 00 z1 · z2 = m0 + m2 + m4 y1
001, 111 10 z1 · z2 = m1 + m7 y1 + y2
011, 101, 110 11 z1 · z2 = m3 + m5 + m6 y2
01 z1 · z2 = 1 not possible
Assignment table
z1 = z1 · z2 + z1 · z2 = m1 + m7 + m3 + m5 + m6
z2 = z1 · z2 + z1 · z2 = m3 + m5 + m6
z1 = h1 (x) = x1 · x2 + x3
z2 = h2 (x) = x1 · x2 · x3 + x1 · x2 · x3 + x1 · x2 · x3
Coding 2:
ẑk ∈ Z
x̂i ∈ X z = h(x) g(ẑk , y)
(ẑ1 , ẑ2 )k
000, 010, 100 00 z1 · z2 = m0 + m2 + m4 y1
001, 111 10 z1 · z2 = m1 + m7 y1 + y2
011, 101 11 z1 · z2 = m3 + m5 y2
110 01 z1 · z2 = m6 y2
Assignment table
z1 = z1 · z2 + z1 · z2 = m1 + m7 + m3 + m5
z2 = z1 · z2 + z1 · z2 = m3 + m5 + m6
z1 = h1 (x) = x3
z2 = h2 (x) = x1 · x2 · x3 + x1 · x2 · x3 + x1 · x2 · x3
42
Step 3 : Construct the composition function g(z, y)
Coding 1:
w = g(z, y) = z1 z2 · y1 + z1 z2 · (y1 + y2 ) + z1 z2 · y2
= z1 z2 · y1 + z1 z2 · y1 + z1 · y2
Since z1 z2 = 1, i.e. the value assignment (ẑ1 , ẑ2 ) = 01 can-

not be obtained from any value assignment x̂ to the input
variable, every product term which contains z1 z2 can be
added to w (internal don’t care values).
w = g(z, y) = z1 z2 · y1 + (z1 z2 · y1 ) + z1 z2 · y1 + z1 · y2
= z1 · y1 + z1 z2 · y1 + z1 · y2
Coding 2:
w = g(z, y) = z1 z2 · y1 + z1 z2 · (y1 + y2 ) + z1 z2 · y2 + z1 z2 · y2
w = g(z, y) = z1 z2 · y1 + z1 z2 · y1 + z1 · y2 + z2 · y2
Circuit realization for example (8) (Coding 1) :
w = f (x, y) = f (x1 , x2 , x3 , y1 , y2 )
w = x1 x3 · y1 + x3 · y2 + x1 x2 x3 · y1 + x2 x3 · y1 + x1 x2 · y2 + x1 x2 x3 · y1
y1
y2 g
x1 z1
w
x2 z2
x3
43
6 OBDD: Ordered Binary Decision Diagram

Every Boolean function f can be represented by a recursive Shannon expansion.
E.g. w = f (x, y) = x · fx + x · fx = β(x, fx , fx ) = β(x, f (1, y), f (0, y))
w = x · (y · fxy + y · fxy ) + x · (y · fxy + y · fx y ) (Difference to SOP form!)

w = β x, β y, f (1, 1), f (1, 0) , β y, f (0, 1), f (0, 0)
OBDD( f ) = (V, E) is a directed acyclic graph (dag) which recursively defines a Boolean
function f .
f (x, y) x Index 1 x root vertex

(rank) order of
x =1 x=0 1 0
variables
f (1, y) f (0, y) y Index 2 y y internal vertices
y =1 y = 0 y =1 y=0 1 0 1 0
f (1, 1) f (1, 0) f (0, 1) f (0, 0) f (1, 1) f (1, 0) f (0, 1) f (0, 0) terminal vertices
Shannon expansion
as root tree OBDD( f )
Example for OBDDs:

f (x) = x f (x) = x f (x, y) = x · y f (x, y) = x + y f (x, y) = x ⊕ y
x x x x x
1 0 1 0 1 0 1 0 1 0
1 0 0 1 y y y y
x = β(x, 1, 0) x = β(x, 0, 1) 1 0 1 0 0 1 0
1 = β(x, 1, 1) 0 = β(x, 0, 0)
x · y = β(x, y, 0) x + y = β(x, 1, y) x ⊕ y = β(x, y, y)
Example (9) : f (x, y, z) = x · y · z + y · z

OBDD( f ) = (V, E) with variable ordering z ≺ y ≺ x is a acyclic root
graph with a root vertex (vertex without a predecessor). Each non-
terminal vertex (vertex with at least one successor) v ∈ V has an at-
z 1 z tribute index index(v) ∈ {1, 2, 3} associated, which points to a variable
Index 1
from {x, y, z}, and two direct successors high(v) , low(v) ∈ V .
y 2 y 0 Each terminal vertex V has an attribute value value(v) ∈ {0, 1} associ-
ated.
x 3 x For the edges between non-terminal vertices
(v, high(v)) or (v, low(v)) ∈ E the following holds:
1 0
index(v) < index(high(v))
respectively index(v) < index(low(v))
OBDD: Ordered Binary Decision Diagram (1)
44
Simplification Rules (SR1, SR2) for tree-like OBDDs
SR1 : Specialized rule of resolution

For f (x, y, z) : IF f (1, y, z) = f (0, y, z) = g(y, z) ,
THEN f (x, y, z) = g(y, z)
Example:
vi vi vi
f (x, y, z) x vi vi
1 0 =⇒ =⇒ =⇒
g(y, z) g(y, z) g(y, z) y g(y, z) x
1 0 0 0 0
OBDD(g) OBDD(g) OBDD(g) g(1, z) g(0, z)
SR2 : Merging of equivalent Sub-OBDDs
vi vj vi vj vi vj
=⇒ =⇒
g(y, z) g(y, z) g(y, z) y
1 0
OBDD(g) OBDD(g) OBDD(g) g(1, z) g(0, z)
Comment : Exhaustive application of SR1, SR2 results in a Reduced OBDD (ROBDD).
Proposition by R. Bryant, CMU, 1986: Definition:
The representation of a Boolean func- Two ROBDDs are equivalent, IF:

tion f (x) by a ROBDD( f ) using a given a) Structural equivalence (Isomorphism)
variable ordering x1 ≺ x2 ≺ · · · ≺ xn is b) Same assignment of values to terminal
canonical. vertices
c) Same assignment of index values for non-
terminal vertices
It follows : ROBDD(g) ∼ ROBDD(h) ⇐⇒ g(x) = h(x)

x1 ≺ x2 ≺ · · · ≺ xn
45
Example (9) : f (x, y, z) = x · y · z + y · z , x ≺ y ≺ z
ROBDD( f ) , x ≺ y ≺ z
1 x x x 1
1 0 0 0
2 y y SR1 1 y SR2 1 y 2
=⇒ =⇒
3 z z z z z z 3
0 0 1 0
Example (2) : f (x, y, z) = x · y · z + x · y + y · z
ROBDD( f ) , x ≺ y ≺ z ROBDD( f ) , z ≺ y ≺ x
x z
1 0 1
y y y 0
z z x
1 0 1 0
Example (8) : f (x1 , x2 , x3 , y1 , y2 ) = x1 · x3 · y1 + x3 · y2 + x1 · x2 · x3 · y1

+ x2 · x3 · y1 + x1 · x2 · y2 + x1 · x2 · x3 · y1
ROBDD( f ) , x1 ≺ x2 ≺ x3 ≺ y1 ≺ y2
x1
1 0
x2 x2
x3 x3 x3
y1 + y2 y1 y1 y1
y2 y2
0 1
46
Since about 1990, the representation of Boolean functions by binary decision diagrams has
improved the effectiveness of design and verification of digital systems significantly.
Properties of ROBDDs:
+ Compact representation of Boolean functions

Only representation where size (number of vertices) usually does not grow exponentially
with the number of variables. Functions depending on hundreds of variables can be
represented.
+ Unique (canonical) representation

Equivalence of two Boolean functions can be shown by isomorphism of their respective
ROBDDs. Verification possible by equivalence checks.
+ Satisfiability check and tautology proof very simple

Satisfiability: at least one terminal vertex has value 1
Tautology: all terminal vertices have value 1 (function reduces to just one terminal
vertex in this case)
+ Fast (partial) evaluation of function f possible

Cofactors are easily accessible in ROBDD( f )
+ Negation of f trivial
Negation of values in terminal vertices
+ Boolean operations very simple on ROBDDs

Simple computation of e. g. ROBDD( f1 · f2 ) from ROBDD( f1 ) and ROBDD( f2 )
+ Composition of functions can be represented
+ Improvement of some discrete algorithms possible

E.g. for covering problems, solution time is proportional to size of problem
representation
+ Much larger state spaces of FSM can be treated
– ROBDD size strongly dependent on variable ordering

Determination of a favorable variable ordering not always easy
– ROBDD size grows exponentially with number of variables for some functions
E.g. for multiplier functions
– SOP representation closer to implementation for some realization technologies (e. g. PLDs)
47
7 Synthesis of Sequential Circuits

Sequential Circuit
(example)
x(t) 11000110... 00101001... y(t)
s(t) z(t)
Q D
D flipflop
clock
Time diagram:
Clock period t 0 1 2 3 4 5 6 7 ...
Input signal x(t) 1 1 0 0 0 1 1 0 ...
Output signal y(t) 0 0 1 0 1 0 0 1 ...
z(t) = y(t) = s(t) + x(t) , t ∈ {0, 1, 2, 3, . . . }

State: s(t) = z(t − 1) = y(t − 1) , y(−1) , s(0)
Next State: z(t) = s(t + 1)
y(t) = x(t) + y(t − 1)
Iterative combinational circuit

(Alternative to sequential circuit)
x(4) 0
x(3) 0
x(2) 0
1 1 y(4)
x(1)
1 0 y(3)
x(0)
∗ 1 y(2)
s(0)
0 y(1)
0 y(0)
y(t) = f (s(0), x(0), x(1), . . . , x(t)) , t ∈ {0, 1, 2, 3, . . . }

(Circuit with memory!)
Synthesis of Sequential Circuits (1)
48
Finite State Machine FSM (as a model of sequential circuits)

(Automaton with output)
FSM (Mealy automaton)

n (primary) m (primary)
inputs x1 y1 outputs
x2 .. combinational .. y2
x = (x1 , x2 , . . . , xn ) . . y = (y1 , y2 , . . . , ym )
xn circuit ym
x̂ ∈ B n ŷ ∈ B m
s1 λ(s, x) = y z1
s = (s1 , s2 , . . . , sr ) s2 δ(s, x) = z z2 z = (z1 , z2 , . . . , zr )
.. ..
ŝ ∈ B r sr . . zr ẑ ∈ B r
r state signals s(t) = z(t − 1) r “next”

state signals
state
memory
registers
clock
FSM = (S, I, O , δ, λ, S0 ) 6-tuple

1) S = {ŝ0 , ŝ1 , . . . , ŝ2r −1 } = Br : finite set of states, 0 < |S| < ∞
= {S0 , S1 , . . . , S2r −1 }
2) I = {x̂0 , x̂1 , . . . , x̂2n −1 } = B n : set of input patterns
= {X0 , X1 , . . . , X2n −1 } input alphabet
3) O = {ŷ0 , ŷ1 , . . . , ŷ2m −1 } = B m : set of output patterns
= {Y0 ,Y1 , . . . ,Y2m −1 } output alphabet
4) δ : S×I → S , (s, x) → z : (state-) transition function
5) λ : S×I → O , (s, x) → y : output function
6) S0 ∈ S : initial state
Types of machines:
Mealy automaton λ : S × I → O , y = λ(s, x)
Moore automaton λ : S → O , y = λ(s)
49
General description of FSM
X j : Input pattern Yl : Output pattern

Si : State Sk : Next state i, j, k, l ∈ {0, 1, 2, 3, . . . }
δ ··· Xj · · · λ ··· Xj · · ·
... ... ... ...
Si · · · Sk · · · Sj ··· Yl · · ·
... ... ... ...
state transition table, state table output table
δ : S×I → S λ : S×I → O
Sk = δ(Si , X j ) Yl = λ(Si , X j )
state transition function, next-state function output function
µ : S×I → S×O
(Sk ,Yl ) = µ(Si , X j )
state output function
µ ··· Xj ···
... ...
Si · · · (Sk ,Yl ) · · · X j /Yl

... ... Si Sk
state output table, state table state transition graph STG

state diagram
50
Example (10): I = O = {0, 1}, n = m = 1; S = {S1 , S2 , S3 }, S0 = S1

(S j , ŷ) = µ(Si , x̂), i, j = 1, 2, 3
next
Reset 0/0 x̂ state state ŷ
µ x=0 x=1 S1 0 S1 S1 0
0/0 1 S1 S2 1
S1 (S1 , 0) (S2 , 1) 1/1
≡ 1/1 ≡ 0 S2 S1 0
S2 (S1 , 0) (S3 , 0)
S3 (S3 , 0) (S1 , 1) S3 S2 1 S2 S3 0
1/0
0 S3 S3 0
state output table
0/0 1 S3 S1 1
STG
cube table
x s1 s2 z1 z2 y
0 00 00 0
y = x · s1 · s2 + x · s1 · s2 = x · s2
1 00 01 1 state z2 = x · s1 · s2
0 01 00 0 coding
z1 = x · s1 · s2 + x · s1 · s2
1 01 10 0 S1 , 00 , s1 · s2
+ x · s1 · s2 + x · s1 · s2
0 10 10 0 S2 , 01 , s1 · s2 | {z }
S3 , 10 , s1 · s2 optional
1 10 00 1
z1 = x · s2 + x · s1
0 11 (1)∗ ∗(0) ∗(0)
1 11 (1)∗ ∗(0) ∗(0)
coded cube table
FSM for example (10): FSM processes strings (words, concatenation

100101 of symbols). Starting with the initial state
y
x 110101 S1 , 00 , s1 · s2 , e.g. the string
z2 str(x) = x(0) ◦ x(1) ◦ x(2) ◦ x(3) ◦ x(4) ◦ x(5)
= 110101
is transformed into the string
z1 str(y) = y(0) ◦ y(1) ◦ y(2) ◦ y(3) ◦ y(4) ◦ y(5)
= 100101
one symbol at a time. The sequential system cycles
through a number of system states during this
s1 Q D processing.
str(S) = S(0) ◦ S(1) ◦ S(2) ◦ S(3) ◦ S(4) ◦ S(5) ◦ S(6)
s2 Q D
= S1 S2 S3 S3 S1 S1 S2 (see STG)
clk Remark: State sequences or strings with an initial state describe

paths in the state transition graph STG.
51
Operations on strings
Assumption: I = O = {0, 1}, n = m = 1, Extension to n > 1 or m > 1 quite simple:

x→x or y → y
Notation : x(t) , xt , y(t) , yt , S(t) , St ;

String : str(x) = x(0) ◦ x(1) ◦ x(2) ◦ . . . , x0 x1 x2 . . .
Length of string : k = |str(x)|
String of length k : str(x)|k
Empty string : ε , ε = str(x)|0 , e.g. ε ◦ str(x) = str(x)
Extension of interpretation of y = λ(Si , x) to str(y) = λ (Si , str(x))
y0 y1 y2 = λ(S0 , x0 x1 x2 ) = λ(S0 , x0 ) ◦ λ δ(S0 , x0 ), x1 x2 = y0 ◦ λ(S1 , x1 x2 )

e.g.
= y0 y1 ◦ λ(S2 , x2 )
x0 x1 x2
x0 /y0 x1 /y1 x2 /y2
S0 S1 S2 S3
A directed path in state transition graph STG

x̂/ŷ ∈ {0/0 , 0/1 , 1/0 , 1/1}
Extension of interpretation of St+1 = δ(St , xt ) to Sk = δ S0 , str(x)|k

e.g. S0 S1 S2 S3 = S0 ◦ δ(S0 , x0 ) ◦ δ(S0 , x0 x1 ) ◦ δ(S0 , x0 x1 x2 )
: S0 , str(x), ε

Initial configuration of FSM
Final configuration of FSM : (S∗ , ε, str(y))
Configuration, situation of FSM : (St , str(x), str(y)) , St : current state
str(x) : current input string
str(y) : current output string
Configuration transition: (Relation)
e.g. S0 , x0 x1 x2 x3 , ε S1 , x1 x2 x3 , y0

2
S2 , x2 x3 , y0 y1

4
S4 , ε, y0 y1 y2 y3

k
Sk , xk xk+1 . . . , y0 y1 y2 . . . yk−1

∗
S∗ , ε, y0 y1 y2 . . . y∗

52
State Minimization
The first step in state minimization is to eliminate non-reachable states.
Definition: A state S j is reachable from an initial state Si , if a directed path from Si

to S j exists in the state transition graph.
The key task of state minimization is to reduce the number of states by merging equivalent
states.
Definition of equivalence of two states Si and S j :
Si ∼ S j ⇐⇒ λ(Si , str(x)) = λ(S j , str(x)) , for all str(x)

Equivalent (non identical output patterns for identical
differentiable) input patterns, originating from Si and S j
states
The equivalence relation ∼ partitions the state set S into disjoint subsets (equivalence classes).
Si and S j are elements of an equivalence class Kl of the partition Π of S. Π ⊆ P(S)
Π(S) = {K1 , . . . , Kl , . . . , KL } ; Si , S j ∈ Kl ,
S
l Kl =S
Remark: Si 6∼ S j ⇐⇒ there exists a str(x), such that λ(Si , str(x)) 6= λ(S j , str(x))
differentiable different output patterns
states
Definition of k-equivalence of two states Si , S j :
k
Si ∼ S j ⇐⇒ λ(Si , str(x)|k ) = λ(S j , str(x)|k ) , for all str(x)|k
(k) (k) (k) (k)

Π(k) (S) = {K1 , . . . , Kl , . . . , KL } ; Si , S j ∈ Kl
1
Si ∼ S j ⇐⇒ λ(Si , x0 ) = λ(S j , x0 ) , for all x0 ∈ {1, 0}
1
Si ∼ S j ⇐⇒ [λ(Si , 0) = λ(S j , 0)] ∧ [λ(Si , 1) = λ(S j , 1)]
The iterative computation of k-equivalent (or simply: equivalent) states starts with the
computation of the 1-equivalent states, since:
0
Si ∼ S j ⇐⇒ λ(Si , ε) = λ(S j , ε) ⇐⇒ ε = ε , for all Si , S j ∈ S , Π(0) = {S}
coarsest partition of S
53
Example (11): I = O = {0, 1}, n = m = 1; S = {S1 , S2 , S3 , S4 }, S 0 = S1

(S j , ŷ) = µ(Si , x̂), i, j = 1, 2, 3, 4
0/0
µ x=0 x=1
S1 S4
S1 (S4 , 0) (S2 , 1) 0/0
1/1 1/1
S2 (S4 , 0) (S3 , 0) 1/1 0/0
≡
S3 (S3 , 0) (S1 , 1) S3 S2
S4 (S1 , 0) (S2 , 1) 1/0
state output table 0/0

STG
From the state output table we obtain the following relations:

1 1 1
S1 ∼ S3 ⇐⇒ [0 = 0] ∧ [1 = 1] , S1 ∼ S4 (S3 ∼ S4 )
1
l 1 1 1
S1 ∼ S2 ⇐⇒ [0 = 0] ∧ [1 = 0] , S1 6∼ S2 (S3 6∼ S2 , S4 6∼ S2 )
false
n o
Π(1) = {S1 , S3 , S4 }, {S2 }
2 1 1 1
Si ∼ S j ⇐⇒ [Si ∼ S j ] ∧ [δ(Si , 0) ∼ δ(S j , 0)] ∧ [δ(Si , 1) ∼ δ(S j , 1)]
2 1 1 1
e.g. S1 ∼ S4 ⇐⇒ [S1 ∼ S4 ] ∧ [S4 ∼ S1 ] ∧ [S2 ∼ S2 ]
2
l
1 1 1 2
S1 ∼ S3 ⇐⇒ [S1 ∼ S4 ] ∧ [S4 ∼ S3 ] ∧ [S2 ∼ S1 ] , S1 6∼ S3
n false o
(2)
Π = {S1 , S4 }, {S3 }, {S2 }
3 2 2 2
S1 ∼ S4 ⇐⇒ [S1 ∼ S4 ] ∧ [δ(S1 , 0) ∼ δ(S4 , 0)] ∧ [δ(S1 , 1) ∼ δ(S4 , 1)]
2 2 2
⇐⇒ [S1 ∼ S4 ] ∧ [S4 ∼ S1 ] ∧ [S2 ∼ S2 ]
Π(3) = Π(2) = Π(S)
Result: state S1 and S4 are equivalent and can be merged in STG (see example (10)!).
µ x=0 x=1 0/0

S1 , S4
S1 (S4 , 0) (S2 , 1)
S4 (S1 , 0) (S2 , 1)
2 ≡ 1/1 1/1 0/0
S3 (S3 , 0) (S1 , 1) 1/1
1 0/0
S2 (S4 , 0) (S3 , 0) S3 S2
1/0
state output table STG
54
Iterative checking for equivalent states in an FSM:
k+1 k k
Si ∼ S j ⇐⇒ [Si ∼ S j ] ∧ [δ(Si , x0 ) ∼ δ(S j , x0 )] , for all x0 ∈ {0, 1}
k+1 k k k
Si ∼ S j ⇐⇒ [Si ∼ S j ] ∧ [δ(Si , 0) ∼ δ(S j , 0)] ∧ [δ(Si , 1) ∼ δ(S j , 1)]
k+1 1 k k
Comment: Si ∼ S j ⇐⇒ [Si ∼ S j ] ∧ [δ(Si , 0) ∼ δ(S j , 0)] ∧ [δ(Si , 1) ∼ δ(S j , 1)]
Determination of equivalent states:
Π = Π(k) , IF Π(k+1) = Π(k) , with k ≤ |S| − 1
Additional remark: Π(k) is a refinement of Π(k−1) ; Π(k) , Π(k−1) , . . . , Π(2) , Π(1)

1 2 k
Because Si 6∼ S j =⇒ Si 6∼ S j =⇒ . . . =⇒ Si 6∼ S j =⇒ Si 6∼ S j
k k−1 1
Si ∼ S j =⇒ Si ∼ S j =⇒ Si ∼ S j =⇒ . . . =⇒ Si ∼ S j
Example (12): Completely specified FSM; I = O = {0, 1}, n = m = 1;

S = {A, B,C, D, E, F, G}
µ x=0 x=1
Π(1) =

A (E, 0) (C, 0) {A, D, G, F}, {B,C}, {E}
2 00 01 10 ŷ−assignment
D (G, 0) (A, 0)
···························· 3 Π(2) =

{A}, {D, G}, {F}, {B,C}, {E}
G (D, 0) (G, 0)
2 2
l
1 1 1
F (E, 0) (D, 0) e.g. A ∼ D ⇐⇒ [A ∼ D] ∧ [E ∼ G] ∧ [C ∼ A]
1 false false
B (C, 0) (A, 1)
···························· 3 2 1 1 1
D ∼ G ⇐⇒ [D ∼ G] ∧ [G ∼ D] ∧ [A ∼ G]
C (B, 0) (G, 1)
1
Π(3) =

E (F, 1) (B, 0) {A}, {D}, {G}, {F}, {B}, {C}, {E}
finest decomposition of S
state output table
(appropriately sorted)
Result : All states can be pairwise differentiated by appropriate strings with k ≤ 3.

Remark : Typically, the state output table will be sorted again after each partitioning step.
55
General comments on machine models
Machine types:
Mealy Automaton λ: S × I → O , Yl = λ(Si , X j )
Moore Automaton λ: S → O , Yl = λ(Si )
Medwedew Automaton λ : I → O , Yl = λ(X j )
Properties of machines:
completely specified – incompletely specified
simplified
minimal Sj
x=1
deterministic – non-deterministic
Si
x=1
Sl
{S j , Sl } = δ({Si }, 1)
In a non-deterministic machine the

state transition is not necessarily un-
ambiguous anymore.
FSM design flow:

Specification
State minimization
Verification, testing
State coding
Input and output coding
Logic minimization
Timing optimization
56
Literature on Logic Synthesis

G. De Micheli: Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994.
S. Devadas, A. Ghosh, K. Keutzer: Logic Synthesis, McGraw-Hill, 1994.
G.D. Hachtel, F. Somenzi: Logic Synthesis and Verification Algorithms, Kluwer, 1996.
Literature (1)
57
II. Simulation of Digital Circuits
1 Introduction
• Why use simulation?
1. Hardware design validation (logic function, timing, power consumption)
2. Fault simulation (fault coverage)
3. Early co-validation of system hardware and software
• Simulation levels:
Abstraction levels
System
Algorithm
Register-Transfer
Logic
Switch-Level
Circuit
Device
Process Complexity
1 10 102 103 104 105 106 107 108 109 1010 # Transistors
• Alternative/Enhancement: Formal (mathematical) verification

2 Logic Simulation
• Overview of simulation system:
Component models
- logic function
- timing behavior
Netlist
Simulator
Stimuli
Signal traces
Logic Simulation (1)
59
Circuit Modeling
The circuit is represented by basic components of the simulation system

Modeling functionality and timing:
∆ : basic time unit

x τ y
τ : (signal-) delay
τd = n · ∆ : propagation delay (gate delay)
yt = xt−τ
τw = m · ∆ : wire delay
Delay dependent effects:
a) Race: “run“ between signal changes on different wires leading to a single

component
b) Hazard: (short) signal pulse does not conform to the pure logic function of
a circuit; caused by internal delays
Example with signal traces :
z1 z2 z3 z5
x 2∆ 2∆ 2∆ 2∆
2∆ y
z4
2∆
∆
x 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
z1 1 1 1 1 0 0 0 0 0 1 1 1 1
z2 0 0 0 0 1 1 1 1 1 0 0 0 0
z3 , z4 1 1 1 1 0 0 0 0 0 1 1 1 1
z5 0 0 0 0 1 1 1 1 1 0 0 0 0
y 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
Hazard
60
Simulation of functional and timing behavior
A) Logic evaluation (purely functional simulation)

Example:
z5
x
y
z4
timing diagram:
x, z5 0 0 0 1 1 1 0 0 0 Boolean function:
z4 1 1 1 0 0 0 1 1 1 y = x·x = x·x = 0
y 0 0 0 0 0 0 0 0 0
typical signal modeling:

– Boolean logic {’0’, ’1’}
– Three-valued logic {’0’, ’1’, ’X’}
– IEEE Standard logic {’U’, ’X’, ’0’, ’1’, ’Z’, ’W’, ’L’, ’H’, ’-’}
B) Timing evaluation (timing verification, race analysis)

”Logic” is not considered
x 2∆ 2∆ 2∆ 2∆
2∆ y
2∆
fan-in without specification
of gate function
Assuming a signal change on x at t = 0 , the following ”time table” results

for the propagation of this signal change to the circuit output.
0 2 4 6 8
x 6 .. 8 8 ..10
6 y
At the output, the maximal transient uncertainty is now known

(important to determine the clock frequency of synchronous circuits).
61
Simulation with slew rate (slope) uncertainty
A signal change does not have an ideal edge (infinite slope). Therefore, a transition period
results, during which the signal value is undefined. In simulation this is represented by a new
signal ”X”.
Example:
z1 z2 z3 z5
x 2∆ 2∆ 2∆ 2∆
2∆ y
z4
2∆
Let the signal uncertainty be one basic time unit:
x 0 0 0 X 1 1 1 1 1 1 1 1 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
z1 1 1 1 X 0 0 0 X 1 1 1
z2 0 0 0 X 1 1 1 X 0 0 0
z3 , z4 1 1 1 X 0 0 0 X 1 1 1
z5 0 0 0 X 1 1 1 X 0 0 0
y 0 0 0 0 0 0 0 0 X 1 X 0 0 0
Hazard
Truth tables with the new signal value ”X”:
AND 0 1 X OR 0 1 X NOT
0 0 0 0 0 0 1 X 0 1
1 0 1 X 1 1 1 1 1 0
X 0 X X X X 1 X X X
62
Simulation with delay uncertainty
Let the minimum and maximum delay of a gate be known. In between the output value is
undefined
x τd y x (ideal) 0 0 1 1 1 1 1
y 1 1 1 XX0 0
e.g. τdmin = ∆
τdmax = 3∆
Example:
z1 z2 z3 z5
x τd τd τd τd
z6
z4
τd y
τdmin = 3∆ τd
τdmax = 4∆
x 0X 1 1 1 1 1 1X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
z1 1 1 1 1XX 0 0 0 0 0XX 1 1 1
z2 0 0 0XXX 1 1 1 1XXX 0 0 0
z3 , z4 1 1 1XXXX 0 0 0XXXX 1 1 1
z5 0 0 0X X 1 1X X 0 0 0
z6 0 0X 0 0X X 0 0 0
y 0 0XX 0 0X X 0 0
Hazard possible
This method results in a worst-case analysis, due to the increasing uncertainty range.
typical modeling of timing behavior:

Gate and wire delays Pin-to-pin delays
τd τw2
τw1
63
3 Simulation methods
Simulation program
a) Modeling circuit components using basic elements (primitives) of the simulation system
b) Circuit replication (compilation or list creation)
c) Simulation execution
Compiler driven simulation

The circuit under test is compiled into an executable program. In each simulation cycle, the
logic function of the complete circuit is evaluated, based on the input signals and the internal
circuit states. (registers, feedback signals).
Very fast, usually no timing analysis (zero delay simulation).
Event driven simulation
Event driven simulation is based on signal changes within the circuit. In each simulation step,
components are evaluated only if a signal change occurs on their corresponding inputs. Signal
changes are coded as events.
• Signal change: val(z,tν ) 6= val(z,tν−1 )

• Event: A component evaluation at simulation time tgen causes that signal z is set to a new
value val(z,texe ) at simulation time texe .
E = (z, val(z,texe ),tgen ,texe ) z: signal name
val(z,texe ): value of signal z at time texe
tgen : generation time of event
texe : execution time of event
texe − tgen = τ: imposed delay
• Simulation cycle:
event
find evaluate
execution event
target these
(change generation
components components
signal values)
signal sensitivity process signal

update list evaluation assignment
zero delay events
+ 1 delta cycle
advance simulation time to next time stamp

(delayed events, event queue)
next transactions in event queue
(italic font indicates VHDL simulation terminology)
Simulation methods (1)
64
Example simulation run: Multiplexer

• Circuit: Nand_a Delays: τ = 2
A S1
Inv τ Nand_c
Sel τ Seln τ Q
B τ S2
Nand_b
• Simulation run:
evaluated new events

t A B Sel Seln S1 S2 Q components (signal, val,tgen ,texe )
0 ’0’ ’0’ ’1’ ’0’ ’1’ ’1’ ’0’ initial state (A, ’1’, 0, 20);
(stimuli) (B, ’1’, 0, 10);
(Sel, ’0’, 0, 30)
10 ’1’ Nand b (S2 , ’0’, 10, 12)
12 ’0’ Nand c (Q, ’1’, 12, 14)
14 ’1’ – –
20 ’1’ Nand a –
30 ’0’ Inv, Nand b (Seln , ’1’, 30, 32);
(S2 , ’1’, 30, 32)
32 ’1’ ’1’ Nand a, Nand c (S1 , ’0’, 32, 34);
(Q, ’0’, 32, 34)
34 ’0’ ’0’ Nand c (Q, ’1’, 34, 36)
36 ’1’ – –
• Signal waveforms:
t 0 10 12 14 20 30 32 34 36
1
A 0
1
B 0
1
Sel 0
1
Seln 0
1
S1 0
1
S2 0
1
Q 0
Hazard
Simulation methods (2)
65
4 VHDL
VHSIC Hardware Description Language (VHSIC = Very High Speed Integrated Circuit)
• widely used hardware description language for simulation, documentation, and synthesis
• standardized format for libraries and interoperability of design tools
• similar to programming language; special extensions for modeling hardware:

– Concurrency (description of concurrent processes)
– Timing model (delays; event driven simulation)
• supports modeling of hardware at different levels of abstraction
• supports behavioral and structural description styles
VHDL model of a Multiplexer

1. Specification:
Sel A B Inputs: A, B, Sel
Output: Q
MUX Sel = ´0´ ⇒ Q = A

Sel = ´1´ ⇒ Q = B
2. Behavioral description (dataflow, zero delay):

(A) Circuit interface: (B) Circuit implementation:
ENTITY Multiplexer IS ARCHITECTURE dataflow OF Multiplexer IS

PORT(A, B, Sel: in bit; BEGIN
Q: out bit); Q <= A WHEN Sel = ’0’ ELSE B;
END Multiplexer; END dataflow;
Sel A B
MUX Architecture
Entity dataflow
Black Box Multiplexer
VHDL (1)
66
3. Structural description:
Nand_a
A S1
Inv Nand_c
Sel Seln Q
B S2
Nand_b
(A) Circuit interface: (B) Circuit implementation:
ENTITY Multiplexer IS LIBRARY BasicGates;

PORT(A, B, Sel: in bit; USE BasicGates.ALL;
Q: out bit);
END Multiplexer; ARCHITECTURE structure OF Multiplexer IS
COMPONENT Inverter
PORT(i: in bit; o: out bit);
END COMPONENT;
COMPONENT Nand2
PORT(i1,i2: in bit; o: out bit);
END COMPONENT;
SIGNAL Sel_n, S1, S2 : bit;
BEGIN
Inv: Inverter PORT MAP (Sel, Sel_n);
Nand_a: Nand2 PORT MAP (A, Sel_n, S1);
Nand_b: Nand2 PORT MAP (B, Sel, S2);
Nand_c: Nand2 PORT MAP (S1, S2, Q);
END structure;
4. Validation by simulation:
Testbench:
• applies stimuli to circuit inputs B

Sel A
• monitors circuit outputs
Test−
• checks correctness via assert statements (optional) bench MUX
Configuration:
Q
• binding of architectures to entities
• flexible mechanism for using alternative implementations
VHDL (2)
67
Testbench for Multiplexer
Interface description:
ENTITY Testbench IS
--
-- no inputs, no outputs.
--
END Testbench;
Implementation (instantiation of multiplexer as COMPONENT:

ARCHITECTURE functiontest OF Testbench IS
COMPONENT Multiplexer
PORT(A, B, Sel: in bit;
Q: out bit);
END COMPONENT;
SIGNAL A, B, Sel, Q: bit;
BEGIN
MUX_1: Multiplexer PORT MAP(A, B, Sel, Q);
A <= ’0’, ’1’ after 20 ns, ’0’ after 60 ns, ’1’ after 100 ns;
B <= ’1’, ’0’ after 30 ns, ’1’ after 70 ns;
Sel <= ’0’, ’1’ after 40 ns, ’0’ after 80 ns;
END functionstest;
Configuration (Entity / Architecture Binding):

CONFIGURATION Test_Setup OF Testbench IS
FOR functiontest
FOR MUX_1: Multiplexer USE ENTITY WORK.Multiplexer(dataflow);
END FOR;
END FOR;
END Test_Setup;
1
A
0
1
B
0
1
Sel
0
1
Q
0
0 20 40 60 80 100 120 t(ns)
VHDL (3)
68
Processes:
• Statements with a PROCESS are executed sequentially within an infinite loop.
• All Processes are concurrent.
• A PROCESS must have either a WAIT-statement or a Sensitivity-List.
• Each signal assignment outside of a PROCESS will be modified into a new PROCESS
by the simulator.
• In a PROCESS variables can be used in addition to signals.
Example: Clock Generator

Example for signal assignment Example for SENSITIVITY LIST
ARCHITECTURE Simple OF CLKgen IS ARCHITECTURE SList OF CLKgen IS
BEGIN BEGIN
CLK <= NOT CLK AFTER 10 ns; PROCESS(CLK)
END Simple; BEGIN
CLK <= NOT CLK AFTER 10 ns;
END PROCESS;
END SList;
Example for WAIT ON-statement Example for WAIT FOR-statement
ARCHITECTURE Wait1 OF CLKgen IS ARCHITECTURE Wait2 OF CLKgen IS
BEGIN BEGIN
PROCESS PROCESS
BEGIN BEGIN
CLK <= NOT CLK AFTER 10 ns; CLK <= NOT CLK;
WAIT ON CLK; WAIT FOR 10 ns;
END PROCESS; END PROCESS;
END Wait1; END Wait2;
Signals and Variables:

Signals:
• Have temporal ”memory”. Future signal values are planner by entry of a transaction
(wn , tn ) in the signal driver.
(wn : planned signal value, tn : timestamp) (transaction 6= event)
• In value assignments “<= waveform” the new value will be planned. It will be incurred
only when the PROCESS will be suspended (during the signal update phase).
Variables:
• Do not have temporal memory.

• In value assignments “:=expression” the new value will be incurred immediately.
VHDL (4)
69
Delay Mechanisms:
Transport-Delay: (signal <= transport waveform;)

• Modelling of an ideal component with unlimited bandwidth.
• Rule for insertion of new transaction (wn , tn ) into the signal driver:
– All (later) transactions (wi , ti ) with ti ≥ tn will be deleted.
– The new transaction (wn , tn ) will be appended at the end of the list.
Inertial-Delay: (signal <= waveform;)

• Modelling of real components with finite bandwidth.
(impulses which are shorter than the component’s delay, will be suppressed.)
• Rule for insertion of a new transaction (wn , tn ) into the signal driver:
– All (later) transactions (wi , ti ) with ti ≥ tn will be deleted.
– The new transaction (wn , tn ) will be appended at the end of the list.
– Transactions (wi , ti ) within the interval tnow ≤ ti ≤ tn will be deleted if wi 6= wn .
Event-driven simulation:
Execution of all transactions at time step tn in ∆-cycles. Advancing the simulation time
tn → tn+1 when all transactions at time tn have been executed.
∆-cycle:
• Signal-Update-Phase:
– Execution of all transactions for the current time step.
– If a transaction changes a signal value, this is an event.
• Process-Evaluation-Phase:
– Processes, for which an event is present, will be executed.
– Value assignments to signals will be scheduled in the signal driver.
Signal- Signal-
Update Update
+∆ +∆
es
ycl
Process- Process-
∆-c
Evaluation Evaluation
tn tn+1 Time
VHDL (5)
70
Literature on Logic Simulation

M.R. Lightner: Modeling and Simulation of VLSI Digital Circuits, Proceedings of the
IEEE, Vol. 75, No. 6, S. 786-796, June 1986.
P.J.Ashenden: The Designer’s Guide to VHDL, Morgan Kaufmann, 2002.
P.J.Ashenden: VHDL Cookbook, 1990.

Available on WWW.
VHDL (6)
71

EDA Lecture Logic Synthesis

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

EDA Lecture Logic Synthesis

Uploaded by

Copyright:

Available Formats

INSTITUTE FOR ELECTRONIC DESIGN AUTOMATION

TECHNISCHE UNIVERSITÄT MÜNCHEN

Electronic Design Automation

Logic Synthesis, binary Boolean functions, optimization of combinational circuits (two-level,

Logic Simulation, event-driven simulation, modelling and simulation using VHDL.

Bn n-dimensional Boolean Space 12

1 Logic Synthesis Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Binary Boolean Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Synthesis of Two-Level Combinational Circuits . . . . . . . . . . . . . . . . . 21

4 Heuristic Minimization of Two-Level Combinational Circuits . . . . . . . . . . 34

5 Synthesis of Multi-Level Combinational Circuits . . . . . . . . . . . . . . . . 37

6 OBDD: Ordered Binary Decision Diagram . . . . . . . . . . . . . . . . . . . . 44

7 Synthesis of Sequential Circuits . . . . . . . . . . . . . . . . . . . . . . . . . 48

II. Simulation of Digital Circuits 59

Behavioral description: Design Requirements:

Typical Design Flow Steps

Testing Integrated Circuit

Behavioral System level Structural

System Spec. CPU, Memory

Behavior Structure Geometry

1 Logic Synthesis Basics

Logical (Signal-) Variable : x, y, . . .

Important Logical Operations

Expression Name Gate symbol

Value assignment Truth values

Logic Synthesis Basics (1)

A) Laws of binary Boolean Algebra (Switching Algebra)

(1) x·y = y·x ; x+y = y+x Commutativity

(4) x·x = x ; x+x = x Idempotence

(6) x·1 = x ; x+0 = x Neutral Element

(7) x·0 = 0 ; x+1 = 1 Dominance

(8) x·x = 0 ; x+x = 1 Negation

(9) x = x Double Negation

(10) x·y = x+y De Morgan

Logic Synthesis Basics (2)

B) Laws of Set Algebra

(1) A∩B = B∩A ; A∪B = B∪A Commutativity

(2) (A ∩ B) ∩C = A ∩ (B ∩C) Associativity

(3) A ∩ (B ∪C) = (A ∩ B) ∪ (A ∩C) Distributivity

(4) A∩A = A ; A∪A = A Idempotence

(6) A ∩ G = A ; A ∪ 0/ = A Neutral Element

(9) (A) = A Double Complement

(10) A∩B = A∪B De Morgan

Logic Synthesis Basics (3)

B n : n-dimensional Boolean Space

B = {0, 1}; x̂ ∈ B n ; |B n | = 2n ; B n = {x̂0 , . . . , x̂2n −1 }

e. g. B 3 = B × B × B = {(0, 0, 0), (0, 0, 1), . . . , (1, 1, 1)}

Notation : (1, 0, 1) , (101) , 101 = x̂5

Literal li (positive or negative) : xi or xi

Logic Synthesis Basics (4)

Minterm m j , 0-Cube, : m j = ∏ li , {li ∈ L0 | i ∈ I0 }

Cube c j in B n , d-cube, : c j = ∏ li , {li ∈ L0 | i ∈ I j }

Dimension d j of cube c j : d j = |I0 | − |I j |

Example : I0 = {1, 2, 3}; |I0 | = 3

Notation : mκ = x1 x2 x3 , {110} ; |mκ | = 2dκ = 20 = 1

x1 x2 x3 , {x1 , x2 , x3 } ; {110} , 110

∗ or − : Don’t Care Value, DC Value

ci ∈ {0, 1, ∗}n ; |{0, 1, ∗}n | = 3n ; mκ ∈ {0, 1}n ; |{0, 1}n | = 2n

Set MC of all cubes in B n : MC = {c0 , . . . , c j , . . . , c3n −1 }

MOC ⊆ MC; |MC| = 3n ; |MOC| = 2n

Logic Synthesis Basics (5)

2 Binary Boolean Functions

sup( f ) = set(x) = {x1 , . . . , xi , . . . , xn } : Set of variables