KRISHNA INSTITUTE OF ENGINEERING & TECHNOLOGY, GHAZIABAD

Department of AI
QUESTION BANK
Course: B.Tech Semester: III
Subject: COA Sub. Code: BCS-302

1. What is CLA? What is the role of Multiplexer and Decoder?

2. What do you understand by microprogram sequencer?
3. What is locality of reference?
4. Write short note on Bus Arbitration?
5. Write the differences between RISC and CISC.
6. What is the difference between 2D and 2.5D memory organization?
7. Explain the term cycle stealing?

8. Describe the functioning of Micro-programmed control unit with suitable diagram

and explain Micro instruction format?
9. Draw flow chart for Booth multiplication algorithm. Evaluate step by step
(-15) X (-13) using Booth Algorithm.
10. Consider the following page references
1 2 3 4 2 1 5 6 2 1 2 3 7 6 3 2
Calculate the page fault and show the resident pages in main memory for the above
string with the help of LRU and FIFO page replacement algorithm (frame size = 3).
Also calculate the hit ratio for each page replacement algorithm.
11. Explain DMA controller with the help of its block diagram? Discuss the different
modes of data transfer.
12. a) Represent (-307.1875)10 in single precision and double precision formats.
b) Write Short notes on Subroutine.
c) What do you mean virtual memory? An address space is specified by 24 bits and
the corresponding memory space by 16 bits.
(i) How many words are there in the address space?
(ii) How many words are there in the memory space?
(iii) If a page consists of 2K words, how many pages and blocks are there in the
system?
13. b)Discuss the different mapping techniques used in cache memories.

A two-set associative cache memory uses blocks of 4 words? Cache can

accommodate a total of 2048 words from memory. The memory size is 128k *32.
i) Formulate all information required to construct the cache memory?
ii) What is the size of cache memory?

a) A digital computer has a memory unit of 64K x 16 and a cache memory of 1 K

words. The cache uses direct mapping with a block size of four words.
(i) How many bits are there in the tag index block and word fields of the address
format?
(ii)How many bits are there in each word of cache and how are they divided?
Include a valid bit.
(iii)How many blocks can the cache accommodate? Draw suitable diagrams
wherever needed.
b) How many 128 X 8 RAM and 512 X 8 ROM chips are needed for a computer
system having 4096 byte RAM and 4096 bytes ROM? List memory address map and
indicate what size decoders are needed. How many RAM chips and ROM chips are
needed? Draw the memory chip connection diagram also.
 a) What do you mean by asynchronous data transfer? Explain strobe control and
handshaking mechanism.
b) Draw and explain the block diagram of DMA controller.

a) What are interrupts? How are they handled? Discuss the types of interrupt.
b) Differentiate between following:
i) Programmed I/O V/S Interrupt driven I/O.
ii) Isolated and Memory mapped I/O
a) Draw the flow chart of memory reference instructions format? An instruction is
stored at location 300 with its address field at location 301. The address field has the
value 400. A processor register R1 contains the number 200. Evaluate the effective
address if the addressing mode of the instruction is: (a) direct (b) immediate (c)
Relative (d) Register indirect € Index with R1 as the index register.
b) Explain the organization of Microprogrammed Control Unit in detail. Write a
program to evaluate arithmetic expression X = (A+B) * (C+D) using a general
register computer with three, two, one, zero address instructions.