Shri Saibaba College, Shirdi

FYBSc(Computer Science) Electronics

ELC 112- Principles of Digital Electronics

SPPU Examinations OCT/ NOV-2022

Model Answer
Q. Sub Marking
Answer
No. Q.N. Scheme
Q1 1 Mark
Solve any five of the following
Each
a) Define propoation delay.
Answer:- The time required to change the output from one logic state to another logic
1M
state after input is applied, is called the propoation delay.

b) Draw symbol and Truth Table of AND logic.

Answer:-
1
2
Symbol

1
2
Truth
Table

c) Convert (23)10 = (?)BCD

Answer:-
1M
(23)10 = (0010 0011)BCD
d) What is the base of Decimal number system?
Answer:-
1M
The base of Decimal number system is 10.

e) How many select lines are required to design 1:8 Demultiplexer.

Answer:-
23 = 8 1M
i.e. 3 select lines are required to design 1:8 Demultiplexer

f) What is non-weighted code?

Answer: -
Non-weighted or un-weighted codes are those codes in which the digit value
does not depend upon their position i.e., each digit position within the number is
not assigned fixed value.
Examples of non-weighted codes are: Un-weighted BCD code, Excess-3 code 1M
and Gray code.
Q2 A) Attempt any two of the followings 2 x 3= 6
a) State and prove De-Morgan’s theorem.
Answer: -
Statement-1 :-
• The De-Morgan’s first theorem states that, complement of the sum is equal to
the product of the complement.
𝑨 + 𝑩 = 𝑨. 𝑩

1M
Statement

Statement-2 :-
• The De-Morgan’s second theorem states that, complement of the product is
equal to the sum of the complement.
𝑨. 𝑩 = 𝑨 + 𝑩
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Proof.

b) Convert (45)10 – (25)10 = (?)2 using 2’s complement.

Answer: -Steps: -
1) Convert the given numbers into the equivalent binary numbers.

2 45 2 25
2 22 1 2 12 1
2 11 0 2 6 0 1M
For each
2 5 1 2 3 0 point
2 2 1 2 1 1
2 1 0 0 1
0 1

(45)10 = (101101)2 and (25)10 = (011001)2

 2) Obtain the 2’s complement of the negative number.

(25)10 = (0 1 1 0 0 1)2

1’s Complement of (25)10 = (1 0 0 1 1 0)2

+ 1

2’s Complement of (25)10 = (1 0 0 1 1 1)2

3) Add the 2’s complement of the negative number with the positive number.

(45)10 = (1 0 1 1 0 1)2
+
2’s Complement of (25)10 = (1 0 0 1 1 1)2

1 0 1 0 1 0 0

The final carry of the addition is 1, then the result is positive & discard this carry from
the result of the addition to get the final result.

i.e. (45)10 – (25)10 = (0 1 0 1 0 0)2

c)
Convert given SOP equation to standard SOP
𝐴̅. 𝐵 + 𝐵. 𝐶̅ + 𝐴̅. 𝐶
Answer: -

1) Find the missing term

𝐴̅. 𝐵 + 𝐵. 𝐶̅ + 𝐴̅. 𝐶

C A B

2) Multiply by missing term i.e. 𝑿 + 𝑿 = 𝟏

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For each
𝐴̅. 𝐵 (𝐶 + 𝐶̅ ) + 𝐵. 𝐶̅ (𝐴 + 𝐴̅) + 𝐴̅. 𝐶(𝐵 + 𝐵 )
point

3) Simplify brackets

𝑨𝑩𝑪 + 𝑨𝑩𝑪 + 𝑨𝑩𝑪 + 𝑨𝑩𝑪 + 𝑨𝑩𝑪 + 𝑨𝑩𝑪

Q2 B Draw and Explain 4-bit universal Adder/Subtractor.
Answer: -
 In Digital Circuits, A Binary Adder-Subtractor is one which is capable of
both addition and subtraction of binary numbers in one circuit itself.
 The operation being performed depends upon the binary value the control
signal holds.
 It is one of the components of the ALU (Arithmetic Logic Unit).
 The block diagram for a 4-bit adder-subtractor circuit can be represented as:

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Diagram

 Let’s consider two 4-bit binary numbers A and B as inputs to the Digital
Circuit for the operation with digits A0, A1, A2, A3 for A & B0, B1, B2, B3
for B.
 The circuit consists of 4 full adders since we are performing operation on 4-
bit numbers.
 There is a control line M that holds a binary value of either 0 or 1 which
determines that the operation being carried out is addition or subtraction.
 As shown in the figure, the first full adder has control line directly as its
input(input carry C0),
 The input A0 (The least significant bit of A) is directly input in the full adder.
 The third input is the exor of B0 and M.
 The two outputs produced are Sum/Difference (S0) and Carry (C1).
 If the value of M (Control line) is 1, the output of
B0(exor)M=B0′(Complement B0).
 Thus the operation would be A+(B0′). 2M
 Now 2’s complement subtraction for two numbers A and B is given by A+B’. Expl.
 This suggests that when M=1, the operation being performed on the four bit
numbers is subtraction.
 Similarly If the Value of M=0, B0 (exor) M=B0.
 The operation is A+B which is simple binary addition.
 This suggests that When M=0, the operation being performed on the four bit
numbers is addition.
Q3 A) Attempt any two of the followings 2 x 3= 6
a) Draw and explain one bit digital comparator.
Answer: -
 A comparator used to compare two single bits is called a 1-bit comparator.
 It consists of two inputs each for two single bit numbers and three outputs to
generate less than, equal to and greater than between two binary numbers.

Inputs Outputs

A B A<B A=B A>B

0 0 0 1 0

0 1 1 0 0

1 0 0 0 1

1 1 0 1 0
1M
For each
point
b) Simplify following expression using laws of Boolean algebra

𝒀 = 𝑨𝑩𝑪 + 𝑨𝑩𝑪 + 𝑨𝑩𝑪 + 𝑨𝑩𝑪

Answer: -
𝒀 = 𝑨𝑩𝑪 + 𝑨𝑩𝑪 + 𝑨𝑩𝑪 + 𝑨𝑩𝑪

𝒀 = 𝑨𝑪(𝑩 + 𝑩) + 𝑨𝑪(𝑩 + 𝑩)

But, (𝑩 + 𝑩 = 𝟏)

𝒀 = 𝑨𝑪 + 𝑨𝑪

𝒀 = (𝑨 + 𝑨 )𝑪

𝒀=𝑪

c) Subtract (10110)2 from (63)10 and write down result in binary.

Answer: -

1) Find binary of (63)10

2 63
2 31 1
2 15 1
2 7 1
2 3 1
2 1 1
0 1

1M
Now subtract, For
Each
1 1 1 1 1 1 Point
-
0 1 0 1 1 0
_____________________
1 0 1 0 0 1
Q3 B) Draw and explain the logic diagram of 1:4 Demultiplexer.
Answer : -
 Demultiplexers are also known as data distributers.
 A Demultiplexer is a combinational circuit that has only 1 input line and a 2n
output line.
 Simply, the Demultiplexer is a single-input and many-output combinational
circuit.
 It is also called as one into many type of circuit.

Block Diagram: -
1M
Diagram

1M
Truth
table

 There is 1-data inputs (Din),

 4 output (Y0, Y1, Y2 & Y3) and
 2 select inputs (S0 & S1).

1 :4 Demultiplexer Truth Table & Logic Expressions: -

1M
Expr.

1 :4 Demultiplexer Logic Diagram: -

1M
Logic
diagram
Q4 A) Attempt any two of the followings 2 x 3= 6
a) Simplify the following logical expression using k-map
11 2
𝒀 = 𝑨𝑩𝑪 + 𝑨𝑩𝑪 + 𝑨𝑩𝑪 + 𝑨𝑩𝑪 + 𝑨𝑩𝑪 K-map
Answer: K-Map:-
BC
00 01 11 10
A
0 1 1 1 1

1 0 0 0 1

The equation of Quad is, 𝑨

The equation of Pair is, 𝑩𝑪

The simplified equation is,

11 2
𝒀 = 𝑨 + 𝑩𝑪
Equation

b) Explain full adder with neat logic diagram and truth table.
Answer :-
 The Full adder is a combinational circuit used to calculate the sum of three
binary bits.
 The block diagram of a full adder with A, B and Cin as inputs and S, Cout as
outputs is shown below
Block Diagram: - 11 2
Diagram

Truth Table: -
Input Output
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1 11 2
Expln.
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
K-map for Sum: -

K-map for Carry: -

Cout = AB + BCin + ACin

Logic Diagram: -
 c) Convert following
Answer: -
1) (101101)2 = (?)16

0010 1101
2 D

(101101)2 = (2D)16

2) (111)10 = (?)2

2 111
2 55 1
2 27 1
2 13 1
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2 6 1
Each
2 3 0
2 1 1
0 1

(111)10 = (1101111)2

3) (123)10 = (?)16
16 123
16 7 11 - B
0 7

1) (123)10 = (7B)16

Q4 B) Design Binary to Gray converter using Karnaugh map technique.

Answer: -
• Let b0, b1, b2 & b3 be the bits representing the binary numbers, where is the
b0 is LSB and b3 is the MSB, &

• Let go, g1, g2 & g3 be the bits representing the gray code of the binary numbers,
where g0 is the LSB and g3 is the MSB.

2M
Diagram
Truth Table: -

2M
Expln.

𝑔0 = 𝑏1. 𝑏0 + 𝑏1. 𝑏0

𝑔0 = 𝑏1 ⨁ 𝑏0
𝑔1 = 𝑏2. 𝑏1 + 𝑏2. 𝑏1

𝑔1 = 𝑏2 ⨁ 𝑏1

𝑔2 = 𝑏3. 𝑏2 + 𝑏3. 𝑏2

𝑔2 = 𝑏3 ⨁ 𝑏2

𝑔3 = 𝑏3
 Logic Diagram: -

Q5 Attempt any four of the following.

a) Draw truth table of BCD to 7- segment Decoder and ts block diagram.
Answer:-
Block Diagram: -

1M
Diagram

OR

11 2 M
TT.
 Truth Table: -
Truth table for common cathode type BCD to seven segment decoder

b) Design AND, OR & NOT logic using NOR gate only.

Answer:-

1) NOR gate as a NOT gate

The Boolean equation of NOT gate is, 𝑌 = 𝐴̅
The Boolean equation of NOR gate is, 𝑌 = 𝐴 + 𝐵

Put, A=B
𝑌 = 𝐴 + 𝐴

𝑌 = 𝐴̅
A NOT gate is made by joining the inputs of a NOR gate together.

Logic Diagram: - 1M
Each
 2) NOR gate as a AND gate
The Boolean equation of NOR gate is, 𝑌 = 𝐴 + 𝐵
The Boolean equation of AND gate is, 𝑌 = 𝐴 . 𝐵
Take double complement,
𝑌 = 𝐴 .𝐵
By using DeMorgans theorem,
𝑌 = 𝐴̅ + 𝐵

Logic Diagram: -

3) NOR gate as a OR gate

The Boolean equation of NOR gate is, 𝑌 = 𝐴 + 𝐵
The Boolean equation of OR gate is, 𝑌 = 𝐴 + 𝐵
Take double complement,
𝑌 = 𝐴 +𝐵
Logic Diagram: -

c) Write short note on ASCII

Answer: -
• ASCII is the abbreviation of American Standard Code for Information
Exchange.
• It is universally accepted alphanumeric code.
• ASCII has 128 characters and symbols.
• We need 7 bits to represent 128 characters, so ASCII is a 7-bit code.
• It can represent number, symbol as well as characters.
• It is used for communication between computer peripherals etc

d) Enlist any Five parameters of logic family.

Answer:-
1) Supply voltage
2) Noise margins
3) Operating speeds
4) Fan-in 1
5) Fan-out 2 M
6) Operating temperature unit
7) Power dissipation.
e) Explain Ex-OR gate as a controlled inverter.
Answer: -

f) Write short note on weighted code.

Answer: -
1. The main characteristic of a weighted code is, each bit is assigned by a
“weight” and values depend on the position of the bit.
2. The sum of the weights of these binary bits, whose value is 1 is equal to the
decimal digit which they represent.
3. A sequence of binary bits which represents a decimal digit is called a “code
word”.
4. Example of these codes is: BCD, 8421, 6421, 4221, 5211, 3321 etc.
5. Weighted codes are used in:
a) Data manipulation during arithmetic operation.
b) For input/output operations in digital circuits.
c) To represent the decimal digits in calculators, volt meters etc.