Pao MADE EASY 202 worknook 2025 | Detailed Explanations of a Try Yourself Questions Electronics Engineering Analog Circuits R= We OnDiode Circuits-Il @ Detalled Explanation of Try Yourself Questions (a) Inthis question weneedto determine which diode ison and which diode is OFF, clearly dade Dis OFF because if its on then current from current source will ow from nto pterminal of the diode D,and ths is not possible, hence D, is OFF Applying the same concept, we can say diode D, is also OF Diode D, is on be: battery of 10 V. @ cause it is forced by the Assume Djon, D,off, Djon ‘ov For negative cycle of input thus the V,, will appear across the series combination of the two 1 k@ resistors and we are taking output across 1 k®2 resistance only a =10v - a» hence the output will be reduced by 50 % and sOL08 20). the above circuit will work as a full wave In = agp = AT mA rectifier with an attenuation of 1/ 0-064) jiq¢ 8 10k Since there is a D.C level shift in the output waveform thus the circult must be a clamper i. Circuit and when the diode is conducting then Since allthe voltage are postive allthe diodes the voltage at the output must be 5 Vas seen ll ty to be forward biased but only the diode from the output waveform hence optian (b) with highest voltage willbe switched on rest pm ay will bein off state. ‘ wwwmadeeasypublicationsorg MADE ERSY © CopyrightMADE EASY ae IV, < 1.7 V: D,-OFF, D,-OFF Vou = Ven Minimum, Vy =-5V IfV,,> 1.7V: D,ON, D,-OFF Vy X 141.71 Vout = Tet S417 Maximum, V4 = 2+*4=3.36v EE Gs.16) If V,<4.8V: DON, D,-OFF i,=0 If V,> 4.5 V: Dy OFF, D,-ON i, = 100mA 6 = sin” 42-267° Average value of , = Vo, = Consider D, ON Assume D, OFF V,=5-06=44V tov Now, fo, = 4.4-5=-06V = D,isOFF Ip, = $4298 -7.6ma Jo = EASY ) wwwmadeeasypublications.org |DC Analysis of BJT Circuits Detalled Explanation of Try Yourself Questions IC,_15mA =- 4. = 0.01. mA B 150 Tgp vill be equal to Z,, as there is no change in R, Toa = Bolo = 200 001 mA =2mA ct2 = Voo~ lage =6-2mAx2kQ=2V The new operating paintis Q(2V, 2mA) (05) , ska & www.madeeasypublications.org MADE 12 in er4s2 = tms Applying KVL in loop L I, X2KQ- 1% KO = Vee 2-Ix3k=05 x8k=-18 r= 28.40% =0.5ma (467) If BUT is in saturation Tosa = for saturation fg > I, le 21x 10% x 100, 2 1 ERSY © CopyrightMADE EASY Detailed Explanations of Try Yourself Questions : ESE + GATE 2025 5 Publications mae ae a 0.25 ma atnode'a’ Ig = fo +3ly (Iq3i8 assumed negligible) " = z zie al sl Using current mirror: Forlarge'B’, 80, HleatonsDC circuit Small Signal Analysis of BJT 12v 220K. Ip= Detalled Explanation of Try Yourself Questions sonal pre 12-07 2” Tis p)a.9k+ 220k = 0.0163mA Je= (1+ Bllp= 1.97 mA wowwsmadeeasypublications org 26 mV Ta7 mA = 13.189 3.83k Ae ~ 4845 = 291.41 z-Ke ye oT EP = 0.752 ||1.578« = 0,509 k@ = 509.4. 2 (0.01) From figure, the equivalent current sources can be written as, 0.01 v,.= ai, = (0.01), = 0.98 ERSY © Copyright)MADE EASY ta We know dp 00 40° =10kQ Gn 10 Drawing the small signal equivalent, we get Reg) n= Ag+ (B, IIR, Now. to calculate R..,.we can use another model V= (++ AY Rog ear + B+ DR + Ry = Re + [Ry IR, I (eB + 1) Re) puting the values Rey = 10kKO + 101 x 500 0.5 ke s Ka + 4.62 KO 62 ko ta Drawing the small signal model of the above circuit, we get Detailed Explanations of Try Yourself Questions : ESE + GATE 2025 7 Let A’ be the input resistance as seen in from point A. Thus, to calcul separately ® 4 i te A’ we can draw the diagram vy (1, ) wet |], 7 (Ge j Thus, the valve ofthe output voltage no (Fy + FY Drawing the small signal equivalent model of the circuit, we get Thus, the equivalent circuit can be drawn as © now, ta 0 and V, + (+ 29,,V,) Re = VEO 29 EASY vomuimadeeasypublicationsorg |8 Electronics Engineering © Analog Circuits = (128 +200Fe Ve Vin = (te + 2Re + 20rmta Re) Va = Uy 2(1+ Fe) (0 Onfg= BD MADE EASY ————Publleatione Vest Ye" TVR DR) ‘now, substituting equation (ii) in (i), we get 1. 2h © +2(1+ BRE) y= Yea Mie Ai) MADE ERSY ubDC Analysis of MOSFET and JFET Circuits Detalled Explanation of Try Yourself Questions iT. [OF g tov Ls ——ew, LM ——», Ad Vp = Vq «: we concliide that each MOSFET isin saturation Iy= kyy Wes Vol? MOSFET M, y= bi oss = Va? Vag) = 10-5 =5v (w) ; O5mA = Bou x 5 (q)xe-0 Ww (%) <7 MOSFET M, I= bre Vase Vi)” aoux + (“) 12 0.5 mA = 86x [ T} 28-1 iw) (i), 00 (© copyright MADE MOSFET Mg Kg Vga ~ Vol? 1 () 2k) 0.5 mA = 36ux 3(2-1? ie Vy = 0.4 PMOS in depletion mode vee 15¥ ‘ “[ verosv osv wv® Yap > Veg Ves < Vgq + Van Tiode region + Vo, current saturation sn = Vg-Vg=15-0.5=1¥ Vso = Vg-Vp=15-0=15v 1.5 > 1V 40.4 current saturation region Vez 08 vp209¥ vey Vae0 oav PMOSin depletion mode oq V5~Vp=09-0 ERSY wonmadeeasypublications org10. | Etecwonies Engineering ¢ Analog Circuits MADE EASY Publleatone Voq = Vg-Vg =0.9-0 =0.9 We 0<09+0.4 ; triode region ce the configuration represents an invertor fa) MOSFET with an active load, the output will be high for low values of input signal and low for high values of input signal. Now, since the load transistor T, has shorted drain and gate, To calculate the value of Vos, we require the voltage of both drain and source terminal Now, assuring the transistor to be in saturation region, the value of Vi, can be calculated as Vos > Ve fos> Vas ly HrCoe W Vag V4)? O>-¥, 2b Which is always true hen« tor T, will 1x 10% = 05 x 10? x (Vag ~ Vi)* always work in region. 241.2 = Vos When V,, = 0, 414412 Hence, 614 Now, Thus And Thus, Vo~ Ve=5-(-2.614) 614V. Vos > Vas~ Vp $0 our assumption is correct oy Hence maximum value of output = 4 V. ullSmall Signal Analysis of MOSFET and JFET Detalled Explanation of Try Yourself Questions ol RL), boned y= BoP) Vow Itis common drain amplifier. ou TR, Dns _On 4K On Toe Tn Fe” Thon FO nla FL) p= 47508 oa aera Yo 04, = 2k, Vag~ Vp ee (i 20x10°(2% 102] 210°) x 1x 10 =2k,| Feawc) 1+ 20x10 x50 au" Vag = 10mV 2lloky 2 flop [™) dy = 2 Ylo* BBC ( mtr) = 2 B2Se lra Vd w 2b ri CW or On = Poot x toa 12. [G 2b I= 2YKulo = avix10% x05x10% = ayt0x10° x10x10° 1.414ma/V jy ~ 20mAN Thus, considering small signal model, we get, now. dlawing the T equivalent model, we have 6 . Mo eee LQ Fee an Fe | © Copyright MADE EASY wonmadeeasypublications orgElectronics Engineering © Analog Circuits MADE EASY 12 Publication Thus, Vo = On Ves Ro the above circuit can be redrawn as Va = Vr (Gn Yoel Rs Vou Va = Volt * 9p As) = Me _ 9m Ro Ae" Teds _ 0a A= Taras) °° 14. [(D) By drawing the small signal equivalent circuit by deactivating all the D.C. supplies, we get, oof IgFYq~V) (from ()) “Ing FVin + Gong VR Vg v= Sens me (from equation (i) now from (3), we get ns Im. BVin — Vout In By drawing the smalls we get ey" Gey Hence, option (a) is correct. MADE ERSY ubMultistage Amplifiers Detalled Explanation of Try Yourself Questions The input resistance will be 1ka, Ska SOT OKO” BRD + 1K Y RY = 1, + (Bp + WRe = 2 =3472 = 1k + (101)(1k) = 102 ka R, fn ifn + (By + 1)" ee = 1k + (51) (102k) = 5.208 M2 i one kHz for single stage. For cascaded stage t 20 vain a4 Vet =4 12 Ska =39.2Hz © Copyright MADE EASY wonmadeeasypublications orgNegative Feedback Amplifiers Detalled Explanation 9 of Try Yourself Questions me The overall forward 0 and close loop. The feedback element is F; it samples voltage gain is 100. Thus, B = 0.009, and mix current so shunt-shunt feedback. Now, when gain of each stage increase by 10% then overall forward gain will be 1331 and using cory the previous value of 6 the close loop willbe 102.86 = Close loop Voltage gain increase by 2.55%. wwwmadeeasypublications.org MADE ERSY © CopyrightDetalled Op-Amp Circuits Explanation of Try Yourself Questions Output of op-amp 1 4 fi ¥ 0 — ii — “oe “4 vj — We ven Fy “ It is connected to schmitt trigger (inverting mode) > clockwise. Butinverting ampifier + inverting schmitt rigger » anticlockwise 2K voltage shunt ® Copyright mADE yong Boor 10x 10x 10° 10° 1kQ Bo Redrawing the circuit by replacing amplifier with its block diagram from the given properties R=) Ry = 0; voltage gain = Ay ERSY wonmadeeasypublications org16 | Electronics Engineering © Analog Circuits MADE EASY Publleaons R From the circuit, te Ati Ve= i, Ry at. Be A,% Vz = V, {Virtual short concept) Yl 2 Ao . ie els It we apply KVL between node Band C, ‘ Vq = Vo Virtual short concept) Vg -AyMn _ Va =[1-A] ° Ry A Ayo =F ln iw toxa ° R duty cycle of the above astable faaok 40K0 itivibrator (designed using 555 timer) is. Toy Rat Re > fon = Ae thus Duty cycle > T= Facarg, us Duby cyote > 50% ull@ Detalled Explanation of Try Yourself Questions 5 7. 1 The output can be +12 V only, Since their are 3 capacitors the maximum when outputis 12 V then phase shift that can be provided will be 270° R ‘ut due to the presence of the RC circuit the al phase shift is equal to 60° for the individual cL hi RC circuit, making the phase shift of the T feedback network equal to 180°. Thus the ¥ amplifier should be an inverting amplifier so 2ka because the amplifier is a practical amplifier P, ies o| thus [ABI > 1 forthe circuit to work Layee 10K. © Copyright MADE EASY wonmadeeasypublications org