ZILOG INC U7E D mm 3584043 0011879 1 mm T-4A~17-0 28001°/Z8002° 4 U October 1968 FEATURES: 1 Regular easy louse architecture 1 Insiruction set more powerulthan mary minleamputers 1 Diteoly aderosses 8 Mbytes 1 Eightusorcolotabl addressing modes |= Seon datatypes hat range om itso 32-bteng words and byte and word stings ‘© System and Normal operating modes 18 Separate code, dal, and stack spaces 1 Sophisticated itorupt structure "= Resource-shaping capabities. for multiprocessing systems |= Mul:progtamming support 1 Compiler support |= Memory management and protection provided by 28010 Memory Management Unt '= 82: operation,inctusing signed multiply and vie BUS compatible 4,6.and 10 Mieclockrate GENERAL DESCRIPTION ‘The 28000 is an advanced high-end 16-bit microprocessor {hat spans.a wide valey of appietions ranging rom simple sland-alone computers to. complex parallel processing systems. Essenialy a monothic minicomputor contal processing unt, the 28000 CPU le characterized by an Inatuction set more powerul than mary mincomputers ‘abundant resources in rogistors, datatypes, addressing ‘modes end addeossing range, and a regua’atchleture that enhances throughput by aoicing extcalbotlenecks such as implied or dectested rages. (CPU resources include sixteen 16-bit goneratpurpose registers, soven daa typosthatrango fam bite to32-bitfong Words and bjt and word evings, and ght user selectable ladiressing modes. The 110 sinc Instucton types opn be combined with tho various dala types and addressing ‘modesto form a poweril sa of 414 instructions, Moroovet, “the instuction seis egular; most instructions ean use any ‘tthe ivemain addressing mades and can operate on byt, ‘Word, end long word datatypes, ‘The CPU can operate in either the system or normal mode, ‘Thecstincton betwen these two modes permis privloged ‘operations, thereby improving operating system Ciganization and implementation, Mutiprogramming Is supported by the "atomic" Test and Set instucton: ‘multiprocessing by a combination of inlrecton and ce =z 3 128ZILOG INC hardware festures; and compliers by multiple stacks, special instructions, and addressing modes. ‘Tho 28000 CPU Is offered in three versions: the Z8001/ £2160 segmentad CPUs and the 28002 nonsegmented ‘PU (Figure 1). Tho main alference is in addressing range. The Z8001 can directly address 8 megabytes of ‘memory; the 2160 directly addresses 2 megabytes; the £28002 direcly addrosses 64 kilobytes, The two operating ‘modes - system and normal - and the etinction between ‘code, dala, and stack epaces within each made allows, ‘memory extension up to 48 mogabyoe fr the 28001, 12 ‘mogabytes forthe 2160 and 304 kilobytes forthe 28602. WE D SS mi 5984043 0011880 8 mm T-49-17-07 ‘To mest the requirements of complex, momory intensive pplication, a companion momory-managemont device's ‘ftred fr the 28001. The 28010 Memory Management ‘Unit manages the large addrass epace by providing fea {ures such as sogment relocation and memory ‘The 28001 can be uped with or without the ZB010. W used by itself, the Z8001 stil provides an 8 megabyte direct ad- ‘dressing rango, extendable to 48 megabytes, ‘TneZ8001,28002 and 78010 are fabricate withhigh-den- sity, high-pertormance scaled n-channel slcon-gato mm 9984043 0022886 9 mm | T-49-17-07 Figure @ ilusvats th eight addressing maces: Register (F), immecite (i, Indrack Register (i). Dict Areas (OA, Indox 09, Ralative Address (A), Base Address BA), ‘and ase Index (BX). In general, ah addressing mode ‘xpllly spect other register adcrens apace or marnory ladgress space, Program memory address space and VO ‘address space are usually ilied by the instruction. aivening Mose Opeand Krona Opeend Yao ‘Ta the Instruction tn @ Register ‘Ia Memory, i esi im a Immedine — (S] oe im oo a Indy Remind te mean Direct Adress 7A oo oo | Sejmeedhon Gre ‘Piviegedbusion Exoauadinytam noon ony SL > Segre ang tet PS= Sytem Cat PS 139ZILOG INC U7E Do M™ 9984043 001189. 2 mm BIT MANIPULATION -49-17-07 de Mnemonics Operands Modes * NS Operation ab 4 Test Bt Stato | aire 8 8 8 Zita * NOT dst pectic by b wo on x wou iw ar oak OR 1 WO ‘est BitDynamiec are 299+ NOT esi epciiod by contantact es a,b R 4 4 4 Reset Bitstatic 7 Resa Ron on on eset dt epeifed yb mw oR Me idee ee res. wah RO Reset it Dynamic ESS ese dl bt speciety contanis or aba 4 4 4 ‘Set Bit Stato sere Roun oH Sel oat bi epectedty> mw 8 Me ie ea tier 7 a rR OO SetBit Dynamic sere ‘Set dl biped by conens oR Teer ey ee “eat and Set ‘Tser8 Roum w ‘Sag ~ SB oft OT cet alte ie 16 06) 210) ROTATE AND SHIFT aL ein Giern=t tate Lett aus a Tleen=2 bys (a= 1,2) ruc an Biern=t Fotate Lett trough Cary Lee 8 Tiecn=2 Dynbie(n= 1,2) ru a Rotate Digit RR R Giern=t Fotate Right Re a Tlorn=2 bynbis(n= 1,2) re wan Stern=t tate Right through Carry Ace a Torn? Dbynbis(a= 1,2) ROB yer Fotate Digit ight SDA oa, R (05439) (15 +3) ‘Shift Dynamie Arithmetic | soe Shit cle ogy SAL contents so oan A (eran) (1S +3m) __ ShinDynamieLogical soLB ‘Shit celeb gntby souL contents ‘35 Sagrared oven 40ZILOG INC A7E D mm 9984043 OOLLas2 4 ROTATE AND SHIFT (Continued) 7-49-17-07 Cioek Cycles ‘Ade, Word, Byte ‘Long Word Mnemonics Operands Modes NS SS. SL NS 8S Operation aa oan (+8m) (18+Sm)—— ShIRLeM Arthmetl. SLAB . byte SEAL su ean R (4am) (1343n) —— ShMLettLogioal sus bynbite sue ra an " (3430) (9+ 3m) ——_ ShiERIghtArthmetio SRAB bynbie ‘SRAL ‘srt win (i330 (943m) Shitght Logical SALB bynbis SRL BLOCK TRANSFER AND STRING MANIPULATION Po Roaches 22] 20 ‘Compare and Decrement roe Pye ‘Aaosocroment se adees Bye y= POR Rese Ryeo (item ‘Compare, Oseroment, and Repeat ‘cPORB Fy a ‘todecomontsradcess Rye y= 1 peat nitentetve ory = 0 cn Rysionyco Ra) ee ‘Compare andinerement cris Pye Pinerement re adeess Pye nyt Fisica (ivem ‘Compare, Inrement, and Repeat Fx se ‘Auteinrement se adkess Prey Fepeatuntcofstuocr Ry = 0 ‘Psp cache RS 25S ‘Compare Siting and Decrement oPsoB 7 ate ~ 0 ‘Aulodectement dt and ee addoseen Rer-4 ‘cPspr Gisohe (ie tam ‘Compare String, Deeroment, and cPsore ‘ulodecrment dt and rc addeseas Rer-1 RepeaturicsisweorR =o *NS = Nonasgnericd 65> Sepreadshan Oke’ GL = Sapneiotong Oe iZILOG INC 27E D mm 9984043 0012893 b mm BLOCK TRANSFER AND STRING MANIPULATION (Continued) T-49-17-07 Moemonies __Operands Operation ‘cps eawone RO crsia Pain cawoRc iF ie ae) cPsine ‘Compare String and inerement it~ ere * Autintement de andere adresses Rea-1 ‘Compare String, increment and Repeat et 0 ‘Aatelneement dt on sc adeses ReR-4 FopealuritcoietusorR = 0 ipo eason RO ‘008, ‘otd and Decrement dst ‘Autodecrement dt and se adcossen R-R-1 itpor aah oR en Lone oad, Decrement and Repeat ost 0 ‘Autocacrement dt and so adresses ReR-1 Fopeat uh = 0 ior oaaeR IR 2D aD toe Lon oaaeR IR an Loire {Load and increment date ‘Aulinrement dt andere acroeses ReR-4 ‘oad, Inerament and Repeat dst ero ‘utlnremen dt sr ae accross ReR-+ FepeatuntlR = 0 TRB isch RSC TRORB aecn is tn “Tanelato and Decroment ‘at aoc) ‘Aulodecrement dt dross RoR sate, Decrement and Repeat at ae) ‘lodecrement dt addoss RoR-1 FepeaturtR = 0 Tre aieoh ROO “Tanelateandinrement at oa) ‘Aoinrement dat adress ReR-+ SHS = Non-aogmanied 5S = Segirted Shot Oitet SL ~ Segmariad Long Of *ivingedinucon Excited sm mo ch a2ZILOG INC we D mm 5584043 0011894 3 mu 7-49-17-07 BLOCK TRANSFER AND STRING MANIPULATION (Continued) Mnemonics __Operande Trine pron) TrroB ‘seach Ae. Modes ® tock Gyles Word, Byte Crrerny 2 8s st 28 tong Word ss su Operation “Tanalate, Increment snd Repeat at ae(e) ‘Aueltemart det aseroos Rer-1 Repeatuit R= 0 “Wanslate and Tost, Deorement RH (et) ‘Audodecrement er edcoss ReR-+ TaroA ‘sot seaR Tare ‘worsreaR eer) 3S 2 ‘Wansiato and Tet, Decrement, and Repeat BHI -s2(een) ‘Auledecrment srt addose ReR-t opesturR = Oot Rt ‘Wanslate end Tos, nor BH ee (ee) ‘uelncomenterct acess aeR-1 TRTIRB sche ie a Transit Repeat RHI = 212 (et) Julneemantse ade aeR-$ posture = Oor Rit = 0 idee, Increment INPUT/OUTPUT a nat Rae @ 0 10 ee 10 2 Taput Rese wot Wwost ete inpat ‘wore! aah i mr aac R= Newser 35 Sagara Son Oe ‘rhsegesiension Emedineyem nade ory aa (r+ 10m aa a a Fert Input end Decrement ass ‘Aulodecronent det adres ReR-4 {Input Decrement and Repeat dae ‘Aodecromont ot adeross Reed Fepeatuns = 0 Input andinerement t= ero ‘aoicrement ds actress 3ZILOG INC 27E Dm 9964043 0022855 T INPUT/OUTPUT (Continues) T-49-17-07 ‘tock Gycles® ‘Addr, Word, Byte tong Word Moemonies nds Modes NS SS SL_NS SS SL_ Operation tat eaach im (11+ 100) Input, Increment and Repeat at dat 20 ‘uineserent det ecoss Rea-+ epeatuntiR = 0 ourt aan 1 10 0 Output ourst AB RB we otek ourot er] ‘Output ana Decrement | ourost ete Aulodocrementetc adress ReR-1 ror? eaiaoR (1+ 10m) ‘Output, Decrement and Repeat Tore dame ‘ulocecrement te adcaes Rent Fepaatuntth = 0 ount aon Rm at ‘Output end noremer ouniat étmae Aeinrement se adsess Rer-1 oni easonR (i+ 109 ‘Output, ineroment, and Repeat onirat sar Auierement te acess ReR-1 Fpeatust R= 0 wt Asc OA ‘Special Input sist Rese ry Simchat ‘Specal Input ond Desrement soat osm are ‘Audodecrment dl adcoss ReR-1 ‘sino? eon 1+ 10m) ‘Special Input, Decrement nd sinonat epost dane ‘Autodecroment dated ero epoatun A ~ 0 ‘it easen aa ‘Spedlal input and increment siNiBt date “HS = Non-sagmeriod 85 = Segreried Shon Ole SL ~ Sogmeried Long Ofsat ‘Privegodiatucten Excite ase moony ‘ueinerorent lt edeose Raat rrZILOG INC L7E D MH 9984043 001185 1 mm INPUT/OUTPUT (Continsec) 7-49-17-07 Cock Cycles* ‘Ads. Word, Byte Long Word Mnemonics Operands Modes NS SS SL_NS SS__SL__Operalon ‘sit auoR IR (t+ 109) ‘Special nput, Inerement, and siNRet Repeat dts ‘Aucincremant dt dress ReR-+ post unt = 0 sourt dame (DAO te ‘Special Output souret dts soutpt ook Ratatat ‘Special Output and Decrement sourost diese : ‘Aodocrement ro across R-R-1 ‘soroat otsoR IR (1+ 109) ‘Special Output, Decrement; and soTorat Repeat odese ‘Autodecrement ero adress ReR~1 Repeat unl = 0 sount Cr a ee er) ‘Special Output and increment oat~ a0 ‘utcnorement se does Rea-t sont easeR (i+ 09) ‘Special Ouput noreent, and Repeat dts ‘ulcincremantse address i ReR-t opoat uni = 0 CPU CONTROL courte tags So ‘Complement Flag : (Gay combination ot, 2.8, A) or ee nea ‘Disable Intrrupt (nycombinafon et NV, VN er int - 77 7 Enable interrupt (Gay combination ot WV.) aur? = = e430 ALT toontcniaseO.SS Led into Contol Register cha~se toon amen ORO Load trom Control Register damn {NS = Non-segmerted "3 = Segieniad Shed Oller GL = Serer Lang bel ‘Miviegedatcten Ewoctedin gn moseyZILOG INC U7E Dom 9984043 0031897 3 mm CPU CONTROL (Continuec) T-49-17-07 Clock Cycles ‘Addr. Word, Byte Long Word Mnemonics Operands Modes NS SS SL_NS 8S. SL ioens ons ee eee toons oncr oR? oT iopst we m2 7 PR 620. x 7 » 2» wort 7 = 7? 7 Test Mutero Bi SalSitMlioLow:roset Mie gh Mnear ot F (CEEY ‘Matiiero Request iNnESt = = 5s 6 8 Muto Re ser! = oe Muttatoro Set Nop = =— 777 No Operation resria ‘9 = 77 7 Reset Fa (arycom serme to = 77? ‘Set Fing NS = Nonsapneriad 66 ~ Geganed at Oto ‘viegedirenion Excladingyorimadecn, (Ary comntinaton 2,8, Pr) 10ZILOG INC A7E D MH 9984043 0012898 5 mm Ss 49-17-07 CONDITION CODES ee code Meaning Flag Settings crit F ‘way tle ~ ‘0000 T ‘Aways ove = 1000 z 20 onto Nz Netz 1110" ce Cary on Ne Nocany am PL Pus s-0 not Mt Mus sat ows NE Netequal 2-0 1110 ea Equal zat or10 ov vow Pvt 0100 ow Nowerow Pwo #100 Pe Panty eon pve 0100 PO, Patty ods Pwo 1100 Ge Gres than or equ lane) exoRFM~0 101 o Lows than once) @xORPM = 1 001 er Geeta than (grec) [ZoRGxOR PIM 0 1010 re Less than or equa gnod) (ZORGxORPA 1” oot ce Unsigned grea than or ecuat CHo a um Uncignetes han cat ont ust ‘Unsignod gresterthen IC =QAND@=o)=1 1011 we Unsigned oss than or equal (Cor =1 oot i tha conacvdion odes hve area tap sts ear haan acon ZOEQNZ = NEC = VILNO = USE. OV PENN = PO. STATUS CODE LINES. ‘STyST3 __Defiion (0000 intemal operation 0001 Memaryetesh 2010 WOreterence 0011 Speci 0 rterence (9.10 an MU) 0100 701 010 ont 1000 1001 1010 ort +100 01 110 11 Segment trap ackroniecge Nonsmashaleiterupt acknowledge Nonveciord iruptacknodedge Vocioredlitanuptackeowtedge ta momar request Stack momory request Data memory roques(EPU) Stackmomoryequost(EPU) Program etree, ward Insuctentech, es word Extension processor vanglr esered “7ZILOG INC ave D ee PIN DESCRIPTION ADg-ADss, Adress/Data (npusioutppls, acive High, late). These muliploxed addross and data nes aro used forliO andto address merry. BB. Adress Stobe (ouput, ect Lov, 2), The sng ‘edge of ASinccstes acresses are vai. 'BUSAGK. aus Acknowiedge (output active Low). A Low on tis ne incioses the CPU has reinquisned contol ofthe bu [BUSREG. aus Request (input, sctve Low). Thi ine must be ctvon Low to request the bus from the CPU. BAW, ByteMord (cutout, Low = Word, State). This signal defines the type of memory reference on the te-bt ddressdata bus, CLK. Sstam Clock (input CLK ie a SV single-phase time base input DBS. Data Srobe (output, active Low, 3-ate. This ine times the datain and outof he CPU, NIREG. Memory Request (ouput, acho Low, 2a), A Low on this ie incites thal tho adace/dala bus holds a ‘memory address. Ai, 1. utero in, MutMtiro Out (input and out, ‘2ctve Low), These two lines form a resourceequedt daisy chainthal alows.one CPU in amullimicroprocessar stom toacoose a sharod resource, Ti. Non-Maskabl norupt ode agere. np, active Low). A’ hightolow nation “on Nil requests a BEREEES S23 Flguro 108 4-pin Oualin-Line Package (IP), Pin Aselgnmente mm 9584043 0011899 7 mm 7-49-17-07 non:mestabe rtp. The Rl iterupt hs he highest pont of tie tres ypesofintarup |W. Norma/9ystem Mode (ouput, Low = Sym Mado, tae). NVS icicle he GPU ie Inthe ermal or ystom moda LAVA. Non-vectored inforup input, actve Low). A Low on this ine requodts a non-vecored neu, ‘RESET, Reset (nput, activo Lov), A Low on ti tine resets the CPU, IW. Reacitnte (ouiout, Low = White, State). RAT Indcates that the CPU is reading from or wring to memory orll0. SEGT. Segment Tap (input, active Low), The Memory ‘Management Unitinioruptsthe CPU wih Low onthis ine when the MMU detects @ sopmentaon tap. Input on 28001 only, 'SNySNe, Segment Number (ouput, active High, state). Those ines provide the 7-bi segment number used 10 ‘address one of 128. segments by the. ZB010 memory Management Unit Output by te Z800% ony. SToST Situs (outputs, active High, 3a), Theso nes speciy the CPU satus (e00 Ststus Coda Line). STOR. Stop (input, active Low), This input ean be used to ‘ingle sepinsiucion execution, ‘Th. Vectoredinterupt (input, active Loy). Law on this Sno requests aveciored iferupi. ‘WAM. Wat (nput, active Lo). This tne incales othe CPU. thal he memary ar UO device isnot ready for daa transer. SSEGSSEEEREEES ‘Figure 118, 40:pinOuatin-Lin Package (OIF), Pin Assignments aeZILOG INC U7E Dom 9984043 0011900 T mm 1-49-17-07 WREFSBEDE eae PPCM EP EE {52pin Chip Carr, Pin Assignmenta severe rrrre vagy ‘pln Chip Caner, Pn Aslgnments Figure tb, 28000 CPU TIMING ‘Tne 28000 OPU executes instructions by seping the soquences of basic machine oyeles, such at memory ‘or wil, UO device read or wie, interrupt acknawledae ‘and interna execution. Each ofthese base cycle rogues three o ten clock oyces to execute. structions hal aque more clock oycles to execute aro broken up iio several ‘machine eyclas. Thus no machine eye is longer than ten ‘lock cycles and fast response lo a Bus Request is ‘uaranted. ‘Theinsruction opcodes ftched by anormal memory read ‘operation, A momory elresh cycle canbe ingerted ust aller the competion of any fis insructon fetch (IF) cycle and ‘can also be inserted whie tho folosing intuctons are being eveouted: MULT, MULTL, DIV, DVL, HALT, all Sit inguctions, af Block Move insctione, andthe Mu Micro n J Reequesinttucon (MRE), The folowing ting diagrams show the relative ting relationships of al CPU sgnale during each ofthe base ‘operations. When a machine oyle requires additonal clock {yclea for CPU intrnal operation, ane o ve clack cycles ato added. Memory and HO read and wete, a8 wall as Interupt acknowledge cycles, can be extended by activating the WATT input, For exacting information eer to ne composte ting haga, Nol thatthe WAT input isnot synchronized in the 28000 ‘and thal the setup and hold times for WATT, clave tothe lock, must be met. If asynchronous WATT signals aro ‘gonetato, they must be synehrorized with the CPU clock ‘loco onering the 28000, 79ZILOG INC U7E MEMORY READ AND WRITE ‘Memory read and instruction fetch oycos are idoncal, x- ‘cept for the status information on the SToSTs outputs. During amemory read oycla, a 16-bi adress is placed on the ADs-ADss outputs eaty In the fist clock period, a8 shown In Figure 12 Inthe 28001, the 7-bitsogment num ‘br is outputon SNy-SNs one clock period carer than the 16-bit addeoss feat. ‘A valid addres is inccatad ty tho rlsing edge of Address Strobe. Situs and mode information bedome valid eat in the memory access eyle end remain stable throughout “The slate ofthe WATT inputs sampled in the mide of the second clock ole by the taling edge of Clock. I WATT is Dm 9984043 0011902 1 mm T-49-17-07 {a an aon clock peed addedbetoon Tz endo. is camped againin the middle ol this Wal cycle, and _addiona waste canbe inserted this allows inefacing slow memories, No control outputs change during wat states, ‘Athough 28000 memory le word organized, memory le ‘addresced as byes. Alinsrucions are weré aligned, Using ‘ven addresses. Within & 16-b word, the most wigeicant bye (Op Deis addressed by th low ordor adress (Ap = Low), and the least sigoicant byt (Oy) Is addressed by thohigh order adgress (4p = High) ccoe__| _| XX 32 a sian xX zenro | YX XX Figur 12. Memory Read and White Timing 60ZILOG INC 17E D mm 9984043 OOLL902 3 mm INPUT/OUTPUT VO tiring Is sina to memory read/write timing, except ‘hal one walt state is automaticaly ya) inserted botwoon T-49-17-07 ‘Tgand Ts (Figure 19) Both the sepmentod 28001/28006 and the noneegmented 28002 use 16st /0 ederesses, on IS X_ ror aon Figure 13 nputiOutput Ting rrZILOG INC INTERRUPT AND SEGMENT TRAP REQUEST AND ACKNOWLEDGE. The 28000 CPU recognizes thee intrupt inputs (Ponmastable, vectored. and ‘nomectord) snd a yreraton top np Ary Higho-Low anton on the inp is asynetroncusly edge detected and ets the itrral Nate. Tne A ond SEGT np, 0 vel os {hosts oftalrral Nach, ae sale ato ord Tenth let machine cyte of ay inaction. Inresponseto an inept ortep, the subsequent; fee isqrrcsod bulgnored Tein de oftne CPU ct sored and he Ineusion wil be vltched and erected ater herent te orp rote. Tho Progen aun’ is rat updated, butte sysiem sac power Gooremartiainpreperaton fr pushing eating fomaton iota eso sack The next machine oye ste interrupt acknowledge eyte, LE D m@™ 9984043 0011903 5 mm “1249-17-07 “Tiscyce has fv automatio walt states, wih adcona! wait statospossbo, as shown inFigue 14, ‘tr the lt val ale, the CPU roads te information on ‘ADp AD g and temporary stores, obo saved onthe stack later in he acknowfedge sequence. Ths wordiderifes the source ofthe Intrrupt of tap. For the nonvectored ad ‘nonmaskable inetupis, al 16 bits can represot peripheral device stats information. For the voolredinerupt. he ow bye is the jump veto, and tha high byte can be extra user Salus, For the segmentation tap, the high bye ls te Memory Menagement Unt identiior and the iow byte is undid. ‘or the acknowledge cycle, the NIS output indestes the ‘automatic change o system mode. sci —saeemn)) Figure 14. Interrupt end Sagmont Tap Request/Acknowledge Timing STATUS SAVING SEQUENCE ‘The machine cycles, folowing the Interupt acknowledge or ‘segmentation trap acknowledge cyole, push tho od status information onthe eystom stack in the following oxde: the @bit program counter; the 7-bit segment number (28001122005 only the lg control word and tnally the Interupt/tap identi, Subsequent machine cycle fetch ‘he new program situs from th program status erea, end ‘thenbranch othe intorupt/rap series routine, isaZILOG INC BUS REQUEST ACKNOWLEDGE TIMING A Low on the BUSREG input indicates tothe CPU that another davoe is requesting the Adtese/Data and conto ‘buses. The asynchronous BUSREG input ls eynonronized atthe boginning of any machine cle Figure 18), BUSREO takes pritly over WAT. f BUSREG Is Low, an inernal synchronous BUSREG signal Is generated, wich: ‘completion of the current machine cycle causes the ‘utbutto go Low andl bus outputs to go nt the WE D mm 9984043 0011904 7 mm T-49-17-07 highimpedance state. The requesting device—typicaly a DMA—can then contol the bus. ‘When BUSRET srleased, Ris synchronized with thersing cock edge, the BUSACK output goes High ono clook patod later indicating thalthe CPU will again take contol ot thebus, ~SLyii =~ t - | ic | fonraramsondX Figure 18. Bus Requost/Acknowtedge Timing 758ZILOG INC ‘STOP ‘The STOP input is sampled by the lst fling clock edge immediately preceding any IF cycle (Fqute 16) and before the second word ofan EPA instruction i fetched, STOP is found Low during the Fy ojo, astream of memory rarest cyclosisinserted ate Ts, again sampling the STOP input on each ling clock edgein tre middoal the Ts lates, Outing ‘the EPA instruction, both EPA nsruction worde ae etched but any data transfer or subsequent instruction fetch is U7E D mm 9984043 0011905 9 mm T-49-17-07 Postponed unt STOP is sampled High. This raesh ‘operation does not use the rolrosh proscar oF is ‘vide-byfour clock prescale;ratho,it double increments the reftesh counter every ties clock ole, When STOP le found High again the ned rekesh cyto completad, any Fomaning T sates of the IF; cycle ae then executed, and ‘the CPU continues. operation. + Oe Figure 16. Stop Ting oyZILOG INC INTERNAL OPERATION Certain extended instructions, such as Mutipy and Divide, and some special instructions need adctional tine forthe ‘@xccuton of intemal opartions. in theca casos, tho CPU. ‘9008 trough a sequence of internal operation machine WE D mm 9984043 0011906 0 mm 7-49-17-07 cycles, each of which Is thee to eight clock eyeles long (€igue 17). This alows fst responso to Bus Request and Frosh Roques, cause bus requestor relresh cycles canbe insarted athe end of ay intonal machine cyco REG, 8, Figure 17 nal Operation Timing HALT AHALT instruction exacutes an united number of cycle itornal oparatons, inerspersed with remary rlresh foycles whenever requostod. An Interrupt, segmentation trap, or eset are the only exis toma HALT ineruction.. ‘The CPU samples the A end SES inputs athe begining of every Tycjele Wan nputitound active ding {we consocutve samples, Ine subsequee IFy ele 8 fwaased. bul ignated, and’ te “normal ntrupt _acknowedge cyt stad 186ZILOG INC MEMORY REFRESH ‘When the.6-bit presale in the reftesh counter has been decremented to zero, a relesh cycle consisting of tee “elots is started as soon as possible ha, ae the ext IF, oy o Internal Operation yet, “The®.itresh courtor valve ieputon helow order side of the addtess bus (ADGAADa}; AD;-ADis are undetined (igure 18). Since the memory is word-erganized, Ag Is always Low during rettesh and tho rete counters eye A7E Do mm 9984043 OOLL907 2 mm 7-49-17-07 incremented by wo, thus stepping trough 256 consecutive Fetresh addresses on: AD-ADg. Unless disabled, the presollabe prescaler runs Continuously and the dey in ‘Staring arefesh cycles thereto not cumulative, nile STOP inputisLou, continuous team of memory ‘ehreth cycles, each thee Tslales lang, is exocuted without Using the retesh proscar a) g a t Figure 18, Memory Refresh Timing RESET ‘ALowon ho FESET input causes the folowing resus lthia five clock oyels Figure 19) 1 AD AD spare Stated 1 FS, DS, REG, ST STs, BUSAOR, and M70 High 18 SNo'SNgare forced Low 1 Retroshis sated 1 RAW, BAT, and NS ae not atoctod forced \When FEBET has been High for three clock periods, thee consecutive momar readeycles ae exocutedin the ystam mode for tha 28001. The 2002 has wo consecutive ead oycies. Inthe 28001, the ret cycle reeds the flag and coil wed trom locaton 0002, the next read the 2 program counter segment number rom location 0008, tho noxt roads the 16. PC ofa from lacation 0005, and tho flowing fF cyte str the program. In the 28002, tho fist cyclo reads the flag ané contol wor from looaton (9002, the next reads the PC from location OD04, and the folowing IF; 0ycl starts the program, 6ZILOG INC A7E Do m™@ 9984043 0011908 4 mm I 1 T-49-17-1 . A, . ci eS ) a A, i Ps t : ‘ ag r+ ey ' | : i ! i | 4 ¢ ! g oa | & ra | | | | Cc a s t a a 07ZIL0G INC ED mm 9984043 0023509 6 mm COMPOSITE AC TIMING DIAGRAM ae a aw | eeZILOG INC U7E Dm 9984043 OO1L910 2 mm ‘AC CHARACTERISTICSt 7-49-17-07 ‘zaooni2 za0owr2 zo0oHr2 “4M ‘omits ‘omiz Number Symbol Parame Min Mox Min Mex Mn Max 1 Te ‘Geek Gye Tne 2502000 165 20001002000 2 Wor Clock wth igh) 105 1995 70 1900 «40.1980 3 wa ‘Ceck Wath (Lop 105 1995 70 190040080 4% ‘Ceca Te 20 10 10 5 i (tock ise Teno 20 16 10 © TaOGNY Cock to Sopmant Number Val 0 ploach 130 110 0 7 TéONA) Cock Sopmant Number Not Va 2 10 ° 8 TdC{B:) Clock to Bue Foat 65 55 50 2 TdCHA) Clack ta Aas i 100 75 55 10 Tels) __ Cock Ho Adoss Flot 6 55 © 11 TENOR) Adee vidio Read Daa Required Vala ae 05° 10" 12" TWOR(C) Read Dato Cocks Setupsime 30 20 0 13 Te08iA) DS to Access Ache eo “6 20 14 TeC(OM) Clack Horie Data Vat 100 6 Cy 15 THORS) Read Dalat DS Hold Time ° ° o 16 ToOWVOS) Wide Dats Valdto St Delay 235" 195" 110" 17 TAMA) ——_Adctos Valeo REG 4 Dtay 55" 35 2 18 TdO(MR) Cook Ho MRED Daley 0 0 60 39 wwRn REG Wish High) 210° 138" wo 20 TaMRIA) —_ RED Ho Adress Not Ate 0 ast Ea ‘21 TaDWOSM Wi Data Valse DS (te) Delay ca cs 1° 22 TOMAR) TIRED tio Res Data Raqures vaid sro 230" 23 TECQUR) Clk REG Dalay 8 © 24 TEAS) —Clak ttoAB Day % © 25 _ToNAS) _ Ades Vit St Daley 55 35 20 26 TEAS) Clk Ito St Delay % 6 27 TaASIOR) Ato Read Dasa Requted ais 220" 40" 28 TaDSIAS) St 1oAS Day 70 3st rs WAS. Swot Low es st sot 30 Tass) FBtto Adios Net ate Day 0 ao a ‘31 TaA(OSA) Adress oa! 9S (Rene) Delay, ° ° ° 32 Tass{osR) ABIDE (Rese) 40am eo ost a0 83 TaDSRIOR) DS (Reac)itoRead DataRequted aia 20s 10 m0 4 Ta@S) Clock 110 BS t Day 70 6 % 5 TeO3]0H —_ FB tov DataNorvaa 15 25 38 TSAOSR) Adress Valaio DS fad) Delay 10" ca 37 TéOIOSF) Cock to DB Rene) 4Daay 20 8s 6 38 WOSR OS (Rosey eth Low) 28" 105" 10" 88 TO(OSM) Cock to BE (is) #Deey 95 0 65 40° WOSW BS (rho) Weth com) 05 110" 7 "Giak oie depandel charac Seo once A Cae, - {ntsinraronsan eh 189“ioc tin doer Staci, Sea Fc oN Croco *Oeirinnaoeeconds ZILOG INC V7 Do m@ 9984043 0012522 4 mm AC CHARACTERISTICSt (Continued) Uae ‘ooo ‘zone “nr? ‘ue une “ome Number Symbol Parameter Min Mox Min Max Min Max 41 TaOS(OR) _0B(V0) Ho eadData Required vad ‘90° 20" 0° 42° TdOI0S)_~ Geoekt 108 (10)4 Daley v0 %0 6 430s BS yoywah eon 10" 25st 0° 44 TaASIDSH) —_FBH0TS Mcknonedge§Doley 1065+ wo 410" 45 TEOIDSA) - Cheek tto DS (oknawiede)4Doay 10 85 n 48 TaDSADA) BS Acknowledge) bo Road Data Roguted Oslay as tes 47 TO) Clock State Vi Day 110 5 48 TeSAS) Stasi oS Day 0° wo Ea 48 TRO) © FEBTioclckt Sep Time +80 70 0 20 TWA) —__PEBETioCiockt ald Tne a a ° a 00 70 % ; 82 TeNMKC)"—Riiloockt Setip Tino 0 70 © 82 TO) Wi RToGackt Sato Tino 0 "0 © $4 THM) TL RWioGeckt Hote Tine 20 20 ‘0 85 _TESGTO) —_EEGTiaClockt SeupTine 70 5s «0 % TSGT) —_EECTioGioakt camo ° ° ° 57 TENG) = ltoClockt Soup Tine 100 10 0 5B TeMliG) ‘to Clsk Hold Tine ° ° ° 88 TECMO) —_CoakttofFO ely 129 8s % © _TETRG) —_ETOPloGhaks savy Tino v0 400 0 61 TSTHG) STOP eck Hone ° ° ° 62 eM) WATiocieckt Soup Tire 0 20 20 63 THC) Tio ciocktHolsTme 0 0 5 64 TeBROC) — BUEAED Glock Seep Tine so eo 0 @5 THERA) —_ BUSAEToGockt Hod Time 10 10 5 © TEOBAK) Clock oBUSACR Daly “00 75 rs 87 TACIBAKY Cocke BURR 4 Daley 100 5 cs 68 wa ‘ase Vad 160° 5° 0° © ToS) BB trostaTUS Net vaid so ost 20°ZILOG INC 27E D Mm 9984043 OOLLIL2 & mm FOOTNOTES TO AC CHARACTERISTICS 1-49-17-07 aoc e002 zaoii2 ‘amie ute ‘omie Number symbol” _Equlon Equation Equation TT TANGA) ——-ATSO + WCH— TaD —«ATSO SCH ~OSmme—~FTaO 4 TWh One Cn ed Wel = 258 Wot ~ 2008 18 TED) Te + THOR — BOS Tee + Woh = 40s Tel + Wh = 808 7 Tangy Woh S008 "Wen ~ 3518 Woh = 208 19 Wh 120 40m Tec - 90n8 Tec ~ 208 2 TSAR)“ wCl = S5e TWOI~ 358 Wal 208 21 TaOWOSA) Ch = Bons woh ~ 388 Wor ~ 2508 2 TaROR) Teo 13008 FIeG ~ 100r8 eo ~ core a ee ‘wen ~ 35 8 won = 2008 2 TeASOR zoo 408 PoC - 1108 2TeC ~ eons 28 TESS) WHOL SBe eC ~ 850 WO Bre 20 was Woh = 2078 TwCh = 15r8 woh — tone 50 TASK) THO S88 Ct ~ 2518 Wot ~ 208 52 TAASOS) TOL 268 Wot 1808 Wo t0ne 53 TOSROA) TECH WOH~ 16008 Te + THO = H05ne Te + TAC ~ 708 3 “TaDSOM) ——~TCI~ 900m woh ~ 258 Wi ~ 18 a ee Teo ~66ne Te ~ 3518 se WOSR Tek + Wh ~ Cone ToC 4 WCh ~ Som Tel + TwOh - sone 40 WOW Tot 6508 Tec ~65ne ToC - 2518 41 TaDSKOR) 2700 - 17008 lec ~ 12018 eG ~ Bord 08 Heo ~ 60a Feb ~ 168 Fee aOre 4 TASOSA) MTEC 4 TH - KOs 20 + Wot ~ Aone {106 + 901 ~ 30mm 48 TeDSADA)—ZTEC + TWON~ 160n8 FTE 4 TCH = N05n8 Te + THC ~ 788 48 TSS) Oh Se Won - cOne TWO = 90r8 Wa TeO = 80ne Teo- 7008 Tec ~ 508 68 TOS) TOI ~ 258 WCi~ 16 ne WO ~ tons Weng a Carns = Wei cea we cea Wie 2287 : We easy Wie" Yeo=04 1ZILOG INC 27E > mm 9984043 0011913 6 me ABSOLUTE MAXIMUM RATINGS 1-49-17-07 Vetags on a pine wih epee mn ont tn ied oa or ary soar onatie -caviestay Sampemmetcrnan ee cea tata eat ‘Operating Ambient ‘tortor ere oth spaces en epi eases “rperaure ‘See rdeng torsion Siac oy tas ee i sorage ampere Nesey 16050 Se : vd Pte may ae STANDARD TEST CONDITIONS ‘The DC characteristics below apply forthe folowing tet condions, unless otherwise noted. Al volages ere felerenced to GND (OV). Postiva current flows nto the referenced pin ‘Avallable operating temperature ranges are WS = 0°10 +70°C, +4,75V, 24-Pin Gea Arey (POA), ‘View toward PC Board 5 Bottom View |NoTE-Pectape dimension se gienninnes.Toconven omnes, yy 264 565