DSDE 152

Digital System Design

Lecture 3: Implementation
Technology Trade-offs
Spring 2021
Dr. Shawkat S. Khairullah
Department of Computer Engineering 1
University of Mosul
 Implementation Paths
Integrated Circuits

Flexible Hardware

ASIC Standard Fixed Hardware

Fixed hardware

Full-custom Semi-custom Processors SSI/MSI

Gate Array
Custom ASIC

New SoC\SiP Flash Static Fuse/ E(E)

start anti PROM

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Performance\flexibility trade-off FPGA C/PLD
 Implementation Trade-offs
• Providesdefinite implementation paths for designers with estimated costs and
design-times.
• Particular devices can provide speed and low-power but without post-
fabrication design flexibility.
• ASICs (semi) provide flexibility and low power for designs, but with larger
financial costs and substantial design-times.
• Standard provide lower cost off the shelve computing component and shorter
design-times, but possibly providing lower performance and higher power
consumption.
• Financial cost plays a major role in deciding which path an initial design 3
implementation will follow.
 Standard Device Technology
• Standard devices are typically off-the-shelve computing
components.
• Provide low cost solutions.
• Power consumption and performance vary between devices.
• Devices re-programmed by software, i.e. limited flexibility.
• Inherently sequential, limited parallelism exploited.
• Short design time.
• Several different device technologies available including:
Microprocessor
Microcontroller (Harvard, 8-bit to 64-bit ) 4

DSPs, (32-bit)
 Semi-custom Technology
• Semi-custom designs provide sub-optimal implementations,
i.e. power consumption can be modest compared to full-
custom and execution speeds are lower.
• Non-expensive compared to full-custom.
• Designs can be altered after fabrication, i.e. re-programmed.
• Design times can be less as standard cell and gate arrays are
pre-defined components that can be easily incorporated, 9-12
months .
• The trade-off of performance to obtain increased flexibility
and lower costs has seen the creation of programmable logic.
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 Full-custom Technology
• Full-custom
designs can provide optimal implementations, i.e.
lowest power consumption, fastest execution speeds.
• Expensive.
• Designs cannot be altered after fabrication, i.e. no re-
programmability or design flexibility.
• Design times can be substantial up to 18 months.
• Designs re-spins are often required increasing design time.
• Example ASIC chip application include digital TV and VoIP.

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Design with Multiplexer &
Decoder

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 Logic Circuit Design using Multiplexer

Advantages: I0

I1 Y
 No need for logic simplification. 2n inputs
MUX
 Minimize the IC package count. I2
1 output
 Simplify the logic design. I3

Enable (G) S0 S1

n control inputs 8
 Multiplexer Function

Truth table of a 4:1 multiplexer (with enable)

Enable Select inputs Output
E S1 S0 Y
0 X X 0
1 0 0 I0
1 0 1 I1
1 1 0 I2
1 1 1 I3
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Y  E.(S1.S0 .I0  S1.S0 .I1  S1.S0 .I2  S1.S0 .I3 )
 Implementing Digital Functions using a Multiplexer: Example
1
I0
Implementation of 0
I1
1
F(A,B,C,D)= 0
I2
I3
∑m(1,3,5,7,8,10,12,13,14)+d(4,6,15) 1
I4
By using a 16-to-1 multiplexer: -
I5
1
I6 F
-
I7
1
1
I8
I9
MUX
NOTE: 4,6 and 15 MAY BE 0
I10
CONNECTED to either 0 or 1 1
I11
0
I12
1
I13
1
I14
1
I15
-
10

S3 S2 S1 S0
A B C D
Thank you

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