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    Solved question paper CN

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    © All Rights Reserved
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    159 views33 pages

    18EC72 Solved QP

    Uploaded by

    bkthejaswini2013
    Solved question paper CN

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
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    of 33
    treated as malpractice. 328 on the remaining blank evaluator and for equations writen eg, 42+8 = 50, wi 2. Any revealing of identification, appeal Important Note: 1. On completing your answers, compulsorily draw diagonal cross CECOCCHENTE USN olvfol fs felc ol6l¢] 18EC72 Note: Answer any FIVE full questions, Seventh Semester B.E. Degree Examination, Feb./Mar. 2022 VLSI Design hrs. = Max. Marks: 100 choosing ONE full question from each module. ‘ Modute-1 With necessary circuit diag agra, explain the operation of tristate inverter. Also realize a multiplexer using tristate inverter. 1 . (08 Marks) Implement a D fipflop using transmission gates and explain its operation with necessary tining diagram, (08 Marks) Realize CMOS compound gate for the funetion Y = A(B>C)+DE (04 Marks) oR Explain the operation of MOSFET with necessary diagrams. Also derive the equation for drain current in linear and saturation region of operation. (10 Marks) Draw the circuit of CMOS inverter and explain its DC transfer characteristics. (06 Marks) Explain the following non-ideal effects channel length modulation, mobility degradatio (ot Module-2 Explain CMOS n-well fabrication process with necessary diagrams. (12 Marks) What is scaling. Compute drain current, power, current density and power density for constant field and constant voltage scaling. (08 Marks) OR Draw the layout of ¥ = (A-+B4+C)Dand estimate the area, (08 Marks) ‘Mention different types of MOSFET capacitances and explain with necessary diagrams and equations, ; (06 Marks) ‘With neat diagram, explain lambda based design rules for wires and contacts. (06 Marks) Modute-3 Develop the RC delay model to compute the delay of the logic circuit and calculate the delay of unit sized inverter driving another unit inverter. (OB Dtarks) Explain Cascode Voltage Switch Logic (CVSL). Also realize two input AND/NAND using. CVSL. (06 Marks) Explain linear delay model. Compare the logical efforts of the following gates with the help of schematic diagrams : i)2-input NAND gate ii) 3-input NOR gate. (osytares) OR Explain : i) pseudo nMOS. ii) ganged CMOS with necessary circuit examples. (06 Marks) Estimate iyrand fu of a 3-inpat NAND gate i the output is loaded with identical gates. Use Elmore delay model. (08 Marks) Explain skewed gates with an example. (06 Marks) 1of2 —=—— 18EC72, giao fies.) Module-4 th necessary circuit diagrams, explain resettable latches with i) synchronous reset ‘ ii) asynchronous reset. (08 Marks)” Compute the output voltage Vou it ies a ey con ae tatte Voltage Veu in the following pass transistor circuits. Assume V,= 0.7. Voyart_p— Vout Viows3¥ ' os a Ved ns UL ala fT T IWS sv sv sy SV 8V 5 Fig.Q7(b) (06 Marks) ¢. With necessary diagram, explain a D flipflop with two-phase non-overlapping clocks. (06 aris) OR 8 a, Withnecessary circuit diagram explain 3-bit dynamic shift register with depletion load. (08 Marks) b. Realize (AA, +B using dynamic CMOS logic. Also explain the cascading problem in dynamic logic with necessary example. (08 starks) c. Explain the general structure of ratioless synchronous dynamic logic with relevant diagram, (04 Marks) Module-5 es diagram, explain the operation of three transistor DRAM cell 9 a, With necessary circuit diagram, explain the op es ». Explain full CMOS SRAM cell with necessary circuit topology. (08 Marks) cc. Explain the terms : i) Observability i) Controltability Per iif) Fault coverage, OR ‘ (07 Marks) 10s, Whatisa fault model? Explain stuck-at model with examples. b. Mention the approaches used in design for testability. Explsin scan based testing 16s necessary diagrams, (06 Marks €. Draw the circuit of 3-bit BIST register and explain. 2of2 Ke eae = Gui cit Design ) Scheme q Solution prepared by bh) Dr. Vikos Baliked au 2): Prof Berpak Sharma ge wero” % Head of the Dr Dept. of Electronic & Cor KLS VIL, HALI i ‘Karnatak Law Society’s ‘Vishwanathrao Deshpande Institute of Technology, Haliyal - 581 329 ‘Doe. No.: VDTT/ACAD/AR/OSb Rev.No-01 ‘Page 1 Rev. Dt: 25/08/2021 Solution and Scheme for award of marks AY: 2021-22 Department: E&C Subject with Sub. Code: VLSI Design - 18EC72 Semester / Division: 7 /A&B Name of Faculty: Dr. Vikas Balikai, Prof. Deepak Sharma Q.No. t Solution and Scheme ‘Marks Module ~4 day : Tristate Thvercter oF Q.No. a Solution and Scheme bY D_ gbpglp using — trancmisgian gate cle ; BE po AY ac ce | Tele og clk. D Gm) IS txplanodion with Truth table — Urry [Q.No. Solution and Scheme Marks tc) Realazation of Cmos gate tor Padtdown network ‘y= ACB4C) +DE ACerc) tDE rs ee ‘4 OR (Ponaltet’) Wwe Ue AND AND (ervies a raed Neher OR (porallel) Pall up yvredusrk oD fara: ae ae A(e +c)4D¢_ on ano off a og OR of AND CMOS _ those . wl cr & mo ef oft oY [Q.No. Solution and Scheme 2a) Case a) Curd off region, Vgs V+ and bt Vds< Vgs-v4 + ras vad ee rae Increases with Vy Vas—V4. pinches indepenctente “tf of Vas Cums) [Q.No. Solution and Scheme Cro Sectoral views of mos a s J id | | Non- sadurated sugion RE Brag oe ate Art QHCV= Co Ve P= Aye booty Schone = Cq Ovgg - Ve ey Cq= EouWl = Cox WL om usher Cox = box y B Ve ue Y Has o Tage Ochannel = C4CVg. -vs ~vae’ TE pe a Vas at Tae oo oor © (Va, “Ver VAs) Vy 3. Conant 2 in Anton sg1en Sadwotion — swqien Subst. 4 tate \éls = Yq.) Pa Meow] Yp-vi ~ G0 la) = MM Vgs ~ vt)” = Aca ( s a eat Vgc Wy Soka dis ie -baia (Gene [Q.No. b) (ac) ea0s _tnverte Valsp =(\5 a Vous.) 8m) Vows Vic —@m) channel ength modi — Euplanation coi th eqpation fx Lats Be BIL, (14 Mis) — Gan) : a Mobility copaclasion — explanashon with etal 2 Koy = Sue Cro - V-s & = WEIS taints Toy oerreameee ke ee Lane ie Lely ster ste] OES Ve — nm caret Kou ae @2am) Solution and Scheme Marks Q.No. Solution and Scheme Marks Soduute = 2. 3a Explanodion of CMs cnet Paocess with Necessary Aeognrems and masks for Hu follooing skps. — * n= wel — formation Cn - wet mask Rake { romadti nn Cpolytilicen mask) » yt Aff uss ion regions (nt af fusion mark } * Defining PF suis Cpt aitfution mask ) ¥ Contact Gd — chafirition Cine Prask » metallezation (Cmotal m4) — 66 xoo mn tach, b> : ae iin with doegnam — (x re Draon pues ay WW Ws, boy = fou eo s % ] Le ' Ny = Np #8 Ne= Maes No. Solution and Scheme Gorsant field scaling Covet t)= kn! [> (Ves) ~ Ve) Veet |= Ske 1) 2 meae 2 84 “svi ae Consort “Voltage Scaong Cao Tia? Be! f 2 We Yada ~ Wr] T= sske[ 2 [Vac “Vre) Vne-v]= 8 ay Cava density = Th _ 2 S.Ep Ama aoe TS ' ; Power dentty= p' rival Ama A suo [Q.No. 40) Solution and Scheme | Layout noaprare of y= (t8tc)> —Gm Aswa Scum ah ¢ estimation — (2m) = Gm) g Ub) Es y F fo | nt trofe VG pe : eer | & model <— Lm I Cas Program. - 2m) exp low odton of oxccke seated Capacthantes with Cab , Cas & Gs eqrations —Co2 ). Eulonatsen ey jancin Capacitance — with five jorction Capactlance ineli cation —2m) aa a Erne LE hy | NW NN List SN 2s SS Heigl 7 SN EXVU= Yen taal S S | iB Ne ial ba sath = SHEA =4or Solution and Scheme Marks Euplan agien 4 dasiga sul fr ORE—H redo Maal2 Diggusion . : L 4n mia 4a vir Explanation of design rurles for tomtact —2™ | ~~ Q.No. i Solution and Scheme | Marks \ Module ~ 3, Si a tip lanadion of fective susittan y Capacitance, ewtt racessoduy notodtimns — G2 my Bglonadson of gore and Avffrusin — Capacitance with — wecetomy — notations —o2m) eqpsdvoderct crroust 4m) os ee “pee A Nor de T 7e ¥ ec g ¢ de I” Te 4 I ; +T° i 5b) explanation of Cas cack voltage swith Logic Gm) Two input pvp [Nand using Cvs. —~ Gsm) ; Von 06 Spock, 7 a Zl @ ao C, [Marks [ Q.No. Solution and Scheme BC Explanadion of area, delay modl with the 2a ack ro d= {+P Gam Logie at | apd Crmpuc ation, 2 ilp NAND a tlp Nog a att & 8 é Cc £ r~ ¥ £ I of : 1 Cine 4 § Cina Logacat ayporl Q= U-(oam) Gee i Ee 3 — Cum) \ A modifies veminn § Coos fecknolepy is Vrms as Pseudo _nmoy , wa Which Prd 7 wed as (oad meted S, leplape raoifet. Se > ACB) te Pe , Cewek ferry % Lis if aS pe H eae nos T ia Syplein 1) Pseudo -nmes i) Garged Cmtes wila wecesgany Cistui{ erangley Meudo nmes Vs ts 4 gales lac luk adguate vaio fw Baawer is seldteD. Tt bor ob, a4! pays Brow In oddiba le Capacihive load an eau fp 3 one unit as Mm fratity g ard be Gods i[D- Veede nos Las afl Spead 5, (a. ares. Change Coos Bu fois lype § Grvutt wher Baw [Boos # Cpuad Le unthy Mien Un crit becomes clafudive Ww habe. Te olp B 4 when Ip i O00 Sol Oo when HP is IU. Ry be ory Bh. Onrbinatios — Vop auts Shatol be Vis | home Pate | Plone # I. olen the wafo eadny ten unity tu Pulao travis — will bawe bi(las Siokinp Oblity duu CH Wak a Nok Why aabio i gyrate her unity, tun, Jutlderg bun usu Grkinp ability, pun dt bebenes oy Nand, Btn >) ee abi loop Bie (1tS5h)C R= Rate tly “, Llmove delay mode) fw fury lp Ser 4 tame @C producty dys 200m) + 2 Chere) + 15h) [Ret Ret) a : lp rand aae =) oe rm ) Soy Explaio Slave gates wi aa TH om J tte ip bansiben ib mere flon te ett 11 woul Ab a prenemency ‘ners a5 Sheaome Ur skeso= gates fore Tee ring ofp Yaarfery Lo-shuo got, fywew delliy 1p Presi ben Srornple erample inverkev unsieeved ae “Lg 1 A eee A wc od Le mg im a <, Unstened 3m eu MODULE 0& Loi veustay — Crewit digpramy , ep lain Teschablo lah wilh §— 4) Cyahromoy wad 7) atyachms e Syrnto le L- ved Most pradiead aa Lorman Tepuive a teref Syma te ent 9 ma inihal She om Save Jaw ave Me typer S$ wee mechanism Yadcamas g O.syn Chromo . syndrom few he @ lo immraediiafels white Gynchs mous rerct wails br tur Cock. 2 ae q-a Sepncheromous ear vad mut be Sable bw a Continua) hep G lnotd firme rile tus Aaynchyarsiey Fad B Cheracterirel oy Ppropatebe delay Synchorensay aad 4s Srmply sepury ANDing tee D ify wrt There. mobomog vet Beypuves gating Wola Mdele % te fpedback + fre Au veset indepercdct So ¥ Cock Tb Gmpude te olp in “lu Kellaong Pas froasitbe Asvne “sepa Yared ple Vat A he Az WBS Vad = BV Ts | ae & 4 SLL Lp a he de3 Bs A C243 Me Vout = “ay Gay [204 Wdh veusten chiegram, expla D {yp flop whl. poo Phase verlappinp — Clocler na non overlapping Properly 4 bi 2 clock Sj fees ful a a qren Pee, ah One bus Clock sph Gin be achve. A153] Combicabindt J] Orbit Groban [=f ks a iB ee ya Pe ay i be a < 6 oe | p? When clock 0. is ae ip ae @ a A (Stews g Rave applied thae/p Poss frane a iP Capacetmes S Shye 2 aekin fren Preview va Lue. Wa all us te incorpate a dy none remem 3 stage aleplafion [oad mores dynarnic (tiff wencfen Z & Mm | | &a Uih —wecescay tiagram oxplio 3b Ghf{t res (anaenic) Hpk a Pywre Shas a somple depnaenic TpiSlew elnmerl| m bet nm & Cres versione Dues idiegeee Te ? tasing ther dynamir wgifer erred, 9 dynsitic Shalt wepistev Go Crafudd. A flee bit Sete wepister is as Cheon betas . Gt [eat aj bifo > eRe ea AS al i fe} an by %) i : Heve Lp. = Wad aah RD= Rood - Omes Verging uses brangmigsizen qote: When che tte sip Sif gels Prmten tek invev p bufhe Slsn tae hgh tu, te Git ad Shel -¢ fay te 3b Sift wegiste Getranes a ‘ Br cult jusd am eveslaypry cleda fe & é4 Hla dite Gn be Bfler ad af te ofp Ode. Bb Ho lek Realize Fe Ailafat &/B wing clynomic Cros Gyre Noo explia Te Caednp froblern in dlynannie hyic Worle waceasany CKams)(e y Eee 4] Congdy a wes |p nad gebey ee Ay fl { lt Ae Roce/ : hilar Wa ten Dee a te ache f te abwe ctf lola ile Srratuods Rel TE ea eee i Srna ie aie ao Sxpecth stots i T Cartes shile A Accovdng te We Gyen Ip Noyso & Vope) « Rt trove dre Second olp will net be in fe expect Stat. Jre crease © Vp) wil! vol Gp leo Ia) being Coscodnp me Su te oh 2m sunfft if Capacitance 6 chic cheyed Complely 3-0 Cubic) thento btere will be a gmat? prpajabin, diay Bub as C=4, Vor will go lao Tt cal( naf-go bufh udPl vert preclarge pare Pau we love Gn ersenoy ofp. We problem is solves by addoy 9 te ten 2 shape. day retry Te daar bape Lege te P ke aha gue: G5 | Expleon the gerne! Shu cduve 4 rebels Spclrmey ynamic logic with ~wolovoud chiagram LM Ho | ‘ie ao > 4 Yop BEEP -L als ala a vi! iE mad (eee su] Ten Tor), For “for | [ t te Under raboed lege Th valid ofp volfope 9 encl, Shope is Shidtg determined 67 diver load eho. Unde, qalroloas Syncharmoes legic in ovdu t Grieg Promshe a gic Wifh wel afte Change Sbamuy tie vahe FL Capa fs Cnt [Cin musk be on made laye crop dLueimp Grut dog Gree Pre vali lige [ao g Vas 0V fon be achieved oupardlass § deve + load ahs, fas ct a TS bay as wabroley dynamic legre, Z [Fat Wits naceiseny cee fB2 cout dignem, explin 27 pero i BT Dynamic Whimpin -" ee | oo depletion | plc | m1 Lot RB | T a1 we Bo " | ! Vee | | LORITE Opovabien | When we=i ,RD=0 Hun 74 & ON. The Codent Pred on | Bus will be Stored as chovg on gate tapactane § Tr. waitten as chavee on” When wes! Ppa + Th any Value i Bere Gpadlone 4. T2, in tre previa cyte, tien it Gn be Rod via teanttfov Tr & Russ Again, we Gn 200d the value Sed om is preva Lyle ov Tr by making WReo & Del. When PD21 Hen TZ th ON G T2 Will abo, be bv we $ Charge prrtect in Gate Capacitance. tefus 73 & Ta bok ae ON ftp. forma daed Grunt te gond. Aud esethe bas ger cunadkad to Giound via T2 § Ts. Hence’ O will be road ia place ¢ A 2n Gpacitorvolue wi RV | Operanon Femower iaifielly “$v 0 0 Held ou oO 4 Read BV ey 0 vorite / eak. Ging fue gate car hes CV omit 7) BPed value will a loth o i is Bus ie pellet te Grand. & Logic OB Arad be lage 4 Ovi dod fw 0) Write wile tla gee (a pacrtante 4 TL ow Rood Moran Ts if f Qay Poy value B . pred Ve Rent fromts 19 Ua complimented fam Weak. Tamme Tz in Gmnp needed Layout ig Vp Bus A weRP G.b Slo Zyplaio hw (mor seAm wy wile \ecostam act Fopolagy gm SPAM meng Ck are osigred 4 pesrnrd qu ay mdifichon 4 data bis te be chyed > army as UR as otfivel on denand ath Dezondng on Pre presened Sfatr § La feo invert lah deurif, fhe data beinp had 1 memeny CH will be interpreted efea os \gie Ow F Os for tar nmat pes hoensisfors owe implenuty te Gnned the 4-64 SRam a b de Crmpleranhog (inas pp bit fugc ae at Boas pala L bit SRA cout Bend Dog Lae can ene Yue @ Symbolic “weprese date () (free Graaf on, epbtegy op bflwec bE Pee | al | oral ee 209 full Cros SPO col No load ray be “poly silica, wesishrs, dep lebron nmas Om Pruns Aepoudlns om “type J rence. | | 7b ConP ned) Ove maym chevadarpy G Une area Te we % Basichve load wwerles wila undoped Poly silicn gescting we inte baht. Lhuchwe frpica ty sus in a Tr Canfi, Mee Gmpad all

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