Basic VLSI Design (20A04606) UNIT-II IfVin =0 Volts T3=OFF so T] will be non-conducting T4=ON so supplies current to base of T2 which will conduct and act as a current source to charge the load CL towards +5 Volts. IfVin =+5 Volts Td-OFF so T2 will be non-conducting T3= ON so supplies current to base of TI which will conduct and act as current sink to the load CL. discharge it towards *0". Advantages: + Cywill be charged or discharged rapidly. + The output logic levels will be good + ‘The inverter has a high input impedance + The inverter has a low output impedance. +The inverter has a high current drive capability + The inverter has high noise margins. Drawback: + There is a DC path between Vop and GND through T; and Ti, Due to these there will significant static current flow when Via = Logic 1 + When Vis=Vop, T= OFF and no conducting path to the base of T2 . + When Vis 0, Ts-OFF and no conducting path to the base of Tt So it will slow down the action of the eireuit. BASIC CIRCUIT CONCEPTS The wiring up of circuits takes place through the varions conductive layers which are produced by the MOS processing and it is therefore necessary to be aware of the resistive and capacitive of each layer. Sheet resistance and a standard unit capacitance helps greatly in evaluating the effects of wiring and input & output capacitances. The delay associated with wiring, with inverter and with other circuitry may be conveniently evaluated in terms of delay unit +. SHEET RESISTANCE The concept of sheet resistance is being used to know the resistive behavior of the layers that go into formation of the MOS device. Let us consider a uniform slab of conducting material of the following characteristies Resistivity- Width = - W Thickness - t Length between faces — L N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 14Basic VLSI Design (20A04606) UNIT-II tot i + Resistance is given by Rap = 2 0 + The area of the slab considered is given by A=W. + Therefore Rag = 5" 0. + Ifthe slab is considered as a square then L=W. therefore Ras=p’t which is called as sheet resistance represented by Rs. + ‘The unit of sheet resistance is ohm per square. Tims the actual vanes associated with the layers in a MOS circuit depend on the thickness of the layer and the resistivity of the material forming the layer. For the metal and polysilicon layers, the thickness of a layer is easily envisaged and the resistivity of the material is known. For the diffusion layer, the depth of the diffusion regions contributes toward the effective thickness while the impurity concentration (or doping level) profile determines the resistivity. Typical sheet resistances of MOS layers are tabulated Rs ohm per square Layer Sam Orbit Orbit 1.2nm Metal 0.03 0.04 0.04 Diffusion 15-100 20-45 20-45 Silicide 2-4 _ _ Poly-silicon 15—100 15-30 a- channel 10* 2x10* p-channel 2.5X 10° 4.5.X10* N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 12Basic VLSI Design (20A04606) UNIT-II Sheet resistance concept applied to MOS Transistors Consider the transistor structures by distingnish the actual diffusion (active) regions from the channel regions. The simple n-type pass transistor has a channel length L = 22 and a channel width W=22. Figure: Resistance calculation for transistor channels Hence the channel is square and the channel resistance is 2a A sa Ry = 710" = 10K Here the length to width ratio denotes the impedance (Z) and is equal to 1:1 > Consider another transistor has a channel length L = 84 and width W = 24. ‘Thus, channel resistance paren eR, = 108 = a0Kn “two wes 2 The length to width ratio, denoted Z, is 1:1 in this case. The transistor structure has length L=8 2. and width W=2 2. Therefore N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 13Basic VLSI Design (20A04606) UNIT-II ‘Thus chamnel resistance R=Z Rs=4 x10" ohm Sheet resistance for Inverters Vos ‘4 * Sy = 4 Rog 4 Rg 40K. ou’ Ma Joo 80:28 1 : di ‘oaMoe ag aan Zag = 1 Ron= 1. Ayn = 10K Pul-up: Pulldown ratio, Yes. Zu pn 4: this (@no) fa u'Zn (On resistance (Vpp to GND) ‘A ratio rule does not apply and there is no = 50k2. static resistance from Vag to V5. (@) nMos (©) CMOS ‘Note: Ray = on’ resistance; Ry = n-channel sheet resistance; R= p-channel sheet resistance. Consider an nMOS inverter has the channel length 8A and width 2) for pull up transistor as shown in figure L=8A;W=2h Z-LIW=4 Sheet resistance R= Z.Rs = 4 X 10'= 40 KQ. For pull down transistor the channel length 2 and width 2), then the sheet resistance is R = Z.. =10KQ 1X 10 Hence Zp.u to Zp.d = 4:1 hence the ON resistance between Vpp and Vss is the total series resistance ie. Ron=40KQ+10KQ=50KQ Consider the simple CMOS inverter as shown in figure 2.3. CMOS inverter Here the pull up transistor is of p-type device with channel length 2). and width 22. Z=L/W=1 Then Sheet resistance Rep = Z.Rs =1 X 2.5 X 10*=25 KQ The pull down transistor is of n-type with channel length 22 and width 2, Z=L/W=1 Hence, Sheet resistance Ray = ZRs= 1 X 10*= 10KQ. In this case, there is no static resistance between Voo and Vss Since at any point of time only one transistor is ON, but not both. ‘When Vio= 1, the ON resistance is 10KQ Vin =0, the ON resistance is 25KQ N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 14Basic VLSI Design (20A04606) UNIT-II ‘MOS DEVICE CAPACITANCES Area capacitance of layers From the concept of the transistors, it is apparent that as gate is separated from the channel by gate oxide an insulating layer, it has capacitance. Similarly different interconnects nun on the chip and each layer is _| Conducting plate 1 Insulator —T Conducting plate 2 For any layer by knowing the dielectric thickness, we can caleulate the area capacitance as follows separated by silicon dioxide £ofinsA ie Farads Where, A is area of the plates, D is the thickness of Sio2, €0 is the permittivity of the free space and Cin, is the relative permittivity of insulator (Sio2). ‘Typical area capacitance values of MOS circuits Value in pF X 10*/ wm (Relative values in brackets ) Layer Sum Orbit {Cate channel 4 8 16 Piffuson 1 175 3.75 Poly-silicon to substrate 04 06 06 ‘Metal | to substrate 03 0.33 0.33 ‘Metal 2 to substrate 02 0.17 0.17 ‘Metal 2 to metal 1 04 05 05 ‘Metal 1 to poly silicon 03 03 03 Standard unit of capacitance oC, It is defined as the gate — to — channel capacitance of a MOS transistor having W = L. ie., Standard Square as shown in figure. The unit is denoted by 2Ce, © Cz may be calculated for any MOS process as follows N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 15Basic VLSI Design (20A04606) UNIT-II Gate to channal capacitance For Sum MOS circuits Area/standard squar Sym X Sum Capacitance vane = 4 X 10+ pF/ jum? Thus standard value ocg = 25 wm’ X 4 X 10+ pF/ jum?’ = 0.01 pF For 2um MOS circuits Area/standard square = 21m X 2m = 4 wm? Capacitance value = 8 X 10+ pF/ jun? Thus, standard value oeg = 4 jim? X 8 X 104 pF/ jum? = 0,0032 pF For 1.2m MOS circuits Area/standard square = 1,2) X 1.2m = 1.44 jum? Capacitance value = 16 X 10+ pF/ jun? Thus, standard value og = 1.44 ym? X 16 X 10+ pF/ jum? SOME AREA CAPACITANCE CALCULATIONS The approach will be demonstrated using 4 based geometry. The calculation of capacitance values may now 0023 pF be undertaken by establishing the ratio between the area of interest and the area of standard (feature size square) gate (2A x 2 b. for A-based rules) and multiplying this ratio by the appropriate relative C value from Table. The produet will give the required capacitance in OC, units. Calculate the area relative to that of a standard gate. . 20 x 30 Relati = ———— = elative area = 5 — Sy = 15 1. Consider the area in metal 1 Capacitance to substrate = relative area x relative C value = 15 X 0.075001C, N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 16Basic VLSI Design (20A04606) UNIT-II = 1.1250, That is, the defined area in metal has a capacitance to substrate 1 times that of a feature size square gate area, 2. Consider the same area in poly-silicon, Capacitance to substrate = 15 x 0.10Cg = 150g 3. Consider the same area in n-type diffusion Capacitance to substrate = 15 x 0.2501Cg SCICg Delay Unit (x) It is the time required to charge the capacitor through the resistor by 63% of the difference between initial and final value or discharging the capacitor to 37%. Time constant t=(1Rs (n channel) x OCg) seconds Ifwe increase OV to SV at input, it takes some time to represent the same at output called delay time or time constant. Thus, t is used as the fundamental time unit and all timings in a system can be assessed in relation tot. N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 17Basic VLSI Design (20A04606) UNIT-II For Sum MOS technology T=RsxaC, =10KQx0.01PF = 0.1 nsec For 24m MOS technology T=RsxcCy =20KQ«0.032PF = 0,064 nsec. For 1.2m MOS technology THRSxoCy =20KQx0.023PF = 0,046 nsec. ANALYTIC INVERTER DELAYS pp Vow Pull Up Network Pull Up Network y, 1 L_v,, Vin ———)_ Pull down Network Pull down Network I L —=—GND ——GND Consider the basic nMOS inverter has the channel length 84 and width 2 for pull-up transistor and channel length of 22. and width 2). for pull down transistor. Hence the sheet resistance for pull-up transistor is Ryn ~ 4Rs ~ 40kQ and sheet resistance for pull-down transistor is Rpg = 1Rs = 10kQ. Since (t= RC) depends upon the values of R & C, the delay associates with the inverter depend up on whether it is being tumed on (or) off Now, consider a pair of cascaded inverters as shown in figure, and then the delay over the pair will be constant irrespective of the sense of the logic level transition of the input to the first, N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 18Basic VLSI Design (20A04606) UNIT-II 4, _____ 5, —__ +1 i 7 a nMOS Inverter Pair Delay Note 1: When capacitor is charging, the current will flow to the capacitor to pull up device. Note 2: When capacitor is discharging, current flows to pull down device. Inverter 1(discharging) —_: Time constant r; Inverter 2(charging) + Time constant 12-Rp.oCy Total delay ta= 11+ t2 Consider pull down device is standard NMOS, so it is having sheet resistance Rpa=Rs Rysm4 Ryd Rs oxaCg Total delay te= t+ 2 SR xaCyt4 RyxoCe5 RexaC 5 7 Thus, the inverter pair delay for inverters having 4:1 ration is St. Hence, a single 4:1 inverter exhibits undesirable asymmetric delays, since the delay in turning ON is t ‘And delay in turning OFF is 4t. CMOS inverter pair delay ‘When we consider CMOS inverters, the mules for nMOS inverters are not applicable. But we need to consider the natural (Rs) uneven values for equal size pull up p-transistor and the n-type pull down transistors, (NMOS) Phow Ves N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 19Basic VLSI Design (20A04606) UNIT-II ——_——_ 7+. —____», ae 5t Minimum size CMOS inverter Pair Delay Figure shows the theoretical delay associated with a pair of both n and p transistors lambda based inverters, Here the gate capacitance is double comparable to MOS inverter since the input to a CMOS inverter is connected to both transistor gate. Inverter 1(discharging) _ : Time constant 1)=Rysx20Cy= RaX20Cy Inverter 2(charging) : Time constant t2-Rpsx20Cy= RpX20Cy For Sum technology: ‘We know, NMOS sheet resistance Ri= 0k PMOS sheet resistance R;~ 25kQ Ry=2.5 Ra Total delay ta 11+ 12 = Ryx2aCpt RyX2aCy = Rex2nCgt 2.5ReX20Cy = Rax20Cgt SRXOCe 7 Roly Consider t =RyaCy TTT DRIVING LARGE CAPACITIVE LOADS When signals are propagated from the chip to off chip destinations we can face problems to drive large capacitive loads. Generally off chip capacitances may be several orders higher than on chip oC; values. CL2 108 oC, Where C, denotes off-chip load. The capacitances which of this order must be driven through low resistances, otherwise excessively long delays will occur. Large capacitance is presented at the input, which in tum slows down the rate of change of voltage at input. N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 20Basic VLSI Design (20A04606) UNIT-II Cascaded Inverters with varying widths Inverters to drive large capacitive loads must be present low pull-up and pull down resistance. For MOS circuits low resistance values imply low L:W ratio, Since length L cannot be reduced below the minimum feature size, the channels must be made very wide to reduce resistance value. For example consider inverter with load capacitance is 10000Cy 4:1 1 1000::C, L T4 = Rs jy 1000000 1 44 = Rez 1000aCg = 1000 Consider a inverters with varying widths 1G GND Driving Large Capacitance Loads 100:1 Calculation of delay for first inverter L 1 = Rez 1oncg 1 1 = R,j 100g = 10r N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 24Basic VLSI Design (20A04606) UNIT-II Calculation of delay for second inverter L t= Rep 1000Cg 1 t= Re zg 100aCg = 10 Calculation of delay for third inverter L 1; = R= 10000Cg 1 3 = Reqpg 1000aCg = 10 Total delayrg = 1, +t. + = 10r + 107 + 107 = 307 Super buffers Generally the pull-up and the pull down transistors are not equally capable to drive capacitive loads. This asymmetry is avoided in super buffers. Basically, a super buffer is a symmetric inverting or non inverting driver that can supply (or) remove large currents and is nearly symmetrical in its ability to drive capacitive load, It can switeh large capacitive loads than an inverter. Yoo Your Figure: Inverting type nMOS super buffer * Consider a positive going (0 to 1) trausition at input Vig turns ON the inverter formed by T: and T> * With a sinall delay, the gate of Ts is pulled down to 0 volts. Thus, device Ts is cut off. Since gate of T, is comnected to Va, it is turned ON and the output is pulled down very fast. * For the opposite transition of Vis (I to 0), Vin drops to 0 volts. The gate of transistor Ts is allowed to rise to Von quickly. N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 22Basic VLSI Design (20A04606) UNIT-II © Simultaneously the low Via tums off Ty very fast. This makes Ts to conduct with its gate voltage approximately equal to Vpo. © This gate voltage is twice the average voltage that would appear if the gate was connected to the source as in the conventional nMOS inverter. © Now as laa Vos , doubling the effective Vp. increases the current and there by reduces the delay in charging at the load capacitor of the output, The result is more symmetrical transition. Yoo UA ; ta Mo i Non-Inverting type nMOS super buffer Bi-CMOS drivers * In Bi-CMOS technology we use bipolar transistor drivers as the output stage of inverter and logic gate circuits. * Inbipolar transistors, there is an exponential dependence of the collector (output) current on the base to emitter (input) voltage Vie * Hence, the bipolar transistors can be operated with nmich smaller input voltage swings than MOS transistors and still switch large current * Another consideration in bipolar devices is that the temperature effect on input voltage Vv. © In bipolar transistor, Vye is logarithmically dependent on collector current Ic and also other parameters such as base width, doping level, electron mobility. * Now, the temperature differences across an Ic are not very high. Thus the Vbe values of the bipolar devices spread over the chip remain same and do not differ by more than a few milli volts © The switching performance of a bipolar transistor driving a capacitive load can be analysed to begin with the help of equivalent circuit. N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 23Basic VLSI Design (20A04606) UNIT-II Yoo Driving ability of bipolar transistor Delay 7 Suter Load capacitance C; Delay Estimation a a a a) ‘Cotecor resistance (0) Gate delay as a function of collector resistance N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 24.VLSI Design (20A04606) UNIT-III Scaling of MOS Circuits Design of high density chips in MOS VLSI technology requires + High Packing density of MOSFETs + Small transistor size The scaling down of feature size generally leads to improved performance. Microelectronic technology may be characterized in-terms of several indicators or figure of merit. > Minimum feature size + 4 Number of gates on one chip + Power dissipation ¢ Maximum operational frequency Die size ° Production cost Scaling factors for device parameters Scaling Models: The most commonly used models are: + The constant electric field scaling model © The constant voltage scaling model * Combined voltage and dimension scaling mode! Device scaling modelled in terms of genetic scaling factors: 1/a and 1/B 1/f---> sealing factor for supply voltage Von and gate oxide thickness, 1/a----> linear dimensions both horizontal and vertical dimensions For the constant field model and the constant voltage model, B= « and B=1 respectively are applied. 1. Gate Area (Ag) Gate area Ag=L.'W Where Land W are the length and width of the channel. Both are scaled by 1/a. N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 19VLSI Design (20A04606) UNIT-III Ths Ag is scaled by= zo = a 2. Gate capacitance per unit area (Co) Gate capacitance per unit area CoS Where éox is the permittivity of the gate oxide and D is the gate oxide thickness which is scaled by 1/B. Thus Co is scaled by 3. Gate Capacitance (Cz) Gate Capacitance C=CoL.W Where Cois sealed by B, Length and width are scaled by 1a a B Thus Cy is sealed by= 4. Parasitic Capacitance Cx Parasitic capacitance Cx is proportional to Avid Where d is the depletion width around source or drain which is scaled by 1/ a, Ax is the area of the depletion region around source and drain which is scaled by 1/a? Thus Cx is sealed by= Th = : 5. Carrier Density in channel Qon QeaCaVen Where Qu is the average charge per unit area in the channel in the ‘ON’ state, Note that Co is scaled by and Vesis scaled by L/B. phat 6. Channel Resistance Ron Thus Qea is scaled by: La W Qontt Where j1 is the carrier mobility in the channel and is assumed constant. Thus Rom is sealed bya =1 Roy 7. Gate delay ts Gate Delay te-ReaCs Where Ron is scaled by 1 Ceis scaled by= & Thus tais scaled by= 1.4 = 4 8 Maximum operating frequency fo fo is inversely proportional to delay ts N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 20VLSI Design (20A04606) UNIT-III Thus fo is scaled by mh = £ 9, Saturation Current Idss ConW fase = ET eB) Where Cois scaled by B Land W are scaled by 1/a. Vp» and Vi are scaled by 1/ B 2 as is sealed by B. @) = 10, Current Density (J) Tas is scaled bys Ais scaled by Thus scaled by = £ == =F LL. Switching energy per gate Eg Where C; is scaled by = 4 Vaais scaled bee Bai. oP ee 12, Power dissipation per gate Pg Thus Egis scaled by = Pg comprises two components such that Py = Pgs + Poa Yop! Ron Where the static component Py, = Dynamic componentPyq = Eyfo It will be seen that both P,, and Ppa are scaled by 1/B* Thus Ps is scaled by= > 13, Power dissipation per unit area Ps 1 Rl _@ 4g Ug Fy N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 24VLSI Design (20A04606) UNIT-III So Pris scaled by = z 14. Power Speed Product Pr PT-Pe. ts ; Bak So PT is sealed by 4.35 = 5 Two Marks Questions: 1. Draw different MOS layers with color codes. 2. Design a stick diagram form NMOS inverter, What are the importances of CMOS design rules? What are the uses of stick diagram? ak we ‘What are the limitations of scaling? Ten Marks Questions Discuss and compare the CMOS design style and nMOS design style. Design a stick and layout diagram for CMOS inverter and two input NMOS NAND gate. Explain about various contact cuts that are used for CMOS transistor design and fabrication. Draw a stick diagram and layout for two input NMOS NAND and NOR gates. Mlustrate the lambda-based design rules with neat sketches Design layout diagram for the CMOS logic fimetion What is the difference between ‘a’ and *f” scaling factors? Give some examples. Briefly discuss about scaling of MOS circuits and its limitations. Draw a stick diagram and layout for two input NMOS XOR and EXNOR gates. 10. Draw a stick diagram and layout for two input CMOS XOR and EXNOR gates, CPR AwRYWHE N GUNASEKHAR REDDY, Assistant Professor, SVEC, Tirupathi Page 22