Chapter 1: Revision

Required equipment
• OrCAD 10.S
• Waveforms Software (Oigilent)
• Analog Discovery (Dlgilent)
• 1 x 1 k.O Resistor
• 1 x luPCapacltor
• l x 74HC04 NOT Gate
• Breadboard
• Wires

PUIJ)ose of the Chapter

l . Revision of analog ,imulations
2. Learn how to simulate digital clrc:uiu
3. Familiarize yourself with using Analog Discovery Board together with
Waveforms Software in order to implement analog and digital designs
4. Highlight the differences between analog and digital waveforms in
OrCAD PS Pl CE and in Ware Forms

Theoretical back~ound
We live in an analog world. Whether we are talking about simple physical
phenomena such as a temperature variation, or the m01t complex wondexs
happening inside a super massive black hole, every physical phenomenon can
be observed by acquiring one or more analog signals. An analog or analogue
signal ls any continuous signal for which the time vaxying feature (variable) of
the signal is a representation of some other time varying quantity, i.e.,
analogous to anothl"r time varying signal. For ex.ample, in an analog audio
signal, the instantaneous voltage of the signal vanes continuously with the
pressure of the sound waves.

However, if one would like to nc:quirc, store or pt"OC%SS these ana\{)g s\gnah
using a computational sy&tem, they need to be converted into digital 51gn.a\r;
A digital signal is a signal that represents n sequence of discrete valuts. A 1
signal is a ,d igital &ignal with only two pomble value: and ~•·\!'~l~, an
arbitrary bit stream. As you already know, this convemon \a cbne u
analog to digital converter (ADC).

7
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read In that
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Ffsurt J 8. Osri/IIJS(Opt U'a1efanns(CJ Vclt'r.~11,011 Caparitor, C2° Rtrtar\_~1la1

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-
input i'cltQ&r)
r1,g1u r,JO Tfomltnt simulat1
ComJUll! the rf'sults obtained by simuJatio11 with those obtaint'd in lhe
p.racltical impltmenution. 1'c force the oulp\\t t1f \he lhg ta\ dradl ta an,
at t h<',,11tpul (lfNOl'Gataand \-l,uaU c lhe,o1t

12 l
 AOl
. __ ,~ with NOT Ga/8 and 1 nF output capaci~or
00

--
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Ob
bo

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t,00--0 0 0 O 0 Q G O O 30\ I, a \

.._ .__.....1.....A ILCLU J'..sL!i.L.,lc.....1_ _

:1 I

- ·- ·- ,-.
Figure 1.13. Schematic - NOT Gate ci~cuit on :QreadboaTd and connection with
A nalog Discovery device
Figure .12. rransient simulation resultsJor circuit in Figure 1.1 0 . ..... . ,_ •.:5.-,,. -·,...!__.~,. ,,,_ "'' n ·• ~--: -.....
~
1
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•
• ' - .

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Practical Implementation I I I I ' •

-I I - - I
\
\
In order to view the digital waveforms, implement the circuit in Figure 1_9
the Breadboard based on the sketch below. Use the Analog Discovery Kit · on \
\ \
'I
\ I
l I \
Digi.lent waveFonns Software. Generate a rectangular w aveform u stn
WaveGen and visualize the desired digital waveforms using the Logic Anal g
from the Digital Menu. Results are presented in Figure 1.1 4.
~d

Yzer
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-~ ..... I
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Figure 1.14. Logic Analyzer - Digital Waveforms (IN - Rectangular input voltage,
OUT - Output of NOT Gate)

14 15
 t h opti:r 2: Sbo:rt CircuitDefecuin J.oglcal
Circuits

Bt 9nire4eauimnent
OrC,\r,,i:,, (
)'111\:tf«f'l'd:Sl)ft.W1,:e(D.lfil1tt1tl
Anllh>t:~er,:,(Ctlib-tn ~

~:1-l
l X 1-lta RcmlM
l. X µa ~jdl\,01
I ¥711,HpOO,NAHDG:a~
1 xT_,M~Oo\ t<-OT Ga\oe

~lJliL 1.Btil-,t,l)l)c)ard
WI""
-- ... ... ·- ... Pumose of the Chapter
l., Let\1'1hoy.,cijff.c,:;eni s ~ c i r w \ t ~ ~ ~ b t b a ~ ~ ~-
u.hd hOW\,e,ti(S~ ~h -~tt"-
'2., Slmulite IMl &Mlyze: bOth -ffl ,Os-CAn and· pnc:lk:itlly, v.ltnt; 11.
Breadlioud or,d;Analog· Duco,;cry)$q,il'ro,. t.hi!''aittut,v\ot of ,ucrl,dtd.llt
w e~ .
Theoretical backifound
Shon: dm.iit. type de{ec:1.5, appear Whett'i/'et. th.cff. \s an v.ll¢.e,.lud p~i\(a,\
0

connection bct.wecntwotlgnlll Urief.. Tbctt. bl' l)Q- fowlt\ riib.e:t'att.'nt pri"nwd

clTd.l.ll bo~SfC-8) 14!:vt,l (u HCn in TI~ 1. l}i ~ at• ch\p le.yet.

iJ

ll
 ('CB tevel. they can have var1ou
~u ~ present at • rc,au of manufacturina the Pc• '
Whl!fl d)dl'
....onJlf wh c •
t~ he-comp0ntn
!.
the> U!Chnotosfcal The# short circuit, can •PJ>ear U:;
-i...__.
t':' and Q2 ta utunt~ Convene. , Uthe output h «11:rur.a
..... { Jdt'J1nl I . ""q • 1• • vcty t-.lgh value curnnt •PPf!&f1 wtoch uawli rrom VCC \,l-.?1~~
proera 0
l/0 ·eioftraclc&,
DI u,warcb OND. ~ potcntW dirr~ bc-nacn u t
muldp~ catePI r Unts (VCC and GND) dlridN! on the thr~ tk:?mnU mentlone-d btf U th., comm.a ,...,......, m
n thepowe
\ha baR of Qt Cut lu nturlltlon b • ITMtl VAM tt-.h ,.,m axM CNl QC
ShortdrcuitbdWU . vcc) is dlrectlY shorted to the referenc:e
,upply lint' C cc.s.•fve rise In the current cons\lrn Of Ui.t uturaticm (condition 1111 > le b no \onp:r rwfilliro) enthhan.m wffl 41& u
6
Wh~ ',~~~SS) it leads to an e~As a result, the testing equipmttnt ~ Of a much grutn powa than ln normal optRtkm Md on l°M ~ o1 l\ lN
dr1:1Jlt w•v ...er source. li . ti' d ••1!6.4. power dlmpaad on Qt can bl! 11,tall OI \arl('.r Ofll. l b 1mall, lhe pG1itlet "1Ul bf!
drcult (rom the po:~ with current nuta on an n~s t -'""ll to (lTl:atU) Alo mull, this defect wtU be ecaimpanltd by a rlH ln U'flq)C:t-.1-UNt
the .rn--~• of supplying ~welirmJtation is active. Thestt type, of d~f o haa"t ofthccomponent'spac\agln,:ifthccommll!ld ln•a• 11 ma\nta\n for a k)
halll! r..,_ • b n thiS . 'Ct.;
me-ms of signalin8 ": e r be discussed in the followmg, becaU$e the cir llt11 period of time. Moreowr, Uthe curnnt drawn from the pawn aupp1y b
not sill'lulated and "?11 n~ nd operational until they have bt!en elimlniu~I& monltort'd, • J4tn\llc.ant the ln lt1 vahic an \lt o~rwd
1.-n,rnt functlOnl a •
donDl~
;gnaI line ernd one of the power lines (\f Tittl SA 1 t)'PI! dclect h attomp.i ,1icd by th, fo\\ow\n el«tr\eal ~hav\of If W
short circuit betWeen as Cc output of U l Ab commanded to outp11t \oa\Cal value• 1• thn 1ho.n drcu\t docs
not have an Impact on the clrcult {uannittorQ2. b b\oc\crd and Q\ ls utur,~)
orGND) . dtis t:
of defect falls either into the catego On the other hand, when thn output II commanded ln "O" • \atp cuJTent
.From a logical standf01:t cate::r of SAl (stuck-at-I). From an elec~ or appears throut:h tran1\1tur Q2. Thls has lta co\\cctor tcrm\na\ tied to the
SAO (~ck.ar_.o) or ;:;. d ~ has particularities "'.hich have con~equencesclaJ. volulgc of the VCC power \Inc 11n!1 lt1 cm\ttcc to thl! potcnt.W of the GND, !And
standpoint thi:5
typeth . cuit and as a result, dunng test execution. n there Core docs not hnve the poulb\llty to nt11ratc. The current bclns \nlccud
in its base hu a large vnlue In ordet to 11tur11tc the tran1lstor under norm11\
the functionality of e ctr '
thwhere all circuits are implemented using bipo( operation condition,. This will lead to a co\kctM cun mt le • Ill, of a very h\nh
First,_ we analyze ~:eofan output pin is presented in Figure 2.2, the twar value (much Larger than the curnnt uavelling through Q.1 \n the prmow
case). ln addition to this. the power dlHip.atcd by transi,tor Q1 wU\ a\so
tranSJ~rs. The 5°:1 SAO fault (left) and a SAl fault (right). o
scenanos represl?Iltmg a become much larger. P • Vee le. As a result, Ir the commllnd to •o• peni,u there
... U2A UlA U2A
is a risk of thermal destruction of the component in which Q2 is found. t{ the
current drawn from the power ,ou.rce \s monitoced, a nsc in its value that
signals the presence of this type of defect can easily be observed.

we now repeat the analyru for the case of CMOS trans\stors (figure '2..1).
Ol
CD S41

UlA
"' U2A UlA
.. \J2A.

.. ...,
-
CD
#I
'"
"' "' ... "' • °'
'IAO
-\ \- -\ \-

Figure 2.2. SAO and SAJ type defects/or bipolar circuits ... .\-
\-
In the first case, the SAO type defect is accompanied by the following electrical
behavior. If the output of UlA is commanded to output logical value "O'' the
short circuit does not have an impact on the circuit (transistor Ql is blocked Figure 2 .3. SAO and SA1 type defects for CMOS circuits

19
18
 a conflict appears between the
chat i.rl this~~~ short circuit• In the situation "'cornll'ttti
Jtcllll be noted ut and the eXJ d bete is a short circuit to GND a ~ e Q.1 cl
gi,,enco weoutJ' in u1Aat1 t t w ac is limited just by th.e l!tlt,_, it Jfboth circuits are built using CMOS technology (Figure 2 .•5) then, when a shon
comznanded tothi~BJlsistor, ~ c i o n also arises if Q2 is co Cond~ ill circuit type defect is present, two diagonally opposite transistor& are open, for
f!oW r.br0°1 th£' traJlSis!or;:to vcc. The transistors have~ d ~ : example Ql from U lA and Q4 from U2A. AJs. a result, 'between VCC and GND
two drain-source resistances are inserted of approximately equal value. This
resistallce tbete is a ,short en open. As a result, they Will ~~hie
open and resistances wh are dependent on the value of thdia'i1>a•• way, in the node the voltage will be O.SV«. Thili voltage represents an
drain-source These pawers e &q "" intermediary value, and as a result the gates commanded by this node will
_A...,,hle ntm•er. 1>p1}, have U11J>redictable values. Due to this fact for detectingthese types of defects,
COIJll""' - r-- .!b-. indirect testing techniques, such as monitoring the current drawn from the
voJrllge vce: P - 11os. . . •
ction of these arcutts the test operatl power souri.e, are recommended.
rder co P ~ t dte de~ese circuits will be powered at higher vonl s are
~qecured at -vcc. = .sv,.,:.-;ons
Jn o even o t~
,
"""' • COD""~ •
under operatil18
,,..,.,.1 lines
• ·t bet..veen two si~,- .,
Slwrl arCUl signal lines can also arise due to a faulty tit . -I
A short curuit 1,e~eei;:;;010gies. In the foll_owing, both bipolar and ~ot
faulty manufacturll1g orn the standpoint ofthis type of defect Os
circUics are analyzed fr

If the tw~ i?cerc:onnect

co~is JS
ga te rece1.vmg •the that
a:
ed res are in bipolar technology (Figure 2.4)
for a. logical "O" will impose this level in
.,,,~.. UlAI then transistor Q2 from this gate•
. e,-,.._
th
the;1
the
t\lio
nodes. Supposing ..ed with a collector current of several rnilli lS
ded co be satura•, ed be atnPs,. Figure 2 .S. Short circuit type defec.t for CMOS circuits
comm.an . ..+n U2A is also command to saturated but Only b
-nsistor Q3 from g,u~ • th b th Ya
,,.. -'--' . ~"'""PS collector c:uaent. Given at o transistor Lf the circuit that is affected by a short circuit between two signal lines is a
s
everaJ bunw= nucr..,..,., fir
current jt results that the st to come out of conductj
s are
purely combinational one, i t can be transformed into a sequential one in the
~osset; bytthUe2AsamAse a result Q2 from UlA will impose a logical uo» level in then presence of the short circuit. As it can be observed in the short circuit between
JS Q3 o, ga e • , e
the output of the circuit to one of its inputs will determine the circuit to have
node.
... a sequential behavior, the states of the output will depend on its previous
states. For identifying these types of defects and adequate test method needs
UIA
.
,
U 2A
to be adopted which does not involve using a succession of test :ngnals.

. u, SC

er U3

Figure 2.6. Short drcuit transforming a combinational circuit into a sequentia.l

one
Figure 2.4. Shon circuit type def eafor bipolar drcuits

21
20
 short orcult appears between two
tel circuit tbeodd um~r of invecsiom, the c· Pot11q
If itJ the:::;: cnne is a11. u:'ough the gates in the loop Is ~C:Ult Ill!~'
i,e<Wi!t'll Ifthe p~atiDD ~~~h Frequency which can cause tn~1 l!r.a.~
osci!We. will ha~ a ,_. ef'lltt.-:'Cll,
r
•'-••e osd-1.lsdOJ'IS -«ec:ted n~s.
u- 1ntbe~·
~It
r r
logi~~ I
cas.eStu~5 \
I'
•
-
Cast
-: adt baween a signal path and the
studY J: short "'r
1y1ground . .
Poitq"e
.
\j \
power SUPP . otCAD the circuit m Figure 2. 7 that lllOd \ I
SinUJ!zte and anal~ '" . t,etween a signal path and ground. I? 1 ela the
presence of a sbo~ci;i~f the (ligital circuit in an~og mode to vtrid ~
rzsjstors force the f;he
gate. Rl is very small, l!l, Lil order to aio,C\lf tht
volt.age at the outpt.ttdo nd R2 is 1k!l which simulates, in this cas<-' u~½, I
. -·:. to aroun , a V an 0p~
short CJI'<=• ,,.. • is applied at the input. o1tage marker, arc Pl
~A~ulse:;.° put voltage VJ and the voltage at the output~df11
the cf.rcUJt to view! C:ate
a tran5ient simulation and visualize at or 1he
l 1 •
I

I"~t 1
gate sunulta.neou.s Y· l
\ \
periods-

11:A
-
lr " R2
-].,,
·-
5Vd: • _
l I \ \
l
\
\
I ,.-

,,, .,,
,., • Cf
{

'~
-U·' 7,.,,coo
J
I'.,
Pl
r Figure 2.8. Translent simulation re.su!u Jor cirC11.it In Figure 2. 7
The output liignal 1hould be an inverted version of the input signal, but \t ls
ro•t
r,,a1~ t1
r, ■ c,-
,.N •t,J.
1£,"I . 1:..-
0J
L
0
I'·o l 0
not, because the volta.ge level& of the output signal ate conmtr:nt with a
constant logical "O" value, th~efore this ia a rtuck-at-0 fault.

Modify the circuit in Figure 2.7 in orde-c to i;imulate a short circuit between a
signal path and the positive power supply. In this case, R2 \s cho&en to have a
very small value, 10. Run the simulation ag~n, analyu the tesulu and
compare them with those obtained previously.
figure 2.7. Circuit tlutt models a short circuit between a.signal path and ground

23
22
 R2 ,ractlcal I m plem entation
' implement the prt'vlous two circuits from rtgure 2.7 and ngurr 2.9 on a
Breadboard based on the schematics below. Use the Aiulog Discovery £\o:ud
and Digilenl Waveforms to generate the Input rectangular ~i,nal and the 5V
power supply and visualitt lhe waveforms on the OsclUo1eo~. Compare the
resulu obtained by simulation with those obtained In the practical
0
implementation.

A8C01i IOH I J 1
IDOOOil 000D0\
s a short cirruit bttween a signal path 0 0
, "t t}urt model
!
and •L _ AOVCC 00000
figUre 2.9. c,rc.w H-~ffl~P"l'!l"t'I'--~

,~
positivt power supply .,ie 0 0 0 Q Q
000 ~ 0
0 0 0~

ADOSCl . . .-+-!
00 00
••ouc 1000D
AD OSCl ♦---Ii+-.--...~ r ") D 0 0 0
0 0
~b 100
0
go5 t 1 0 ti 0 0 10 b o
0 0 0 , 0 .. 0 0 0 0 o
0 o 11 o h 0 000 Q 0 '
000
ADGND•-W..• o o 0 o 0 0
00
•-++ffl!P"l!l"'l!l"l!I'..- - " 0 D -0 15
00
00000
0 0 00000 00000
00
'
0 Q
0· 0 0 0 0 00000
b ti
:l
0?
0 0 0 0 0
200 0 0 0 0
0 0 0 0 0
0 0 0 0 020
00000
I

\\
0 0 0 0 0
0 ? 0 0 0 0 0 00000
t '
~i 00000
0 - 0-0- 0 - 0
'
00000
0 - 0 - 000

D
I
~
250 0 0 0 0
00000
I 000G02&
0 DD D 0
b~
.__ 0 0
I D D-G- D-0 0 D 0-0- 0 11 1i Q
' 90
-
DD 0 0 0 0 0 0 0 0 0 0
•
~❖
00
0-0 0 0 0 00000
0 0 DOD 30 \ t D
300-0000
Al\_C,DE l FGHI J

Figure 2.11. Schematic - Short circuit between a signal path and grottrid (Stuck-at
- O) on Breadboard and connection with Analog Discovery device
•

Figure 2.10. Tra(ISient simulation result.s for circuit in Figure 2 .9

What are the differences between a stuck-at-0fault and a stuck-at-1 fault?

25
24
 ...

.. .... •·~
Figure 2.14. Transient simulation results for circuit in Figure 2.13 .

. Short circuit between signal paths Simulate and analyze in OrCAD the circuit in Figure 2.15 that models the
case StUdY 2• . . · u1 · presence of a short circuit between two signa\ paths. Source Vl applies a
2 14 the circWt and SlID anon results obt . rectangular signal at the input of gate UlA. For source V2 choose a DC source
In figure 2.13 and ~eui~ between the two sLgllal paths are present:.ed bi and apply voltages suitable for the two logical levels, 0 and 1. Place voltage
the absence of a short ore markers in order to visualize the signals from the shorte.d node and from the
outputofthetwogatesUlB and UlC.

Compare the results obtainedfor the two cases:

1. Short circuit defect missing

2. Short circuit defect is present

UV,

v,
V2•5V
•fN '1!1C04
TO•0
TR• 0. 1n
TF • 0.1n
PW• &In
PER• ,om -=0
u1x:o)ll-_ _ __.._ __ ..-J"-- :5.1c ~

Figure 2.13. Two signal paths in the absence of short drcuit defect
9
41-1(:04
...
41-1~
,:

Figure 2.15. Short circuit model between two signal paths

27
26
 ~
••

.;
I
I
I
I
I ••
••
••
••
••:t
I •
.... .... ...
, .... AOOICU
:1
..~·... . .. ,,,.....
I
·- All Dill I
All lll\11
AOQND~~r.6o:-"tT:!°!1,li
0~

-+t-....#-<ini..J. 0 " CIOOOO

O ooouo 001110-0
1
1 uoaou 00001.J
DO l<IU O D O D nooeto DO
ft D !"' uoaao GIJOOD
; ooaao
DQ'OOO
o u no a
bOOOII
0
1i
~,
"'"'""
tttooooa
00000
QOOOO
t:1000.;1~•
oooon
1? 0 uoo~o aooqn
OO QOODSI OOOQQ
qc, 00000 00000
O O :M)O O Oa ID a o a o u,a O Cl
All<;Pr f Q H I J

. ... .... ...

,
- ,. Figure 2.17. Schematic- Short circuit defect missing- implementation on
Breadboard and connection with Analog Discovery device
. T.ra"dtnt simulation results/or circuit in Figure 2 . 15
F,gure•216
. • •-·
As it can be seen from the above fi~es, defe~ occurs When the output of the
·
~,....
·- ~J
S-.
, r
~_-.."ii11, Vlf
~
I\•
• I
W •

1---l===------l__la--!,__--L....lo,,-.....l.--!...~.....-
d u D are set to different logical states. The effect gene
cwoga tes, UlA an · 1 , h rated
by the defect is the presence of an unknown state. Note ow the OrCAO PROB£
Window signals an unknown (X) state. {l1============....===r- - -\-====t
+
=
Practical ImpJement.ation Figure 2.18. Logic Analyzer Digital Waveforms

Implement the previous two circuits from Figure 2. 13. and Figure 2.15. on 8
Breadboard based on the schematics below. U ·• the Analog Discovery Board
and Digilent Waveforms to generate the input rectangular signal and the 5V
power supply and visualize the digital wavefon n s using the Logic Analyzer.
Compare the results obtained by simulation with those obtained in the
practical implementation.
1. Short circuit defect missing - rn th.ls case the circ-ult is worlclng
properly.
2. Short citcuit defect is present - Test this situation using Oscilloscope
and see on channel 1 the voltage at the short circuit node and on
channel 2 the input rectangular voltage. The effect of the short circuit
can be observed, the maximum value of the voltage at the shorted nod.P.
is 2.SV.
Note!
The Logic Analyier does not recognize intermediate stat eli tx u.-.kn.owr.
state). Test this situation by generating, using WaveGen, OC volta.ge, hlth
values starting from OV up to SV with a step of 0.5V . See, for each val~ the
corresponding logic level in the Logic Analyzer.

28 29
 a.o,,,P=========================

•.••
-1---- o.,..
....-- --.-___JL_~--
•.•• -----~---~
I •••
--
j I ,,.t__i....,.,,_....._..J •V iV h•I • Vt0'1A1lt • V 1t1 • • •1'1
I i 1 ..,...;...i.-•• ., _ •• •-
-...,_
" I
·-- j I .... ~ - ·-

. . wavefomis (CJ - Voltage at the shorted node C

-----
i:1======:::-
:__,_
- ,..
= _:--:;
.,..:_--::
,.. -- ~=--=~--_ - _-:;:--::_::--:_-::::,-=_ ---:•
::--:c:::-
"'U'."'.' 1-------...........,. - - - ~ • :;.~:;;.,-::.-::
~ ~~=
d ·..;-....
_,._-,:;.
_,;;-::;_;;;:;:,-=,
:,--

Figure2.I9, oscilloscolipe Ml -Mathematic Channel to simulate sv 2 · l~Pllt

rectangular va t/lge, C)
D
·c ChanDel, enter the Control menu in the scope . ,.,,.~ ========================
To add a Mathemadt:i.,ffthematic Channel-> Custom . Witl<il)\y
and then select Ad ,.,..
... Introducing a reaction by the presence of a ..i.
case StudlY ~. ..,,on
circuit
.n, in OICAD the occurrence of oscillations in the .
Simulate and an al; - th . th
at m e teste CU'cuit the h
arions annPat due to the faet
d . CltC\lit ··J.._- -,------11-----.- ---.-- - - -,-------.-----
0-HH. . L O~O!c~ ~~oooi....
!,elow. Osdll betw rr-hich th . .
S . Ort e v t v1~ ~1 • li(0 2t.-;a) • "?tUU:.Yl
circuit is present between two pomts een w er.e is an odd nurnbfr
of inversions.
~,,.......
Figure 2.26. Transient simulation results for circuit in Figure 2.
.. Practical Implementation
I Implement the previous circuit from Figure 2. on the 'Breadboard basedon the

,~·-
l '"°'
-I ~

'-
1
.,,..
.,:.
't.lOf

--... ,11
l,Q&
1.__,
schematic below. Use the Analog Discove.r y Board and Digilent Waveforms to
generate the input rectangular signaland the power supply of SV and visualize
the waveforms using Oscilloscope.. Compare the results obtained by
simulation with those obtained in the practical implementation.

~=t
I.:
"1 r1:t
,., .
r
~
J
~ "-· '7-

. ... ... ...

T:r • O !':) • •
!'l•• ,."
V tf • tl

""'.,. "P• •
0 e

Fi.gure 2.2J. ApFaro.nct ofoscillador.s due to short drcuits

31
30
 ' r _ _ ,-

1
'
. I~==
.-.
,.

•
8
o - 0-0
~-. ·r, r 77'.I
000001
HI ,
DO
0..0.000
oo
a "

1If
09
AO vc, · ~;.;.n-""ll't
.!!. o-
O " 0
o O OJ DO Chapter 3: Indirect Testing Methods
n
~
ooao
...0
, O O O 0
0 D-0

a-- 0-0 i:x:

AO OSO •'i' 0 0 0 0 10
Do
Reguixed equipment
_ ...1,...,..,+1,1~
o:rr::J~~i~==~
~. . .
~ooo
00
• OrCAD 10.5
~oo:.r- /j!•"."..' o O O O 0
a oPO
-o
o...c,-o i,
!!
00
• waveForms Software (DlgUent)
$ 0 D 0-0 DD • Analog Discovery (Digilent)
• oooo 'i' a • N1 Lab VIEW 20 IS
oo '.l,C,000 DD
oa I I l x 7 4 HC04 NOT Gate
fH>-0--0 D
•
AOGND •
o,
-Hf:0'-U~o-c>-~:o:!
-0~
~,-o
DOODO
o -o-om
0-,.000-0
1; •
•
Breadboard
Wires
0 , a--,ao-0- 0-0
0-0---0 o a "'X
oO 0--oOOO
0-0 0-0-0
o o o a ats T1
a o
250 a o o o
0--0-0-0 ° o,-0--0 0-0
xi Purpose of the Chapter
0--0- 0-0--0
0 0 o,-a-0--0--0
00000
' '
I' a 1. Study i'1direct monitoring and testing teehniques used for devices
ao 0000-0
O O
G O
O O
D(tO-C O Q.--0
o-o 0
C>-OODO
o--a o a 030 ii under operaton
F G ti I
II 0£ i. Learn the IDDQ test method
3. Understand monitoring methods based on device temperature
_._,...,.....-,-An,pearance ofosdllations due to short circii" changes
'"''re
F.. ~
2.27: 5..,"',,,,,...
B adboard r, ·
and connection ·hA
wit · 1ts •.
nalog Discover"-'~
imple,nentation on re ·J -vice
,._,.,__....,.... ,as.. 'JI• ,.. Theoretical background
The IDDQ testing technique can only be applied to CMOS circuits. The
structure of such a gate consists of n-MOS transistors connected_ to the
reference of power supply (Vss) and p-MOS transistors connected to the
positive power supple (V DD). When there are no defects present in the circuit
only one of these two categories of transistors is in conduction (open). ln this
way a high impedance path is always present between V DD and V ss, due to
which no current travels between the two supply lines. In reality howeve-r, the
only currents that do cross this path a-re the leakage currents through the
junctions of the transistors (these being reverse biased). The maximum value
of this current in the case ofa NAND CMOS gate has the order of nanoamps and
therefore a current of such a low value can be neglected..

The presence ofa short-circuit type defect inside the structure of the transistor
will determine a permanent saturation (open) state of either the n -MOS or p-
MOS transistor. When the complementary transistor is commanded to open a
large current will appear between the t wo powex lines. The value of th\s
Figure 2.28. Oscilloscope Waveforms (Cl •Voltage at the output ofgate U3B, C2. current can have the order of milliamps for a single defie ct. The output of the
Input rectangular voltage at gate U3 B) circuit in this case will have an unknown (intermediate) logical sta~lf d ~
testing or exploitation the current drawn from the power source i£ monitot'"\l,

33
32
 Chapter 4 : Erroneous logical pulses

ReaujrPd equipment
• OrCAD 10.5
• WaveFom\5 (Olgilent)
• Analog Discovery (Dlgilent)
• 1 x 74HC73 Jl<fllp-nop
• l .x 74HC00 NAND gate
• 1 x74HC08ANOgate
• Brendboard
• Wires

Purpose ofthe Chapter

l. Study the behavior of different defecu whic:h cause the apperance of
erroneous logical pulses.
2. Simulation of circults that illustrate the fo\low'ing lype of defects:
dlsappeara nee of functional short Impulses, the occurence of parasitic
short pulses (glitches, spikes), change of temporal parameters o{ the
pulse (pulse delay, pulse duration change).
3. Determining of causes that generate these types of defects.

Theoretical background
Defects which cause erronous logical pulses are considered the following
categories of defects:

• The disappearance of short functional logical pulses

• The aparition of short parasitic pulses, called, sldpes and glitches
• Modifications to the temporal parameters of the pulses (delaying the
pulse or m odifying its duration).

These defects h ave the following characteristics: they apearfor shorter periods
of time than the functional signals or test vectors are applied. As a u.sult, for
identifying their presence, the test equipment needs to be capable t o detect
pulses with widths shorter than that of the applied test vectors.

These type of defects can have various causes, amongst which erronous design
of the circuit, different timings of signals in the circul. . and using fast ligna.ls
with slow circuits. All these causes are exemplified during the Cue St.udi.es.

49
 - cttJ~ o,fparasitic short pulses
~ . ccurrence . . .

~~°llt '
stJlllYl• 0 . QtCAD the cirCUlt m F~gure 4.1. ""hi -practical lmplenantation
CfJSI and an.Jyzt _111e,irCuit is an example of erroneO\ts lo c~ t'Pt, unplement the previoua circuit from 1'1gu~ 4.1 . on the llreadboud bued on
siJPulare U)1ter- 'fhiS . tunction,_thetwooutputsrnust; theschematicbelow.UsetheAnalogOisc:ovuy'Boardll.l'l<iDl&il,entWavtfonns
J110d111° 3 co (hedegredlog.ic an be observed in signals <Ua gothtl>\i ~1 ro generate r.i&nal for the clock 11.nd the power supp\y of !.V (H\GH tenn\na\)
,.ceordill.B co
10 and o •
1 131.1t asstates,
c h • irall\ ft,._lb~
for a very s ort ti1tte, a fo :·"Ill ,"it and visuallu! the waveforms uslna l.ogic _t\nalyiu. Compare th'!! ruu\u
st,1¢= OO, end of the~ _.:--' to reset the two flip-flo l.irthii_ti...."' obtained by simulation with those obtained in the practical implementation
2 at the rt time 1s req,...,.~- . . t. Ps. 'l'h ~~I
4.. fbatsho . ciesoftheorcw eaerl•.11,
appears. design defioen "<I~
occurdue to :'!-..!..?"-, 4 Tc o..,u
,-,.- ~'cfi1T J
10D-D00 000001
AOVCC 00000
0 0
00
00
00
0 0
I I
ADO AOl
0
i tOD ADl
0

r-"----'~ U2A
ADGND ◄t--++49 a l oo
00 150 0 9
74HCOO 00 00
OQ 0 0

'r"'
I
oy 000
q 0

1I "ff"-iiiiiiiri«
0 0 020
0 0 0
0 0
00
0 0
0 0 0 0 0 00000
0 0-0 0 O 0 0
0-0-0-0-0
. •tfior observing the occu"ence ofe"oneous lo<ricalp ,_ 00000
0 Q
Figure 4.1. C'"UI
00000
o• Ui,es I
250000-0 0 0 0 0 025
0-0-0 - 0-0 00000 '?' q
0 0
0-0--0 0 0 00-000
0-0000 0--0 0 0 0 q ~
0 -0-0 -0--0 0--0-0 0 0 0 9
0 0
-300 0 0 0 - 0 0-0-0-o-tl 30
SCOE .._LG li_l J

Figure 4.3. Schematic - Circuit illustrating the occurrence of erroneous logical

pulses on Breadboard and connection with Analog Discovr.ry devite

" .. ... ... ... ...

Figure 4.2. Transient simulation results for circuit in Figure 4.1.

51
50
 II>
1• It r:-===----:-=-=-=--_-:_
,,.. - ~ - -
____,___
: :------ -------....- -
_.. ..._ _.-.. -

...
L__.-:1--_!.:·.-•
ffSVJt4.4,l,oi1'
-=:== ... ,.. ,.. ...
--..!,:__
. Analyur D{gitol Waveformsforcircu.it in Fi --.... '·
'gUre 'I.J
..... '... .
. O~cUrrence of erroneous logical PUlses
2
case study · . parameters ofthe control stgncas ~"
differentdynm1uc . . . .
in OlCAD the orcu:tt 111 Figure 4.5. that ill
simulate and anal~ logical pulses. The two inp uts of : ~ •• ....;==;\:====r=
. = = = = =-=
-~=
occurrena. of err, ·te phase. The sources VI and V2 apply two . ~ ~
~ ~ e ~ : n g edges because in reality any rectagutn : : :.;~'
(l11.Rk'-"-. .t'<l,.

,\
irapez.oi~furm. •

c·, . . .
t .. l.a...t :.i.-s ! .. k s
• vrn:a~ ,., .., .,,n a. s ■ » , 'l'tS'U1,1.1

Figure 4.6. Transient simulation results for circuit i11 F~e 4.5.

Practical Implementation

Figure 4.5. Circuitforvie-iltfingthe u:au,e, ice oferroneous .ogical pulsts
Implement the previou£ circurt from Figure 4.5. on the Breadboard based on
the schematics below. Use the Analog Discovery Board and Digiient
tflaveForms to generate signals for the two input sources and the power
supply of 5V and visualize the waveforms using Oscilloscope. Compaxe me
"esults obtained by simulation with those obtained in the p:actical
implementation.

53
52
 -
100 000
Ci
- ,_ 0- C

ooa
O C:
001
aaa
F H I J

0 -a-,aao
00
o~
! 00000 00

..Ji,µ,!-!
oaaao
" 01'1~~~"':"":--~~000
,n
•• --··----
,, ,.. I!;
- ·-·-
l •·.. ·-
- - - 1111, ,, •
soaooo 0 0005
~ ••
AO '" ' .,; ;; 0 P g O g
...
0 0
0 0
0
..
;;t 0 G-o 0
..,,
oo
oO
DD

oo~oo
:,0000
;;) 0 0 0 OfO
"lD"Oaa
;;, 0 - 0 0 0
;> 0 0 0 o
.,
•• I
u J LI I

oa
ao
150-~-0 o- o
00000
0 - 0-0 0
PO 0 0 o
0 15 ..
ao
0000--0
ooooo 00000
.,
0 0 0-0-0-0-0 0-0-0- 0 - 0
o- a o o-o 0 0 0 0 0
0
O 0
oo
o 200 o o o o
0--0-0-0- 0
ooolJ-(I
Q 0
0-0- 0--0-0
o - oo
0 0 020
'jl 0
Do
- ·-
0 Q
&,o'
oo 0000-0 0 0 0 O O
'? 0
D O 0-0--0.-0-0 0-0-0-0-o Do
2500 0 0--0 0-0 0 0 - 025
oa 0 0- 0 0 0 0 0 0 0 Q Do
0 0 0-0- 0-0-0 0-0-0-0- 0
oo 00000 0 0 0 O 0
'ii 0

0 0 0-0--0 0 0 0 0 0 0 0 &0
' 0
0 0 30 o-<>- 0 0-0 0--0- 0-0- 0 30 0. ii
ABCDE F G H f J

. 4 7 Schtmatic - Cirant illustrating the occurrence of erroneou.s lotr1,_,

fiKUTt · · .,__ .,... A-d and connection with Analog Discovery ,1_.,_ 6 "-'ll
pulses on DrtOf.UIUUI ' "'<' Vu:t

Figure 4.8. Oscilloscope Waveformsforciradt infi.gure4.7.

Case Study 3: Disappearance offunctional short impulses

Simulate and analyze in 0rCAD the circuit in Figure 4.9. that illustrates this
type of defect. Input pulse duration has to be small. C.onsidertngthe first chain
nf gates, AND gates, the rising edge of the pulse is delayed more and more, the
pulse becomes narrower and finally it will no longer ha-..-e a sufficient duration
to trigger gate Ul D. On the other hand, in. case we consid!!I the dwn ofNAND
it;es, egdes are alternated and after two gates the initial duratlon of the pulse
1. re.stored.

54 55
 chapter 5: Deterministic Test Generation

R,eguixed equipment
- •
•
QrCADl0.5
waveFonns (Digilent)
• Analog Discovery (Digilent)
• 1 x 74HC04 NOT gate
• 1 x 7 4HC08 AND gate
. . 'ordisapFaranaof shortimpulse.s
Figure 4.!J. Cimnt tmmp 1t J •

- • lx74HC320Rgate
• BTeadboard
I
I I I I • Wires
I I ;rµrpose of the Chapter

~
1. Understand the principles of determnistic test generation for circuits
2. Generation and validation through simulation of test vectoxs for
combinational circuits using deterministic method
--..::::
-- - 3 . Learn how to test circuits using deterministic test vectors.

• ... • ••
""'
Theoretical background
Figure 4.J 0. Trattsien: simulation results for circuit in Figure 4 .9
Practical implementatfun
Being that these effects only manifest themselves at high frequencies (short
impulses) by analyzing the documentation available on the Digilent website
<w:ww41@entinc.com> upWn why a practical implementation for this
circuit cannot be done using the Analog Discovery.
There are three major methods for determining test vectors the deterministic
way: the boolean difference method, the path activation method and the
critical path method. All of these target specific defects \n a given node of the
circuit and only calculate the test vectors necessary f or detecting the defect in
question.
'the boolean difference method
This method starts with the presumption that the r~sponse of the circuit
wi ~hout a defect is different than that of the circuit containing a defect.

Let s suppose we have a circuit with n variables for input:

Tht circuit outputs the boolean function:

F(X) =F(x1,x2, - ,x1,--,Xn)

If the variable .x1 is erroneous due to a defect, meaning that it takes thevalu
Ya, the output function will be:
 ., ..
t,, ...... •. . . -
C'l111pt,•t G: PHcudo-~andom Test
Generation

~red c<1ulomcnt
• OrCJ\IJ IO, '>
• W1111e1'01nu (IJl1;1llr11t)
• Analoe lJl,covery (Olr,llr-nt)
• I JC 'l'1JIC'(M 110'1' g:,111
• J ,c 74 11C08 ANIJ eutc
• I X 74 l1C''32 011 8'1lt>
• z x '/4JIC7◄ D typ" flip flop
• Breadboard
• Wire,

_rt11J>ose of the Chapter

1. Under&tand the princlplu of pseudo-random test generation
2. Generation of pseudo-random test scquertcee using Unear Feedback
Shift Registers
3. Learn how to test clrculte using pseudo-random teit vectors

'theoretical background
For generating pseudo-random test vectors Linear Feedback Shift Registers
(LFSR) are used. To begin, we consider the feedback registers in Figure 6.1. The
presented structures are au tonomoU&, meaning that they operate without any
input signals being applied at their inputs (the clock signals that determines
the shifting of data in the registers is not considered an input signal). Each cell
from the structure of the registers i.s considered to be a D type flip.flop. It can
be observed that the ope.r ation of the registers is cyclic, meaning that if a dock
is constantly applied, then the output sequences will start re~ating after a
given number of clock pulses. The maximum number of states through which
a register can pass through is 2n, if it has 11 flip-flops. For example, a b\naxy
counter with n flip-flops will count from Oto 2r. -1

The -:1rcuit in Figure 6.1 (a) passes through two lltat,s. If the flip•flops aft!
initi Ii.zed to 00 or 11, then these vah1e; will never change when appl,ing a
clock However, if the flip-flops are initialized to 01 or 10 then the glvm state
wi' repeat aftertv.-o clock pulses. Tobenotedhoweverthatthefintc:asew \Jo
eye• le, but the changes in states cannot be observed.

69
68
 Ouq,l.lt

.. O 10 l -rhe cl.reult In Figure 6.1 Cb) hns the same components lf \t I.a inltl.Uud with
l tbesequenc.e repeatedatth.eoutputw\11 have a length of 1 bit and will have
Sl1l 1ttpe1ted
~e logical value of l. If the same c.lrc.uit \s lnitiallud with ol\ , It can be
.s. wb$equence
bscrved that the length of the aequence that ls repeated at the output ls of four
0
bl.tr~, t,e.ing 1100.

the example In Figure 6. 1 (c) a circuit is presented that. has the \ength of the
[!\tput sequence equal to 2• - 1. lt c.a.n be observed that passing through the

r -• -6
Oulpllt
11que"c•
~~00 state is avoided bcq1use this would lead the register to be "atw:k" In this
state. All other possible states are pass~ through successively by the registe1:.

aased on the previ?us examples it can ~e said that the operation of a L'FSR \s
based on the delay_m~oduced by the filp-fl?p and on the properties of binary
'-" 111 addition and multiplication. At next table ts the hue of binary addition and
subtraction.
SJJS Rep. .1..i
s. rubJ.equanm
Table 6.1. Binary addition and subtraction
l J
I
s,.S. :t O l
l l
0
$, 0 1
0 0 0 1
s, J 0 0
s, 1 0
_!1 L..-
0 J r 1 1 0
vs.

(b)
The next base property results:
r O•
6

I I
•
Output
Hqu•nce
X + X = -,: - X = X - X =0
I The presented circuits are linear because the principle of superposition is
8W -,- , respected: the response of the circuit to a linear combination of stimuli is
s, R•peat•d obtained as the linear combination of the responses obtained for each
,ubuqu•1101 individual stimulus.
s, 0 0 l
s, 1 0 0 Autonomous LFSR
Si 0 1 0
s, 1 0 1 The first category ofLFSRs analyzed are the autonomous ones, so those that do
s, J J 0 not have data at their inputs. ln Figure 6.2 and figure 6.3 +he two canonical
1 1 1
-s,.-s,~---·· 0 ·-·· 1 ··--1- implementation forms are presented. The C1 constants are binary ~on~ts
wh:",ch signify an existing connection if C1 = l anc;l a missing connection \f c, c
o.
(c)

Figure 6.1. Exmnplefor illustrating th~ operation of LFSRs

70
71
 ◄
(p-
~
':t
1,
C, Q 0 S-.
if we consider the lnitial state to be ch&racterlzed by the
._,.0-.,, -. a••♦ 1•0- and substitutlng the ClCpreU\oa Ulecocffidmu
:~don is obtained for the ~ o r pol}'Tl0m1al: • following
~ ,... ....,
.-o ala;
-- a-a: a Q
• D Cl: Q,, • C(r) • rr., c,x1(a_,r-< + •-+ a.,x-')
.D

?'
..... ....
?
.....
LJ
Firtc canonical form ofLFSR.s th
1 + t;., c1r 1

A$ it can be observed, the gmentor polynomial wu a p ~ asa function of

r initial statu a.,.a...1,a-s, - ,a_.,,a • of the reot .. - __ ... th
- o· •...:• .,,.. e TCact\on
f'ir.JTl 6. 2• ,oefficlenU c1 ,c,,.- ,c•: The denomlnator from the obta1ned definition of the
- - -- - - generator polynomial is called the charactnutic polynomio.l l'(x):
l'(x) .. 1 + c 1 x + c 2 r' + .•• + c.r•

for a 5hift --'

reginer with n cells it Is compulsory to have c • 1 Mo •
reover, 1t can
be observeu th at P(x) ·ts a funcoon . •
only of the reaction •--u:...: __ .,
. charact . th . = • = t i l t l ,UJU
therefore 1t enus e reaction structure of the circuit.

If the initial state of the register is a_ 1 = a_, = .•. = 0 •

0 and Q._ - 1 •'- _
•a1 • • l-a UICII
the generator po lynoml 1s reduced to:

Figurt 6_3. ~ctmd CQUJnicaJJorm of LFSRs G(x) = -

1
P(x)
•
-
~
a_x"'°"....
c1uuaamsticpolynomials For this situation, if the sequence generated at the output is periodic v..-ith a
A uwci of numbers a..a1,az,-,C1m• ·- can be associated with a P01Ynorni.J period of p the generator polynomial can be written as:
call~ apr:aazarfa1u:rim1 &(r):

L-
1
G(x) = P(x) = (ao + a 1 x + ... +a,.,~')+
&(x) = 4o +ll1X + a2r1-'- ••• + a.rm + ... = ClmX., +x"(ao + a1x + ··• + ci.-1 x,-') +
m•O +x1 "{Clo + Cl1X + ,., + 12p-1xP•1) + , .. m
= (o.o + a,x + ··· + 4,_,xP-1 )(1 + x• + x1 • + ... ) =
The sequtncr 0o,a1,a2,-,0.,- 1ep1esents the output sequence of the LFst (CJ.o + 41% + ••• + 4,-1XP-l)
whm0t .. Oar 1. 1-x'

For the structure premited in Figure 6.2 it can be observed that the cumm This shows that the characteristic: polynomial divides 1 - xl'.
sta.e depends on the previous states and therefore the following recuneo~
rel.tionship can be written for the a. coefficients; It can be shown that for every generatm polynomial two c:hancterlstlc
polynomials exist, polynomial P(x) and its reciprocal:

p•(x) = x"P G)

72 73
 niaJCim um lcngt/1 Jcquencc u the cycUc sequence of rlod •
Tbe8 LFSR with n registelli, lie 2 - \ &enerated
bY
ri,nitlve polynomial u the C!hata.cterlstlc po\ynomla\
A P
,equence wjth m .a ximum length. a.uoclated to a

irreducible polynomial ls a -polynomia\ that cannot be f-.ct rued, .

~visible only by l and itself. o l.e.. \t is

'fhe following theorems can be proven·

1• tftheinitialstateofaLFSRlsn_1 •a 1 . . . . . a
. - l-1'1
=Oand
Cl-w • 1 ,
the generated sequence is periodic With a 'l)erlod of k, whete k \s the
,n
th

smallest integer for which P(x) divides (1 - x').

r
2_ An irreducible polynomial P (x) fulfills the following two conditions:
a. Has an odd number of i:1 • l coefficlenta·
1 '
__a -,
Q Q ►
xn-1 " D Q
where k "" 2" - 1.
•
b. If its degree is greater than 3, then P(x) must divide (l + x'),

3 . A p.rimitive polynomial of deg_ree n is ineducible if the smallestinteger

D I ,c
Xl 1c for which P(x) divides 1 + x" is k • 2• - 1.

3 n The number of ~rlmitive polynomials for a LfSR of n degree can be obtained

1 using the following formula:

where

7,n-;:;;
I,'~ r xn-1
► D Q
xrt-2
~ D Q -- ►
X
Q 41(n) =n fl (
11111
1 - ~)
p

f> -
1---'
2
l 3 n In the above formula p is taken as greater than all the prime numbers that
divide -n. The 2 index shows the fact that each polynomial has a reciprocal
polynomial.
Figure 6.4. Implementation of the characteristic and redproca 1polynomials

The periodicity ofLFSRs

It was shown thatifthestructureofa LFSRcyclicallypassesthrough a number
of states, then the output sequence will also be periodic. The maximum length
ofa period is 2• -1,if n is thenumberof registers in the structure.

74 75
 . . d reciprocal polynomialsJo,-
ct~nstrc an n froht J
. ·(ivi c1rara p·(x) lo Jo
.2, pr,/111
- n
p(.r)
x+l
~estudies
- l
,-+1
r 2 +r+1
case study 1: Pseudo-random method
- 2
x1 +~+ 1
x 3 +r1+1
sider the circuit in figure 5.1. and the rob . .
co~~ve the logical value Ols 0 ,5.
tO J ~
P llbibty for e-.ch \npul I\ a C D
• , •

-3 x' +x+ 1
Pl• r: - P2 • i>g • O!.
x◄ +x 3 + 1
x•+.r+l pctetJTline the probabili:Y of apl)earance of log\c.a\ va\\,
4
x 5 +x3 + 1 at the output Z considenng the circuit wlth.out defect. e O and\ogk&l valut 1
~ .r5+:r1+1
5
x 6 +x5 +1
.r'+.r+l
6
.r7 +x6 + 1
.r' +x+ J
7
.re+ x1 + xl + x2 + 1
.r• + ,r6 +.rs + X + 1
8 Pi "" Pl · Pl • 0.5 • 0.S • 0.2$ • po~ • 1. - pt, .. v.
,. 7 s
x 9 +x5 +l
.r' +.r• + 1
9 P8 = pg . i>g ,.. o.s . o.s ... o.25 • PA • i - J>2 • o.1s
10 7
.rtJ)+.r3+1 .r +x +1
10 Pl = Pj • P2 = 0.75 · 0.25 = 0.1875 ~ p%1 • \
-
poz • 0.ollS
.,

{Pj = 0.1875
characteristkS ofmaximum length sequences
lPJ = o.a12s
enerated by LfSR.S that are associated to a primitive polyn
Seqaluencc~lt-' pseudo-random sequences. They have a series of properti OtniaJ consider a stuck-at O defect in node F. Determine:
are so t:U ·gna1 s· th es that
make them similar to random S1 s. mce ey are Periodic and
deterministic, they are called pseudo-random.

1 _ The number of 1 bits differs from the number of Obits in a sequence of

length zn - 1 by one unit. PP = 1 ~ p: = p~ · pg =1 · 0.25 = 0.25 ~ Pl = 1 - Pi = 0.7S
2. Evey time the sequence is repetead the number of binary 1 and 0
values is the same for each sequence. f/1 == 0.2S
3. In each sequence half of it repre&... .ts ~ uccessions of different bits of lPj = 0.75
length 1, a quarter represents sucession .. of different bits of length 21
Consider a stuck-at 1 defect in node F. Determine:
oneeigth represents sucessions of ctiffertnt bits of length 3 and so on.

All these p:°perties determine the frequent usage of LFSRs for generating test
sequences m BIST circuits.

Pl = 1 ~ pi =0 ~ Pl = 1 - ~ =1

77
76
 pf .. 0
{PJ == 1
billtyofthe output signal?
tbePfOb a
rirJluence .
oes tlJedefeC ce generator ustng a LFSR With_r,
floW d randoJll sequen rcial: P(x) = x4 + xt + l . .Fot th0lq teb
ment a pseu~~r11cterisdc pol}'llp_'.'.u, in orCAD the designe(l .4_ e lo&ir~'.
IIJIPIe we
o;;,,=~ ces. •u••
~frQl11. uit use XOR ga sient simulation. 1su
· v· alize -,..cu.it .....
the ou il.1\4
summati~n ~tionalitYbyau:an and identify each state the cir~~Q.ar
siJTlulateics/ul1 d also the dock gh 2 • _ 1 states (n - number Passec
each D tlip-flop; oretrlt pass thrO::U.Ougb 0000 state. Of teU,)1
thrOugh. voes • uit does ,not pass
]Jodee that the cifC

~~-~-------- ..
f•,rure 6 · ·
..,-
7 Jmplementation.of the pseudo-random sequeM•• ge .
'""" nn-citor 11.Slna LFSR
for P(X)"x"4+X" l + 1 in connection with the Initial circuit .,..
... -
- ..._,......
_
- --
~

...
~

~ .
'-
i -
.., ,__
- =~ ... rl'- ,...=
. - ~

'·;- '"
4-1~
;:;- .
I - ~ ~
~

I ~

\ \
I \ I

\
I ,·

Figute6.5. Jmplementat
ion of the pseudo-random sequence generator Using l.FSJt
for P(x) == x• + x + 1 \
I \
\I \ '
\ I

.., . 'I
,. ••• ,... ... " . '' .. \
' -'-' _, "
j:
.f-u_.
.., • -= ;;_,,,' -
N
~,
'
I
I ' .
- - . - -- - - - - ___.~
=

" ~r
•••
.J

I
- J-
=
~

I
Q
- J "r' J :.r ., J
U' .r J figure 6.8. Transient simulation for circuit in the above figure

,,
I.I
1,

I I
I II 11

"
'
I

: I
f
'
I
I

,,..
II II
....
,,_ ,.,.

Figure 6.6. TransieTit simulation resultsfor circuit in the above figure

Connect the inputs A, B, C, Dfrom the circuit in Figure 5 .1. at the outputs of
each D flip-flop in proper order. Simulate the circuit and ch eck the states that
output Z passes through.

78
79
 d ,trnulat~ th~ clrcult.
,tlJCk-at o defect an
,..,
0
i,dt fa 1
pi,ce ...

.
••
I
·-
II....I
.. ... ...
• . uJariDnfor circuit in Figurt 6. 7 with a stuck-at Oder
. 6 9 rransiDlt s:rn
FIi"" · ·
. --", F
rn,wc,
:1eq ·- ·- ·- ...
d«t and sunuJ.a_rt! the circuit. figW'' 6.1 J. Logic Analyur Digital Wavefornu , 0 . __ , • .
r ar..... t in flgllre 6,5
. _J.fastUCk•ltl d
J'
pfactlllOU- J)Jlect the inputs A, B, C, D from the circuit at the outpu
~o proper order. Simulate the circuit and check the states~ each D flip-flop
~, in ft.,
tbfOU6-'-
output2.passu
•
""' •
II I
I I

I I
I

..
I ~
-~ ... - - u~ •• •
I I
.... ,... .... .... ...
I I

Figurt 6.10. r,ansimt simulation/"; ci~C:!t in Figure 6. ?with a stuck-at J deftct

znn-F

PractiaJ Implementation

Implement the previous circuit from figure 6.5 on the Breadboard using
74HC74 D flip-flops, 74HCB6 XOR gate and \\'lreS. Use the Analog Discovery
Board and Digilent VlaveForrns to generate a rectangular signal for the clock
and the power supply of sv and visnaJire the \l.'i worms using Logic Analyzer.
-
Co:npa.re the results obtained by simulation with those obtained in the Figure 6.12. Logic Anal.)'ZD Digitcl \'laveforms for drcuit in Figurt 6.7
practial implementation. .[)e+.erm.ine lf the am.tit passes through all 211 - 1
states. Gtnerate for the dodc a rectangular signal of SOOus period. Place ln node Fa stuck-at Odefect and simulate the circuit.

80 81
 -- - --
chapter 7: Code Coverage and .
Using Razo Unit 'l'
teat Tessy

9111
•red eg11ipment
~ • Tl!SSY software
gg!Pose of the ~hapter .
_ c}lapter is orgaruzed as a tutorial which aims to \n:
~ g Tessy test system. lt:zrat

1 Readers learn to create a new databue, new 'mod

· folder and add the tested source files. ul
2 _ 1,.earn_ how to define passing directions 'IUUblu
-"fiordraiit in Figure 6. 7 with a stuc...· en o functiOilS-
• Ana.{)'zer wave;.F,o,,,_
Fi,fu.rt 6.13. Logi& defect in node F 3. 1,.eam to develop test cases.
4 _ t.eam how to execute a test, evaluate the teat th:
efect and simulate the circuit. monitor the code coverage. OUi
Place in node fa stUclc-at 1 d

'l'beoretical backi];ound
-T stingis an activity aimed to evaluate the cal)ahilitiu
estem in order to verify if it works properly. Softwau,
sy
executing a program WI'th the rnearung
. of finding emn:
systems, m_ost of th_e softw~ defed.5 are due
manufactunng. Detecting the design defects in softwa
for reason of complexity. Because software and any c
continuous, testing boundary values are not i\l
correctness. All the possible values need to be testec
complete t esting is infeasi'ble.

A primary purpose of testing is to detect software fai

corrected. Testing cannot establish that a product fw
condition s but can only establish that it does not
specific condition s. Thl' ccope of software testing
... .. ••• code as well a s execution of that code in various env
Figure 6.14. Logic Analyzer Waveforms for circuit Figure 6. 7 with a stw:k-at 1
The complexity of testing depends not only on the 1
defect in node F
source code, but also ,;n the software quality u
duration of the impler entation will be estimatE
available and it is based on its complexity core

82 83