1.

-- Déclaration de l entité
entity PorteATrois is
Port (
oe: in std_logic; -- Output Enable
data_in: in std_logic; -- Input data
data_out: out std_logic -- Output data
);
end entity PorteATrois ;

-- Architecture Definition
architecture Porte3 of PorteATrois is
begin
process (oe, data_in)
begin
if oe = '1' then
data_out <= data_in; -- Output data when Output Enable is high
else
data_out <= 'Z'; -- High impedance state when Output Enable is low
end if;
end process;
end architecture Porte3;

1.2

-- Définition de l'entité
entity Multiplexeur is
generic (
N : integer := 12 -- Taille du vecteur d'entrée
);
port (
e_0, e_1 : in std_logic_vector(N-1 downto 0);
sel : in std_logic;
S : out std_logic_vector(N-1 downto 0)
);
end entity Multiplexeur;

-- Architecture flot de données

architecture TP of Multiplexeur is
begin
process (e_0, e_1, sel)
begin
if sel = '0' then
S <= e_0;
else
S <= e_1;
 end if;
end process;
end architecture TP;

1.3

-- Déclaration de l entité
entity UAL is
Port (
A, B: in std_logic_vector(7 downto 0); -- Assuming 8-bit operands
alufs: in std_logic_vector(3 downto 0);
S: out std_logic_vector(7 downto 0)
);
end entity UAL;

-- Architecture Definition
architecture TP of UAL is
begin
process (A, B, alufs)
begin
case alufs is
when "0000" =>
S <= B; -- Transfer B
when "0001" =>
S <= B + 1; -- Incrémenter B
when "0010" =>
S <= A + B; -- Somme de A et B
when "0011" =>
S <= A - B; -- Soustraction A et B
when "1000" =>
S <= A AND B; -- ETLogique
when "1001" =>
S <= A OR B; -- OU logique
when "1010" =>
S <= A XOR B; -- XOR logique
when others =>
S <= (others => '0'); -- le cas par defaut
end case;
end process;
end architecture TP;