THIẾT KẾ VI MẠCH

GV: hoangtrang@hcmut.edu.vn

Chương 2:
Giếng bán dẫn (well/tub)

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

Substrate, n-well technology: quick overview

p- substrate: popular => n-well technology: popular.

Other reasons?
Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design
Parasitic diode, n-well as resistor: quick overview

• Parasitic diode (pn junction)

• Resistor
=> Analyze to understand, and develop model for later

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

n-well Fabrication

Photolithography process
for n-well

A, B: as only for reference

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology

n-well Fabrication: thermal oxidation

SiO2: thermal oxidation

very popular in CMOS Fabrication

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

n-well Fabrication: thermal oxidation

•Silicon Dioxide Dry Oxidation

High quality electrical insulator
Diffusion/implantation barrier Si + O2 → SiO2
Passivates silicon surface
Wet Oxidation

Si + 2 H 2O → SiO2 + 2 H 2

Growth Occurs 54% above and

46% below original surface as
silicon is consumed

Temperature for oxidation: 900 0 C – 1100 0 C

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

n-well Fabrication: thermal oxidation:
Oxidation on <100> Silicon

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

n-well Fabrication: thermal oxidation:
Oxidation on <111> Silicon

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

n-well Fabrication: thermal oxidation

Note:
• Wet oxidation is much more rapid than dry oxidation
• Note that dry oxidation appears to always have some initial
oxide present
• Dry oxidation (slow) produces higher quality oxide than wet
oxidation
• Oxidations often consist of sequence of dry-wet-dry
oxidation cycles -Most of oxide is grown during wet phase
• Dry oxidation usually used to grow gate oxides

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

n-well Fabrication: formation n-well

Oxide: minimum
Depend:
thickness is required
+ donor materials
(acceptor in p-well
formation)
+ Diffusion time
+ Diffusion temperature

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

n-well Fabrication: Thermal Oxidation
Masking Properties of SiO2

• Required oxide thickness

depends upon dopant species
and temperature
• Hydrogen greatly enhances
diffusion of boron - wet
oxidation release hydrogen

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

n-well Fabrication: formation n-well

In case:
Diffusion of Donor atom Oxide: minimum
thickness is NOT
obtained

n-well: expected

“n-well”: un-expected => error

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

Layout n-well

Scale factor: λ

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

Design rule for n-well

DRC (Design Rule Check): important step in IC design flow

DR concept.

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

Resistor for n-well

𝜌 𝐿∙𝑠𝑐𝑎𝑙𝑒 𝜌 𝐿
• 𝑅= ∙ = ∙𝑊
𝑡 𝑊∙𝑠𝑐𝑎𝑙𝑒 𝑡
𝜌
• 𝑅𝑠 = 𝑡
𝐿
 𝑅 = 𝑅𝑠 ∙ Rs : Sheet resistance.
𝑊
Square resistance

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

Resistor for n-well: layout

0.6 Rs

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

n-well Fabrication: some remarks

. n+ field, p+ field implant: imcrease threshold voltage.

. FOX (Field Oxide) or ROX (Recessed Oxide): will be discussed
later

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

Remind: semiconductor physics

Review: energy band, Donor, Acceptor, ….

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

Remind: semiconductor physics

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

Depletion layer Capacitance

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

Depletion layer Capacitance

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

Depletion layer Capacitance

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

Storage/Diffusion Capacitance

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

Storage/Diffusion Capacitance

Circuit used to demonstrate simulation of diode’s reverse

recovery time
Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design
SPICE modeling

Rs : constant (although phenomena on R: Change)

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

RC delay model through an n-well

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

RC delay model through an n-well

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

Twin well/Triple well process

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

Design rules for the well

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design

 END
CHAPTER 2: N-WELL

Hoàng Trang, hoangtrang@hcmut.edu.vn. Chapter 2: well technology; IC design