Lecture 10: Physical Synthesis

-Routing

1
Review
q Physical synthesis (placement, routing, etc)

System Spec. Partition

Graph
Netlist…
Architecture
Module(a, b) Floorplan
Input a;
Output b; Graph
Function, logic Placement
Placement
Circuit design Analytical Cells

CTS
Physical design Tree

Signoff Routing
DRC, LVS Graph
Routing
Manufacturing Timing
Disk, legacy C codes Cells
Testing (Linux LSF cluster)
22nm 10B+
Final chip NFS transistors

2
The Problem

Thousands of macro blocks

Kilometers of wire.
Millions of gates
Millions of wires

3
Basic Routing Problems
q Scale
q Big chips have an enormous number (millions) of wires
q Not every wire gets to take an “easy” path to connect its pins
q Must connect them all--can’t afford to tweak many wires manually
q Geometric complexity
q It used to be that the representation of the layout was a simple
“grid”
q No longer true: at nanoscale, geometry rules are complex – makes
routing hard
q Electrical complexity
q It’s not enough to make sure you connect all the wires
q You also must ensure that the delays thru the wires are not too big
q And that wire-to-wire interactions (crosstalk) don’t mess up
behavior

4
Physical Assumption
q Many layers of wiring are
available for routing
q Made of metal (today, copper)
q We can connect wires in
different layers with vias
q A simplified view
q Standard cells are using metal
on layers 1,2
q Routing wires on layers 3-8
q Upper layers (9, 10) reserved
for power and clock
distribution

5
Typical Example (5 Layers, Circa 2000)
q Some terminology
q FEOL: Front end of line. Chip
fabrication steps that make
transistors on Si wafer
q BEOL: Back end of line. Fabrication
steps that make layers of wires on
top of transistors

q This picture
q Cross sectional view of FEOL and
BEOL structures in 5-layers of
wiring…
q … along with packaging connection
(“bump”) which is how chip
connects to pins on package

6
 Typical Example (5 Layers, Circa 2000)

Package
interconnect,
(like a via), but
from chip to board Layer 5 metal Thicker layers
(less resistance)
Layer 4 metal for clock, power

Vias, connect Layer 3 metal

Metal layers
k and k+1 Layer 2 metal Wiring for logic
Layer 1 metal

Transistors to make gate-level logic

7
Placement vs Routing
q There are lots of different placement algorithms
q Iterative methods. Used mainly for high-level
floorplanning, not gate layout
q Many analytical methods based on solving/optimizing
large systems of equations
• Quadratic wirelength, exponential model, etc.

q There are not quite so many routing algorithms

q There are lots of routing data structures – to represent
the geometry efficiently
q But there is one very, very big idea at core of most real
routers…

8
Big Idea “Maze Routing”
q From one famous early
paper:
q E.F. Moore. “The shortest
path through a maze”
q International Symposium on
the Theory of Switching
Proceedings, pp 285--292,
Cambridge, MA, Apr. 1959.
Harvard University Press

q Yes – it’s that Moore of

“Moore finite state
machines” fame
q Given a maze (or a graph),
find a shortest path from
entrance to exit
9
How to Get from “Mazes” to “Wires”
q Make a big geometric assumption: Gridded routing
q The layout surface is a grid of regular squares
q A legal wire path = a set of connected grid cells,
through unobstructed cells in grid

For us: wires are also

strictly horizontal and vertical.
T
obstacle No diagonal (eg, 45o) angles.
A path goes east/west, or
north/south, in this grid.
N
S W E

10
Grid Assumption
q A critical assumption – implies many constraints on wires
q All wires are the same size (width)
q All pins we want to connect are also “on grid” ie, center
of grid cell
q Wires and their vias fit in the grid, without any
geometry rule (eg, spacing) violations

Via Layer K

Layer
K+1

11
Maze Routers History
q 1959 – Basic Idea
q E.F. Moore. The shortest path through a maze. In International Symposium on
the Theory of Switching Proceedings, Apr. 1959. Harvard University Press
q 1961 – Applied to electronics (board wiring)
q Lee, C. Y., “An algorithm for path connections and its applications”, IRE Trans.
on Electronic Computers, pp. 346-365, Sept. 1961
q Chester Lee of Bell Labs invents the algorithm; gets famous for “Lee routers”
q 1974
q Rubin, F., “The Lee path connection algorithm”, IEEE Trans. on Computers, vol.
c-23, no. 9, pp. 907-914, Sept. 1974.
q Frank Rubin applies some ideas from recent AI results to make it go much
faster (some interesting ideas in the AI can be applied to this and vice versa)
q 1983
q Hightower, D., “The Lee router revisited”, ICCAD, pp. 136-139, 1983.
q Dave Hightower uses fact that “modern” computers have big virtual memory,
builds great router
q ACM ISPD 2007-2008 Global Routing Contests
q ACM ISPD 2018-2019 Initial Detailed Routing Contest
q … a lot of works still going on

12
Maze Routing Strategy
q Strategy
q One net at a time: completely wire one net, then
move onto next net
q Optimize net path: find the best wiring path

q Problems
q Early nets wired may block path of later nets
q Optimal choice for one net may block later nets
q We are just going to ignore this one for the moment…

13
Maze Router: Basic Idea for 2-Pin Nets

q Given:
q Grid - each square cell represents
where one wire can cross
q A source and target
S
q Problem:
q Find shortest path connecting
source cell (S) and target cell (T)
q When using cells, a wire can:

T
cross or bend

14
Maze Routing: Expansion

S Start at the source

Find all new cells that are reachable

at pathlength 1, ie, all paths that are just 1 unit in
1 total length (just 1 cell) - mark all with this the pathlength

2 Using the pathlength 1 cells,

find all new cells which
2 1 2 are reachable at pathlength 2

2
Repeat until the
target is found.

15
Maze Router Step 1: Expand

q Strategy
q Expand one cell at a time
S
until all the shortest paths
from S to T are found.
q Expansion creates a
wavefront of paths that
T search broadly out from
source cell until target is
hit

16
Maze Router Step 1: Expand

q Strategy
1 q Expand one cell at a time
S
until all the shortest paths
from S to T are found.
q Expansion creates a
wavefront of paths that
T search broadly out from
source cell until target is
hit

17
Maze Router Step 1: Expand

2 q Strategy
2 1
2
q Expand one cell at a time
S
until all the shortest paths
2 from S to T are found.
q Expansion creates a
wavefront of paths that
T search broadly out from
source cell until target is
hit

18
Maze Router Step 1: Expand

3 2 3 q Strategy
2 1
2 3
q Expand one cell at a time
S
until all the shortest paths
3 2 3 from S to T are found.
3 q Expansion creates a
wavefront of paths that
T search broadly out from
source cell until target is
hit

19
Maze Router Step 1: Expand

3 2 3 4 q Strategy
2 1
2 3 4
q Expand one cell at a time
S
until all the shortest paths
3 2 3 4 from S to T are found.
4 3 4 q Expansion creates a
wavefront of paths that
4 T search broadly out from
source cell until target is
hit

20
Maze Router Step 1: Expand

3 2 3 4 5 q Strategy
2 1
2 3 4 5
q Expand one cell at a time
S
until all the shortest paths
3 2 3 4 5 from S to T are found.
4 3 4 5 q Expansion creates a
wavefront of paths that
5 4 5 T search broadly out from
5 source cell until target is
hit

21
Maze Router Step 1: Expand

3 2 3 4 5 6 q Strategy
2 1
2 3 4 5
q Expand one cell at a time
S
until all the shortest paths
3 2 3 4 5 6 from S to T are found.
4 3 4 5 6 q Expansion creates a
wavefront of paths that
5 4 5 6 T search broadly out from
6 5 6 source cell until target is
hit

22
Maze Router Step 1: Expand

3 2 3 4 5 6 q Strategy
2 1
2 3 4 5
q Expand one cell at a time
S
until all the shortest paths
3 2 3 4 5 6 from S to T are found.
4 3 4 5 6 7 q Expansion creates a
wavefront of paths that
5 4 5 6 7
T search broadly out from
6 5 6 7 source cell until target is
hit

23
Maze Router Step 2: Backtrace

q Now what? Backtrace

3 2 3 4 5 6
q Select a shortest-path (any
shortest-path) from target back
2 S 1 2 3 4 5 to source
q Mark its cells so they cannot be
3 2 3 4 5 6 used again – mark them as
obstacles for later wires we
4 3 4 5 6 7 want to route
q Since there are many paths back,
5 4 5 6 optimization information can be
T 7 used to select the best one
6 5 6 7 q Here, just follow the pathlengths
in the cells in descending order

24
Maze Router Step 3: Clean-up

q Now what? Clean-up

S q Clean up the grid for the
next net, leaving the S to T
path as an obstacle
q Now, ready to route the
next net with the obstacles
T from the previously routed
net in place in the grid

25
Maze Router: Obstacles

q Also called “Blockages”

q Any cell you cannot use for
S a wire is a an obstacle or a
blockage
S q There may be parts of the
routing surface you just
cannot use
q But most importantly, you
T label each newly routed
net as a blockage
T q Thus, all future nets must
route around this blockage

26
Classical Maze Router
q Summarizing three main steps:

q Expand
q Breadth-first-search to find all paths from source to
target
q Backtrace
q Walk shortest path back to the source and mark path
cells as used
q Clean-Up
q Erase all distance marks from other grid cells before
next net is route.

27
Some Algorithmic Concerns
q Storage
q Do we need a really big grid to represent a big routing problem?
q What information is required in each cell of this grid?
q Complexity
q Do we really have to search the whole grid each time we add a
wire?
q Technology
q Just 1 wiring layer? How do we do 2 layers? 3? 4? 6? 8? 10?
q How do we deal with vias (connecting different routing layers?)
q 2 issues here
q Applications of basic algorithm versus implementation issues

28
How do we Deal Multi-point Nets
q Multi-point Nets
q One source à Many targets
q You get this with any net that represents fanout (ie, almost all real
nets)

q Simple strategy
q Start: Pick one point as source, label all the others as targets
q First: Use maze route algorithm to find path from source to
nearest target
• Note: You don’t know which one this is up front, routing will find it
q Next: Re-label all cells on found path as sources, then rerun maze
router
using all sources simultaneously
q Repeat: For each remaining unconnected target point

29
Multi-point Nets

q Given:
S
q A source and many targets
q Problem:
T
q Find a short path
connecting source and
targets
T

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Multi-point Nets

3 2 3 4 5 q First segment of path...

q Run maze route to find
2 S 1 2 3 4 5
the closest target
3 2 3 4 5 T q Start at source, go till we
4 3 4 5
find any target

5 4 5T

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Multi-point Nets

q Second...
3 2 3 4 5
q Backtrace and re-label the
whole route as Sources for
2 S 1 2 3 4 5 the next pass

3 2 3 4 5 T
q Note – this is different
4 3 4 5 q We don’t relabel the path as
blockage (yet), as we did
before
5 4 5T
q We label it as source, so we
can find paths from any point
5 on this segment, to the rest of
the targets

32
Multi-point Nets

q Second...
q We will expand this entire
S set of source cells to find
S T next segment of the net
q Idea is we will look for paths
S
of length 1 away from this
S S whole set of sources, then
length 2, 3, etc.
q Go till hit another target

33
Multi-point Nets

3 2 3 4 5 q Trick
q Expand from all these
2 S 1 2 3 4 5 sources to find the shortest
2 S 1 2 3 4 T 5 path from the existing route
to the next target
2 S 1 2 3 4 5

2 S 1 S 1 2 3 4 q Next: Backtrace as before

q Follow pathlengths in
3 2 2 3 4 5
decreasing order from
target, to some source cell

34
Multipoint Nets

q Finally
q Do usual cleanup
S
q Mark all of the segment cells
S 1 2 3 4 T 5 as used and clean-up the
S
grid
q Now, have embedded a
S S
multipoint net, and
rendered it an obstacle for
future nets

35
Is this Strategy Optimal?
q Does this method give us guaranteed shortest multi-
point net?
q No!
q Maybe surprising, but this is just a good heuristic
q The optimal path has a name: called a Steiner Tree

q How hard is to get the optimal Steiner Tree?

q NP-hard! (ie, exponentially hard)
q Yet another example of why CAD is full of tough,
important problems to solve

36
 Steiner Tree Construction

2 so-called
“Steiner-points”

EASY HARD!
Pins to connect Route it so we Redraw it--different Now we can see the
guarantee each orientations better (shorter)
2-point path of 2-point paths Steiner tree
is shortest; this is
Minimum Spanning
Tree

37
Real Routers …
q Are often iterative
q Problem: How do you know where the wire wants to go? You
don’t know till you know where the other wires want to go?
q Solution: So, route all the wires, leave some info on the routing
surface, or even previous wires, about congestion, overlaps, etc.
Then iteratively ripup (remove) and reroute the wires, using cost
info from geometric footprint of previous wires.

q Are always hierarchical

q Problem: measured in terms of metal pitch, big chip has an
intractable number of locations to search for each wire
q In 2008, the M1 pitch was about 120nm. A simple gridded router
for 1cm x 1cm chip = 83K x 83K cells = ~7 billion grid cells (ugh)
q This is waaaay too many places to look for each path…

38
Summary
q Maze routing has been around a long time …
q Very flexible cost-based search
q Extremely flexible, can be recast to attack many problems
q Zillions of tweaks for speed, space, etc.
q Dominates all modern routers…
• Some of the big chip-level routers use fancy dynamic grids
• Some use rather sophisticated ”gridless” representation of “space”

q Lots of of ancillary problems (and solutions)

q Still routes one net at a time. Early nets block later nets.
q Lots of iterative improvement strategies here (I didn’t talk
about)
q Lots of hierarchy/abstraction (I did talk about Global Routing
a bit)

39
Quiz
q Find the shortest route from S to T on the 6x6 grid

q You can expand 8 directions

S
2 2 2
2 1 2
S 1 2 3
2 2 2
S T
S q Black cells are blockages

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