Roll No.

KIET Group of Institutions

PUE I Examination (2023-2024) Odd Semester

Department: IT/CSE/CSIT/CSE(AI)/CSE(AI-ML)/CS Course: B.Tech

Year: 2nd year Semester: III
Subject Name: Computer Organization & Architecture Subject Code: BCS302
Duration: 3 Hrs Max. Marks: 70
Note: Attempt all the questions of each section
Section-A (10X2=20)
Competitive BL/
Q. No. Question Exam
CO
KC*
a List down the functions performed by an Input/Output unit. 1 1/F
b A digital computer has a common bus system for 8 registers of 16 bit
each. The bus is constructed with multiplexers. Calculate how many & of 1 3/P
what size of MUXs are there in the bus?
1. c Explain bus arbitration. 1 2/C
d Explain IEEE 754 double precision format. 2 2/C
e Explain the concept of restoring in division operation. 2 2/C
f If the content of 4-bit shift registers A is 1100 & of B is 0010 then show
the serial transfer operation of data from A to B such that the contents of 2 3/P
A does not get loose.
g Elaborate different program controls. 3 2/C
h Explain speed up ratio. 3 2/C
i Differentiate between Microprogram and Microinstruction. 3 2/C
j Explain SRAM and DRAM. 4 2/C

Section-B (5X4=20)
Competitive BL/
Q. No. Question Exam
CO
KC*
Express in diagram form a Bus system which uses 3 state buffers and a
2 decoder instead of the multiplexers.
OR 1 2/P
Explain about stack organization used in processors. What do you
understand by register stack?
Convert the decimal no 612.125 & 82.25 to IEEE – 754 single precision
3 floating point representation.
OR 2 2/P
Explain effective address? How is it calculated in different types of
addressing modes?
Draw one stage ALU and explain its components.
4 OR
A binary floating-point number has seven bits for a biased exponent.
The constant used for the bias is 64. Explain the following.
I. List the biased representation of all exponents from -64 to +63. 2 3/P
II. Show that after addition of two biased exponents, it is necessary to
subtract 64 to have a biased exponent’s sum.
III. Show that after subtraction of two biased exponents, it is necessary to
add 64 to have a biased exponent’s difference.
Explain Instruction Cycle and its sub cycle with its diagram with respect to
5 registers.
OR 3 2/C
Differentiate between RISC and CISC.
Explain Memory Hierarchy in detail with diagram.
6 OR 4 4/C
Distinguish between 2D and 2 1/2 D memory organization.
Section-C (5X6=30)
Competitive BL/
Q. No. Question Exam
CO
KC*
 Differentiate between hardwired and micro programmed control in tabular
7 format. Write the sequence of control steps for the following instruction for
single bus architecture. 1 4/P
R1  R2 * (R3)
OR
Explain microprogram sequencer with block diagram also explain its
working.
Show the operation (8) * (-12) using Booth Multiplication Algorithm
8 OR
2 3/P
Derive the procedure of look ahead carry adder by an example and with the
help of block diagram.
Explain the arithmetic statement P = ((X - 𝑌 + 𝑍) ∗ (A ^ B))/(C ^D ∗ E)
9 using general register computer with two address, one address & zero
3 4/P
address instruction format.
OR
Explain the concept of pipelining and its types.
The memory unit of a computer has 256 K words of 32 bit each. The
10 computer has instruction format with 4 fields, an operation code field, a
mode field to specify 1 of 7 addressing modes, a register address field to
specify 1 of 60 processor registers and a memory address. Specify the 3 4/P
instruction format & the no. of bits in each field of the instruction, if the
instruction is in 1 memory word.
OR
Explain the concept of horizontal and Vertical microprogramming.
A computer employs RAM chips of 256 x 8 and ROM chips of 1024 x 8.
11 The computer system needs 2K bytes of RAM, 4K bytes of ROM and 4
interface units, each with 4 registers. A memory mapped configuration is
used. The two highest order bits of the address bus are assigned 00 for
RAM, 01 for of the ROM and 10 for interface registers. Calculate the 4 3/P
following-
(i) Number of RAM and ROM chips needed. (ii) Draw memory address map
for the system. (iii) The address range in hexadecimal for RAM, ROM, and
interface
OR
RAM chip 4096 x 8 bits has two enable lines. Determine the number of pins
are needed for the integrated circuits package. Draw a block diagram and
label all input and outputs of the RAM. Explain the main feature of random-
access memory.

● CO -Course Outcome generally refer to traits, knowledge, skill set that a student attains after completing the course successfully.
● Bloom’s Level (BL) - Bloom’s taxonomy framework is planning and designing of assessment of student’s learning.
*Knowledge Categories (KCs): F-Factual, C-Conceptual, P-Procedural, M-Metacognitive