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1. BCD adder designs based on three-input xor and majority gates
2. High-speed area-efficient vlsi architecture of three-operand binary adder.
3. Single bit fault detecting alu design using reversible gates
4. Modified high speed 32-bit vedic multiplier design and implementation.
5. An analysis of dcm-based true random number generator.
6. Low-power high-accuracy approximate multiplier using approximate highorder
compressors.
7. A low-power yet high-speed configurable adder for approximate computing.
8. Low power 4×4 bit multiplier design using dadda algorithm and optimized full adder.
9. A low-power high-speed accuracy-controllable approximate multiplier design.
10. Performance analysis of parallel prefix adder for datapathvlsi design.
11. Chip design for turbo encoder module for in-vehicle system.
12. Design of efficient bcd adders in quantum-dot cellular automata.
13. Tap delay-and-accumulate cost aware coefficient synthesis algorithm for the design of
area-power efficient fir filters.