Dissertation Peter Seidel SwitchLosses

Power Cycling With Switching Losses
Von der Fakultät für Elektrotechnik und Informationstechnik der Techni-

schen Universität Chemnitz
genehmigte
Dissertation
zur Erlangung des akademischen Grades
Doktor-Ingenieur (Dr.-Ing.)
vorgelegt
von M.Sc. Peter Seidel

geboren am 23.11.1990 in Plauen
Tag der Einreichung: 03.07.2020
Gutachter: Prof. Dr.-Ing. Josef Lutz

Prof. Dr.-Ing. Mark-Matthias Bakran
Tag der Verteidigung: 07.12.2020
Online : https://nbn-resolving.org/urn:nbn:de:bsz:ch1-qucosa2-738670
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gen - steht unter der Creative-Commons-Lizenz
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Bibliografische Beschreibung
Seidel, Peter
Titel: Power Cycling with Switching Losses
Dissertation an der Fakultät für Elektrotechnik der Technischen Universi-

tät Chemnitz, Professur Leistungselektronik, Dissertation, 2021
141 Seiten
98 Abbildungen + 6 Abbildungen im Anhang
3 Tabellen + 1 Tabelle in Anhang
130 Literaturzitate
Referat:
This paper deals with a method to additionally heat with switching losses
in a classical power cycling test, as it is often used for power semicon-
ductors. The fundamentals of testing, switching behaviour, thermal and
electrical characteristics of semiconductors are covered. The core of the
work is the construction, start-up and solution of technical problems dur-
ing the testing of the test stand. Another aspects are the measurement
and software challenges in generating the pulse pattern and in evaluat-
ing the results. The last part of the work deals with the testing of different
types of semiconductors, such as IGBTs and MOSFETs, which were
also made of different materials, such as silicon and silicon carbide, and
had different voltage classes.
Schlagworte:
Power electronics, Semiconductor, Power cycling test, Switching losses,

Silicon carbide
Contents i
Contents
Contents ...................................................................................................................... i
Symbols and Abbreviations...................................................................................... iii
Introduction ................................................................................................................ 1
1. Power Cycling Lifetime..................................................................................... 2
1.1. Power Cycling-induced Ageing Mechanisms and Test Methods ............ 2
1.1.1. Overview of Packaging Technologies and their Wear-out Failures ... 2
1.1.2. Failure Mechanisms in Power Modules and Discrete Devices ........... 6
1.1.3. Basic Structure of a Test Bench for DC Power Cycling Tests ........... 8
1.1.4. Modifications for SiC MOSFET Operation ..................................... 12
1.1.5. Measurement Accuracy, Limits and Consequences for Test Evaluation
……………………………………………………………………...16
1.1.6. Thermal Resistance and Thermal Impedance Spectroscopy ............ 18
1.2. Empirical Power Cycling Lifetime Models........................................... 21
2. Specific Limitations in Conditions for some Devices...................................... 27
3. Approaches of an Application-close Power Cycling Test ............................... 30
4. New Test Bench Concept with an adjustable part of switching losses ............ 35
4.1. Basics for Switching ............................................................................. 35
4.1.1. Active Clamping .............................................................................. 38
4.1.2. Boosted Active Clamping ................................................................ 40
4.2. Repetitive Unclamped Inductive Switching .......................................... 42
4.3. Test Bench Concept for Power Cycling Test with Turn-off Losses ...... 44
4.4. Dimensioning of the Stray Inductance .................................................. 47
4.4.1. Current Ripple and Attainable Switching Losses ............................. 51
4.5. Special Setup for Si and SiC MOSFETs ............................................... 57
4.6. Measurement Algorithm and necessary Hardware................................ 58
4.6.1. Measurement Hardware ................................................................... 58
Contents ii
4.6.2. Measurement Algorithm .................................................................. 60

4.6.3. Challenges during the Measurement................................................ 62
4.6.4. Current Source for Fast Regulation ................................................. 66
5. Test Results with IGBTs ................................................................................. 69
5.1. Modules with Baseplate ....................................................................... 69
5.2. Modules without Baseplate .................................................................. 80
5.3. IGBTs in Discrete Housings ................................................................. 90
6. Test Results with MOSFETs........................................................................... 97
6.1. Low Voltage Si MOSFETs .................................................................. 97
6.2. SiC MOSFETs.................................................................................... 106
7. Analysis of Si Low-voltage MOSFETs Results with FEM ........................... 107
8. Conclusion and Outlook ............................................................................... 113
9. Acknowledgement ........................................................................................ 118
References ............................................................................................................. 119
Appendix ............................................................................................................... 136
Symbols and Abbreviations iii
Symbols and Abbreviations
Indexes
a Ambient
avg Average
b Bond wire
ch Channel
c Case
d Delay, thickness
f Failure, Fall
i Device index
j Junction
m Mean
max Maximum
md Measurement delay
min Minimum
mis mission
n Electron or number
off Turn-off
on Turn-on
s Heat sink, Rise
sw Switching
th Thermal or threshold
C Collector
D Diode or drain
E Emitter
F Forward
G Gate
H Main (Inductance)
L Load
M Measurement or metal
O Oxide
Q Source (Power supply)
Symbols and Abbreviations iv
S Source, semiconductor or blocking

T Transistor (or IGBT)
V Loss
σ Stray (Inductance)
Symbols
α Coffin-Manson exponent or Parameter in lifetime model
β Parameter in lifetime model
γ Parameter for current dependency in lifetime model
ε Permittivity or emissivity
σ Stefan-Boltzmann constant
τ Time constant
c Specific heat or speed of light
d Thickness
f Frequency
k Boltzmann constant
t Time
A Area
B Spectral radiance
C Capacitor
D Bond diameter or Ratio
E Energy
I, i Current
J, j Current density
K Basic power cycling lifetime
L Length
N Number of cycles
P Power
R Resistance
T Temperature
V Voltage
Z Impedance
Symbols and Abbreviations v
Abbreviations
AC Alternating current
BAC Boosted active clamping
DC Direct current
DCB Direct copper bonding
DUT Device under test
EOL End of life
FEM Finite element method
FPGA Field-programmable gate array
HVDC High-voltage direct current
IEEE Institute of electrical and electronics engineers
IGBT Insulated gate bipolar transistor
IR Infrared
MMC Modular multilevel converter
MOSFET Metal oxide semiconductor field effect transistor
RoHS EU Directive 2011/65/EU
SAM Scanning acoustic microscopy
TCP Temperature compensation point
TIM Thermal interface material
TSEP Temperature sensitive electrical parameter
TO Transistor outline
0. Introduction 1
Introduction
Much of the energy consumed in our society comes in the form of electricity,
whereby it is important to use it as efficiently as possible. One of the key
technologies is power electronics, which has experienced strong growth in
the recent decades and will continue to grow in the future through the in-
creased use of renewable energies, such as photovoltaics, and electric mobil-
ity. The greatly changed demands on the grid, such as decentralised power
generation, strong fluctuations due to battery-operated vehicles and regener-
ative feeds, are also leading to increased use of power electronics in energy
transmission and distribution. In many applications, semiconductors are the
most critical component in lifetime considerations, which in turn leads to an
extremely high interest in making the most accurate lifetime predictions pos-
sible. One of the critical points is the aging of the packaging technology due
to thermal-mechanically induced stress in the system. Power cycling tests are
typically used to determine how long a particular component will last under
a selected load.
One of the most criticized points of standard power cycling tests is the fact
that it is not close to the actual application due to no switching losses and no
applied high voltage. Furthermore it is quite complicated to perform mean-
ingful tests for special points of operation and certain semiconductors.
The goal of this work is to show a new concept for power cycling tests, which
has the advantages of the standard power cycling test, such as good measure-
ment accuracy and a reliable temperature sensitive parameter, whereas it is a
lot closer to application due to the applied switching losses. This new ap-
proach allows an additional degree of freedom and the semiconductor is
tested with high voltage and with high frequency switching, which is not the
case for the standard power cycling test.
1. Power Cycling Lifetime 2
1. Power Cycling Lifetime
For the assessment of the lifetime of power semiconductors, there are a num-
ber of test procedures, each focusing on a specific part of the packaging tech-
nology or the die itself, whereby the test of interconnection technology is the
most important part of this work. In order to understand why a new type of
power cycling test has been devised, it is first necessary to break down how
the previous concept is designed.
1.1. Power Cycling-induced Ageing Mechanisms and

Test Methods
In order to understand how the standard power cycling test works, the error
mechanisms in different packages have to be considered first.
1.1.1. Overview of Packaging Technologies and their

Wear-out Failures
The structure of a power module with baseplate is well known and will be
shown here only briefly.
Figure 1: Schematic structure of a power module
As Figure 1 shows, the chip is attached to a copper-clad (DCB) ceramics by

soldering. The DCB is also soldered to the baseplate and the top contact of
the chip is realized by thick aluminium bond wires. There are also other or
improved packaging technologies, such as sintering the chip or copper bond

wires, which drastically change the lifetime of the module. The baseplate can
either be directly cooled with water (or water glycol mix), in which case it is
equipped with structures, or it can be screwed onto a water or air cooler with
a thermal interface material. The typical weak points of this system are the
bond wires and the solder layer of the chip. For very long switch-on times,
the lifetime of the system solder can also be limiting, which is typical for
applications with air cooling. The typical area of application for this module
class is the medium power segment from a few 10 amps to a few thousand
ampere, with reverse voltages of up to around 6500 V are possible. There are
also a number of modules without baseplate. The most common one is the
TO-package.
Figure 2: Transistor outline package [1]
A sketch of the structure of this type of devices is shown in Figure 2. Its

similarity to the construction of a power module is not to be overlooked, as
the ceramics and a base plate are missing. If there is no insulating layer, the
user must provide insulation, which is usually achieved by means of insulated
heat sinks or, as in the power cycling test, an electrically insulating thermal
interface material, such as heat conducting foil. The main cause of error in
this package design is in the bond wires, where a heel crack typically occurs,
although in some cases lift-off may occur, as in the power module. The areas
of application in which TO packages are used are numerous, although in
power electronics they are mostly used for smaller currents and voltages up
to a few 10 amps and up to 1,200 V. The last big group of package design is
the press pack, which today is only used in the high power segment.
Figure 3: Schematic structure of press pack IGBT [2]
Figure 3 shows the structure of an IGBT press pack, including the construc-
tion of a single cassette. Essentially, the design consists of two metal discs
which, together with the ceramic housing, hermetically shield the chips inside
against the environment. A defined pressure has to be applied to ensure good
contact between the cassettes and the housing. The dissipation of the power
loss usually takes place via heat sinks which are mounted on both sides of a
presspack. Usually, a stack assembly is made up of alternating heat sinks and
disc cells, which means that the heat sinks are not potential-free. The main
reason for the ageing of press packs is the thermal expansion of the entire
structure [3], which lead to deformations that occur mainly at the edges.
Figure 4: Deformation of a Press Pack under load (factor: 500) [4]
The consequences, as shown in Figure 4, are poorly or no longer electrically

and thermally contacted chips, which force the others to carry more current
and thus heat up the entire module. As already mentioned, the application of
this design is mostly limited to regions with a very high current carrying ca-
pacity and at the same time an extremely high blocking capability. Currents
in the range from 500 to 10,000 A and simultaneously up to 8,500 V are pos-
sible, whereby blocking voltages greater than 10,000 V are also possible, but
the current carrying capacity is then limited. In this thesis, power modules
and discrete components with currents of less than 250 A and less than 1700 V
are considered, since the effort for, above all, the dielectric strength of the
measurement equipment would otherwise not be reasonably feasible. In this
work a new methodology for power cycling tests shall be described, which
may lead to different failure mechanisms than the standard test, which is the
reason why the next chapter will deal with the different causes of failure.
1.1.2. Failure Mechanisms in Power Modules and Discrete

Devices
As already mentioned in the previous chapter, the modules in standard pack-

aging technology have three main causes of failure [5], which vary depending
on the switch-on time and structure. With very short on-times (less than one
to two seconds), a failure of the bond wires very often occurs, which is typi-
cally due to a lift off of the bond foot from the chip [6], [7], [8]. This behav-
iour is mainly caused by thermomechanical induced stress due to different
thermal expansion coefficients, which in turn lead to crack growth between
bond and aluminium [9], [10]. The metallization made of aluminium can also
age, which mainly leads to restructuring [11], [12], often referred to as recon-
struction, which increases the resistance of this layer [13]. The type and in-
tensity of the degradation occurring are temperature dependent and depend-
ent on the change in temperature [14], [15]. The occurring mechanisms are
largely attributed to creep processes, which are consequently highly depend-
ent on temperature [16]. Formations are emerging that are similar to Hillock
formations [17] but are attributed to grain boundary sliding, plastic defor-
mation through dislocation glide and diffusion creep [18], [19]. Electro mi-
gration could also be a cause of the changes in metallization, but it is gener-
ally believed that it plays no role, or only a minor one, in terms of emitter
vias. However, this behaviour can be counteracted by a passivation layer, alt-
hough it should be noted that a certain area must be kept free for the bonding
process, which can take up to 50% of the metallization area [7], [20]. The
bond interconnection is also directly influenced by the disruption of the met-
allization, although it is not clear to what extent this behaviour has an effect
on the lifetime. Usually, a bond wire lift off occurs for a power module,
whereby the cause is due to crack growth close to the interface between the
wire and the metallization [19], [21]. Over the years, it has been detected that
with a good bond connection, residues of the bond remain on the chip after a
lift off, as can be seen in [22]. Typical for a degradation of the metallization
is a continuous increase of the voltage drop, while in case of bond-wire faults
there are sudden increases. With a strong crack formation within the chip
solder layer, an increase of the voltage drop can also occur, but this happens
only at the end of life, as it is the case with the thermal resistance [23]. Crack
formation can start from the centre or edge of the joint, assuming that the
material and power dissipation density play a role [24], [25]. In order to trig-
ger a fault in the solder layer, the typical switch-on times are 2 - 16 seconds,
but if the device is heated up for a longer time, the soldering of the DCB is
damaged in modules with a base plate [26]. With discrete components, a
crack up to a fracture of the bond wire near the foot usually occurs (heel
crack) and less often bond wire lift off also was also recorded [27], [28].
The next paragraph briefly describes how a test bench is set up for the stand-
ard power cycling test.
1.1.3. Basic Structure of a Test Bench for DC Power Cycling

Tests
In the standard power cycling test, the devices under test are usually perma-
nently switched on. To understand how a power cycling test works a short
simplified sketch is given.
Auxiliary Switch
DUT 1 V
A
DUT 2 V
Low Voltage
Current Source Measurement
current source
DUT n V
Figure 5: Schematic representation of the structure of a power cycling test

bench
Figure 5 shows the structure of a test bench for determining the lifetime of a
test object, whereby the devices under test (DUT) are represented in the pic-
ture as diodes. As already mentioned, the test subjects are not switched ac-
tively, which means that switching losses and switching voltages cannot oc-
cur. A regulated current source is used to adjust the desired load current,
which is the only way to heat the devices by conduction losses. An oversized
IGBT or MOSFET is usually used as an auxiliary switch, which is shown in
the diagram as the ideal switch. This is necessary because the auxiliary switch
should not age due to the current set in the test. The number of DUTs that can
be tested simultaneously, in this case connected in series, depends on the
available voltage of the current source and on the dielectric insolation of the
measuring instrument used. For accuracy reasons, a current measuring device
(usually a current-voltage transformer) is also used. An accurate and often
applied method to determine the temperature in the semiconductor is the
widely known VCE(T)-method [29]. In order to use this physical behaviour of
the pn-junction, a small current is required which does not contribute to the
heating of the component. As a rule of thumb for the level of the measuring
current, about 1/1000 of the nominal load current of the device has proved to
be good. In order to be able to follow the individual behaviour of the DUT in
the test, the voltage drop must be measured individually over each test sub-
ject. In order to be able to deduce the temperature from the voltage drop, each
component must be calibrated in the best case. For this purpose, the compo-
nent is heated on a heating plate and a thermal sensor is placed as closely as
possible to the chip.
There are different control strategies for a power cycling test, while at this
point only the method which is widespread in Europe and meanwhile also
defined by automotive standards [30], is discussed. In this procedure, the time
during which the devices are heated and cooled is determined by the auxiliary
switch. For cooling through the test, a heat exchanger is recommended, since
the ambient temperature usually leads to strong fluctuations around the test
progress and furthermore large power losses can also be poorly dissipated in
limited spaces. Because the VCE(T) method cannot be used in the heating
phase, measurements must be taken as soon as possible after switching off,
which is also a reason for using an auxiliary switch. The measuring delay
time is determined by the auxiliary switch, the amplitude of the switch-off
current and the level of the clamping voltage and it is in the order of several
10 to several 100µs. This test stand concept therefore offers the greatest flex-
ibility, which, however, also has some disadvantages, for example the cooling
time cannot be used additionally and the load current source is also power
cycled by constantly switching on and off. For these reasons, an improved

structure was devised where the current can be alternated into one or more
further phases.
Auxiliary Switch Auxiliary Switch Auxiliary Switch

A Phase 1 Phase 2 Phase 3
Low Voltage Phase 1 Phase 2

Current Source DUT 1 DUT 1 Phase 3
V V DUT 1 V
Cross
regulator Phase 1 Phase 2
DUT 2 DUT 2 Phase 3
V Im 1 V Im 2 DUT 2 V Im 3
Phase 1 Phase 2
DUT n DUT n Phase 3
V V DUT n V
Figure 6: Schematic representation of the structure of a power cycling test

bench with multiple phases
Figure 6 shows the structure of a test stand where the current can be con-
ducted alternately into several phases with the aid of several auxiliary
switches. This concept has several advantages over the single-phase model,
such as the fact that the power source now only has to withstand a few large
load jumps or that the switch-off time of one phase can also be used to heat
another. During the test, the auxiliary switch of the next phase is switched on
after the defined heating time of one phase, so that two switches are switched
on for a short time and the load current begins to split up. This overlap time
is usually set to a few 10 µs to avoid significant cooling in the shutdown
phase. Based on this principle, three phases are usually built up, resulting in
a cooling time twice as long as the switch-on time, under the condition that
the same heating time is used in all phases. The flexibility of the single-phase
construction is not lost, so if required a dummy branch can be built, which
provides additional cooling time. If different types of devices are to be tested,
a different current is often required for the same switch-on time in order to
set the same temperature swing, for example. To achieve this, as shown in
Figure 6, one or more large switches can be installed in parallel to the com-
ponents to be tested, which are then, for example, controlled by the real-time
measuring system as linear controllers and thus form a real-time cross-current
controller. A further advantage of this additional controller is the more pre-
cise adjustability of the current and the fact that the current reaches its static
final value much faster than that which would be the case if the current source
alone took over this task. In this way, almost any device can be tested, only
for MOSFETs, in particular, those made of silicon carbide, the test bench
needs a modified setup. If no gate driver is used as voltage source for the test
object in the power cycling test bench, only the inverse diode can be used for
heating, which can lead to other lifetimes and also does not occur often in the
application. The reasons for and consequences of this fact are discussed in
more detail in chapter 2. In order to test a MOSFET more closely to the ap-
plication, it is heated in forward direction, but must be switched off to meas-
ure the virtual junction temperature, so that the forward voltage of the inverse
diode can be used as a temperature-sensitive parameter [31], [32] . In order
to implement this measurement method, some changes to the test bench are
necessary.
1.1.4. Modifications for SiC MOSFET Operation
In particular, silicon carbide MOSFETs, which have become increasingly us-

able in recent years, require a driver that applies a negative voltage to the gate
during the determination of the virtual junction temperature for a more real-
istic test. As shown already [33], this method is sufficiently accurate, but it is
possible that the specified negative gate voltage of the component is exceeded
to ensure that the channel of the MOSFET is securely closed. At first sight
this seems to lead to a critical violation of the manufacturer's data and thus to
a discrediting of the test, but if the internal structure is taken into account, it
can easily be stated that this is not the case.
Figure 7: Proposed trench SiC MOSFET from Infineon AG with asymmetric

channel [34]
If the semiconductor has to block voltage, it is mainly the n-doped region that
picks up the blocking voltage, and a corresponding electric field is formed.
At the same time, the channel must be closed, which means that a suitable
negative voltage must be applied to the gate. At the corresponding corner of
the gate, see Figure 7, field super elevations occur when the gate voltage is
too high, which causes the gate oxide to age and the gate threshold voltage to
change, thus altering the properties of the semiconductor. For this reason,
most manufacturers of silicon carbide MOSFETs allow a smaller (absolute
value) negative gate voltage than the positive one. In the power cycling test,
however, no reverse voltage is applied, but still a more negative gate voltage
can have an effect on the durability of the gate oxide, which can also be con-
firmed by measurements of the gate threshold voltage before and after a test.
As mentioned above, the gate supply has to be realized now with a switchable
driver whose logic signal must be synchronized with that of the auxiliary
switch. Further functions are the selectable voltage levels of negative or pos-
itive gate voltage and operating voltage within certain limits, as well as a
flexible current monitoring to permit the testing of test module types of dif-
ferent sizes under the same conditions. Further protective functions such as
shown in [35] and [36] can and should be used in conventional gate drivers,
but must be dispensed in order not to limit the effectiveness by false tripping.
A complete schematic can be found in Appendix Figure A. 1. The switching
algorithm to ensure safe operation for the DUTs is shown in the following
diagram.
VGate DUT 1,2...N

15 V
Ton Toff
e.g. 1s e.g. 2s
Time
Tdelay
1-50µs
-8 V
VGate Auxiliary Switch

15 V
Tdelay Tdelay
1-50µs 1-50µs Time
-15 V
Figure 8: Pulse pattern for MOSFET power cycling - load current in

MOSFET mode, sense current in inverse diode mode [37]
As Figure 8 shows, the drivers of the devices under test are switched on and
off with some delay time to the respective auxiliary switch of the phase,
which ensures that these semiconductors do not have to switch off actively
themselves. In addition to the driver, the measuring current source has to be
reversed in polarity, which appears simple at first, but it becomes a problem
when load current flows.
Auxiliary Switch
e.g. IGBT
Protection
Driver 1 DUT 1 Diode
Protection
Diode
+
IMeas
Power So urce +
DUT 2
Driver 2 Protection
Diode
Protection
Diode
Figure 9: Test bench circuit setup for MOSFET mode (according to [38])
As soon as the voltage drop across the devices becomes greater than that
across the internal circuitry of the measurement current source, the current
begins to split, which can lead to destruction of the measurement current
source. To prevent this, as shown in Figure 9, protection diodes are inserted,
enough to make the total voltage drop of the measuring current branch larger
than in the load current path. This passive way offers a simple feasibility and
little effort, but has the disadvantage that the measurement current source has
less voltage available for regulation, which means that fewer semiconductors
can be connected in series to one source. Another possibility is to switch the
measuring current by means of a low-voltage MOSFET. Apart from the fact
that an extra semiconductor and driver has to be used for this, a new logic
signal has to be generated as well, either by the measuring system or by a
logical conjunction of the signals of the auxiliary switches. The main ad-
vantage of this solution is the better usability of the measuring current
sources, since a fast regulating and flexibly adjustable source can be rela-
tively expensive, making this solution more suitable. When selecting the
component, care has to be taken to ensure that switching is fast enough, so
that the measurement is not falsified at the given points in time, which makes
relays unusable, for example.
1.1.5. Measurement Accuracy, Limits and Consequences

for Test Evaluation
The importance of the measurement time points and the measurement periods
for the power cycling test can hardly be overestimated. Usually, measure-
ments are taken at several points in order to be able to record the condition of
the semiconductor as accurately as possible.
ILoad
VCE(ILoad,hot)
VCE(ILoad,cold)
3
2 VCE,
VCE, Iload
Iload
1 4
VCE VCE
TC TC
IMeas Ton
VCE(IMeas)
TJ,max
TC,max
TJ,min
TC,min
Figure 10: Measurement time points and behaviour of semiconductor with

positive temperature coefficient
As Figure 10 shows, there are four measurement points that are important for
the power cycling test: one and two are the points shortly before and after
switching on the load current, and three and four are the points shortly before
and after switching off the phase. The figure shows the behaviour of a device
with a positive temperature coefficient, typical for IGBTs and MOSFETs,
which means that the voltage drop at load current also increases with increas-
ing temperature in the semiconductor. If, on the other hand, measuring cur-
rent flows, the behaviour is reversed, since the pn-junction of the device now
determines the value of the voltage drop, which has a negative temperature
coefficient [39]. At time points one and four, the voltage across the device is
evaluated accordingly and a virtual junction temperature is calculated [40].
Since the losses in the chip are not evenly enclosed and the edges are there-
fore better cooled, a power loss dependent temperature distribution [41] is the
result which the VCE(T) method, due to its averaging function across the chip,
cannot represent, which is the reason why the calculated temperature is called
virtual junction temperature [29]. For easier data processing, the value of the
thermocouple [42] is also recorded at points one and four. It would also be
possible to determine the temperature at time point three, but due to the ther-
mal capacity of the heat sink and the thermocouple there is no relevant change
between the two time points. At time points two and three the voltage drop
of the semiconductor, as well as the respective current of the phase is taken
up, which are later used to detect the power loss in the hot state (PV,hot) and
changes in the forward voltage over time. During phase commutation, the
current is forced to flow from heated devices with a comparatively high volt-
age drop to components which have already cooled down again and therefore
cause less voltage drop. The load current source has to compensate this dif-
ference or load jump and additionally provide the energy which ensures that
the current commutates into the new phase, which, depending on the initial
state, for example current or voltage and size of the source, leads to different
settling times in the range of a few milliseconds. For this reason it can occur
at the given measurement time to over- or undershoot, which is again the
reason why the current is also measured at this point. This behaviour can be
significantly reduced with cross-regulation. The measured power dissipation
is used to calculate the thermal resistance.
1.1.6. Thermal Resistance and Thermal Impedance Spec-

troscopy
The determination of the thermal resistance and the thermal impedance spec-
troscopy is used to make statements about the characteristics of the layers of
the power module.
𝑇𝑇𝑗𝑗,𝑚𝑚𝑚𝑚𝑚𝑚 − 𝑇𝑇𝑠𝑠,ℎ𝑜𝑜𝑜𝑜 (1.1)

𝑅𝑅𝑡𝑡ℎ,𝑗𝑗𝑗𝑗 = [43],
𝑃𝑃𝑉𝑉,ℎ𝑜𝑜𝑜𝑜
Formula (1.1) gives the equation for calculating the thermal resistance, where
Rth,js is the value from the pn-junction to the thermocouple in the heatsink. In
data sheets for power modules, the value up to the case (Rth,jc) is usually
given, but this is not done in many power cycling test benches due to the
much simpler assembly and reusability of the thermocouples. The thermal
resistance is calculated automatically in the test bench and can be used as a
good indicator to see if there is a change in the cooling path. However, this
method reaches its limits if, for example, it is not possible to detect how high
the actual power dissipation was that generated the corresponding tempera-
ture swing. An example of this is when the module has not yet been com-
pletely warmed up and has reached its thermal equilibrium at a given power
loss. This behaviour is the reason why this value often does not reflect the
actual thermal resistance of the module and yet it is necessary to make a clear
statement about the course of the test. With this method, a change in the cool-
ing path can be detected, but it is not possible to determine where a deterio-
ration has mostly occurred. In order to identify the possible position of the
modification, it is necessary to record the complete cooling curve and calcu-
late the transient thermal resistance. If the module is in thermal equilibrium
at a certain power loss, it can be assumed that, under constant cooling condi-
tions, the cooling curve is identical to the heating curve under the constraint
that it is inverted in value.
𝑇𝑇𝐽𝐽 (𝑡𝑡) − 𝑇𝑇𝑠𝑠,ℎ𝑜𝑜𝑜𝑜 (1.2)

𝑍𝑍𝑡𝑡ℎ,𝑗𝑗𝑗𝑗 (𝑡𝑡) = [44], [45]
𝑃𝑃𝑉𝑉,ℎ𝑜𝑜𝑜𝑜
Formula (1.2) shows the calculation of the transient thermal resistance, which
shows that discrete values of the cooling curve of the junction temperature
are used to allow the temporal representation.
0,09
0,08 after 23.000
0,07 cylces
0,06
Zth [K/W]
0,05
0,04
0,03
0,02 after 100
0,01 cylces
0
0,0001 0,001 0,01 0,1 1 10 100
Time [s]
Figure 11: Measured transient thermal resistance at the beginning and at

the end of a power cycling test, ton = 16 s, ΔTj = 100 K, Tvj,max = 150 °C, 550 A
rated SiC-Mosfet in “Econo”- package, water-cooled
The scans in Figure 11 show the difference between 100 and 23,000 cycles,
whereby it is not clearly separable which layer of the structure is involved in
the increase of the thermal resistance and to what extent. If clear statements
are necessary, it is possible to fit the cooling curve with a corresponding ther-
mal model (Foster model [46]) and to determine the time constants and re-
sistances. Under the condition that the component does not age so strongly
that time constants change, the difference of each part can be calculated. The
change in the transient thermal resistance is used as an end of life criterion in
the power cycling test. Usually a rise of more than 20 % of the initial value
of the transient thermal resistance will lead to a failure in order of the device.
The recorded data during the power cycling test for turn-on times, where the
complete device is not heated up, e.g. 30 s, can only give a transient thermal
resistance. When the device then is heated up completely for a ZTH-measure-

ment, it becomes visible that the steady state value of the ZTH (RTH) is already
higher than 20%. A paper by Zeng et al. [47] where different control strate-
gies for the power cycling test were chosen, shows this behaviour in an im-
pressive way. With the test setup explained in chapter 1.1 and the measure-
ment methods mentioned, it is possible to create lifetime models for individ-
ual components or groups of components.
1.2. Empirical Power Cycling Lifetime Models
The aim of an accurate lifetime model is to use the collected data of the power
cycling test to predict the lifetime for certain operating conditions, whereby
the exact operating conditions usually do not lead to a failure in an acceptable
time and therefore cannot be satisfactorily reproduced. For this reason, an
accelerated lifetime test is usually carried out, whereby more or fewer varia-
bles have to be determined depending on the model. If the model can now
predict the lifetime for test points properly, it is used to extrapolate into areas
where application-relevant loads occur for the power semiconductor. In order
to be able to make an accurate statement, not only the model has to fit very
well, but also the results of the power cycling test have to be as exact as pos-
sible. In order to create a model, a physical approach or an empirical approach
can be chosen, while both can only depict reality within the respective limits
of the model.
Most models, which are based on a precise analysis of the physical processes
during the aging of the assembly and joining technique, refer to the slow deg-
radation of solder layers [48]. Precise information about material parameters
and properties of the structure are just as much a prerequisite as precise
knowledge of the physics of failure. Usually in such models stress strain
curves are generated from the deformation and thus the consumption of the
lifetime is calculated. The data required for this is obtained from simulations
or experiments. However, accurate lifetime estimations based on such models
are difficult because the semiconductor and the packaging technology form a
complex system in which electrical, thermal and mechanical components in-
teract strongly and therefore only an extremely complicated model can pro-
vide accurate data. Very complex models are characteristically difficult to
reproduce and therefore require considerable effort for simulation. This can
give rise to very long calculations which is why it is essential and mandatory
to use simplifications. However, this makes it difficult to achieve a high de-
gree of accuracy over the wide range of application.
Empirical results are based on the observations of test engineers and do not
claim to be physically correct. For this reason, the models are usually adapted
to the test data and are therefore only valid in this area. As already mentioned,
however, in accelerated lifetime tests test conditions are chosen which are
usually not application-oriented, which would lead to the fact that the appli-
cation cannot be inferred from the test data. However, the experience in re-
cent decades shows that it is still possible to make limited accurate statements
about the lifetime outside the test points with the most accurate model possi-
ble. CIPS 2008 [49] can be used as a good example of how an empirical
model is structured.
β
β2
β
(1.3)
Tj,min +273
Nf = K ∙ ∆Tj 1 ∙e ∙ t on3 ∙ 𝐼𝐼β4 ∙ 𝑉𝑉 β5 ∙ 𝐷𝐷 β6
This formula for estimating the lifetime of power semiconductors was pre-
sented by Bayerer et al. in 2008. For this model a lot of experimental data
was evaluated and a suitable fit was created, but only modules with base plate
in standard packaging technology (soldered die attach, aluminium bonds)
were used. The model consists of six factors, where each part contains a de-
vice dependent variable and additionally the standard lifetime K is multiplied,
which is also structure dependent. The model is dependent on the following
variables: the temperature deviation delta TJ, the minimum junction temper-
ature TJ,min, the switch-on time ton, the current per bond foot I, the voltage
class of the chip V and the thickness of the bond D. Each parameter of the
equation, except TJ,min, is described by means of a power function with asso-
ciated β, where for optimal results it is necessary to make an adjustment for
each module type. When looking at the individual components, it is noticea-
ble that some parts are already known from other lifetime models or have a
strong similarity to those. The first part with the associated ß and K corre-
sponds exactly to the Coffin-Manson term, which had already been discov-
ered by Coffin [50] and Manson [51] independently of each other more than
60 years ago.
Nf = K ∙ ∆T𝑗𝑗α (1.4)
This simple relationship found between the temperature swing and the life-
time applies to thermal stress, which occurs in substrate solder, but cannot
describe a very complex system such as a power module. The Coffin-Manson
equation was extended by an approach from electrochemistry, the Arrhenius
term [52], [53], which describes the extent to which the absolute temperature
accelerates the ageing of the device.
-EA (1.5)
𝑘𝑘 = 𝐴𝐴 ⋅ e k ∙ T
In the original version, the activation energy EA is used to describe an approx-
imate quantitative temperature dependence of the reaction rate of chemical
processes, where k is the universal gas constant and A is a prefactor. In order
to describe the lifetime of components subjected to a temperature change with
this approach, the Arrhenius approach was used for the first time in the Nor-
ris-Landzberg [54] model.
EA (1.6)
Nf = K ∙ ∆T α ∙ e k ∙ Tmax ∙ f m
For the first time, this model also took into account the frequency f of the
occurring temperature cycles, where k is the Boltzmann constant, and m is
the power factor describing the dependency. Despite the high age of this
equation, it is still used today to describe the lifetime of electronic compo-
nents with SAC solders [55]. The approach of including the frequency of load
changes in the lifetime is obvious and is represented in many modern models,
such as the CIPS 2008, by the ton dependence. Other lifetime models, such as
those published by Scheuermann [6] et al. in 2013, have approaches that are
partly similar, but also completely different.
γ
EA
C + t on (1.7)
Nf = K ∙ ∆Tjα ∙ e k ∙ Tjm ∙ ar (β1 ∙ ∆Tj + β0) ∙ � � ∙ fDiode
C +1
This model also includes the Arrhenius and Coffin-Manson term, but goes its
own way with the remaining factors. In contrast to CIPS 2008, sintered chips
were used here, which is why no ageing of solder layers has to be taken into
account and only 1200V components were tested, so the chip thickness can-
not be considered as an influencing factor. The alloy bond thus remains the
only weak point, but the approach regarding the relationship of the bond wire
is surprising at first sight. Research in relevant literature, however, reveals
that this approach is not new either [56], [9]. This model also confirms a ton
dependency, furthermore the lower lifetime of an equivalent designed diode
with the factor fDiode is taken into account. It is also mentioned that a 1,200V
diode is much thicker than an equally blocking IGBT and therefore this could
be the reason for the reduced lifetime. This model should only be valid for a
certain Semikron power module, which is why no investigations on different
diameters of bond wires have been carried out, although it is known that thin-
ner bonds have a positive effect on the lifetime [57].
Recent publications on transfer moulded devices show clear differences to

other lifetime models, especially with regard to current dependence.
𝐸𝐸A
β γ (1.8)
Nf = K ∙ ∆Tαj ∙ e𝑘𝑘 ∙ Tjm ∙ ton ∙ Ib
The author chooses an approach [58] with significantly fewer parameters than
the above mentioned CIPS 2008 model, but this can be explained by the lim-
ited choice of components, e.g. no semiconductors with a reverse voltage
higher than 1,200V are tested, which explains the missing influence of the
chip thickness. Interesting, however, is the comparison of the influence of the
current per bond on the lifetime, which is significantly greater in the model
shown than in other models. The power factor in this case, with 2.35, is more
than three times higher than the CIPS 2008 model [49]. Further investigations
of the lifetime behaviour of power semiconductors at switch-on times in the
millisecond range reveal astonishing results. Discrete packages with low
power, as well as high power modules, do not show an increase in lifetime
below a certain threshold of the switch-on time, whereby the limit also de-
pends on other parameters of the test [59], [60]. In complete contrast to this
are the investigations in the range of small temperature swings, where there
also seems to be a limit. Hartman et al. [61] formed a model predicting that a
temperature swing of less than 35-15 Kelvin will not cause ageing of the de-
vice, whereby it should be noted that the cut-off line by the Coffin-Manson
term has a strong temperature dependence. However, recent studies show that
this limit may be lower, although it should be noted that there is a strong
component dependence or that other factors may play a role as well [59].
Furthermore, the approach to fit such small temperature swings with the Cof-
fin-Manson equation seems to be not the best solution [62].
However, all models for the aging of power modules have in common that
parameters of the components can only be influenced within certain limits
and are therefore subject to certain limitations, e.g. the fact that higher tem-
perature swings can usually be achieved only with very high currents. After
a more detailed consideration of the lifetime models mentioned in chapter
1.2, it becomes clear that they almost always follow an empirical approach,
which is hardly surprising if the complexity of the ageing mechanisms and
their interactions are contemplated. Based on the approaches of material sci-
ence, there are four possible bases to create a physical lifetime model of a
solder joint [63]. The strain-based approach, which describes the errors that
can occur due to thermal fatigue induced strains in the joints [64] fits most to
the failures that occur during power cycling. In mechanics and materials sci-
ence, a distinction is usually made between high cycle fatigue [65] and low
cycle fatigue [66], since in both areas different failure mechanisms occur and
different observations can be made. From this it can now be concluded, as for
example in the model by Hartmann et al. [61], that an error caused by low
cycle fatigue can be expressed by plastic deformation strain (Δεpl). This
model as well as the others mentioned in chapter 1.2 use the Coffin-Manson
approach to describe at least some parts [67] of the occurring failures mech-
anisms. From these considerations it follows that for very small temperature
swings, elastic deformation (Δεel) has to be the dominant cause of error and
therefore a Basquin based approach [68], [69] has to be used to describe fail-
ures. Recent publications show that the zones overlap in the range of about
20-40K temperature swing [62]. This would be in accordance to the Wöhler
curve of aluminium, because when steel and aluminium are compared, it be-
comes apparent that there is seemingly no point at which aluminium does not
age any longer and therefore does not have an infinite lifetime, in contrast to
steel [70]. In order to describe the total strain, creep processes (Δεcr) have to
be considered, which usually occur above the homologous temperature [71].
𝛥𝛥𝛥𝛥 = 𝛥𝛥𝜀𝜀𝑝𝑝𝑝𝑝 + 𝛥𝛥𝜀𝜀𝑒𝑒𝑒𝑒 + 𝛥𝛥𝜀𝜀𝑐𝑐𝑐𝑐 (1.9)

Most considerations from the point of view of materials science show no re-
sults for repeated creep [72] processes below one second. For this reason,
from the author's point of view, the strain caused by creeping processes can
be neglected for power cycling tests that have a turn on time of less than one
second.
𝛥𝛥𝛥𝛥 = 𝛥𝛥𝜀𝜀𝑝𝑝𝑝𝑝 + 𝛥𝛥𝜀𝜀𝑒𝑒𝑒𝑒 (1.10)
The result is equation (1.10) with the total strain resulting from the elastic
and plastic strain. With the observations from [73] now the following equa-
tion can be established.
−
1
𝑐𝑐2 −𝑎𝑎 (1.11)
Δε = c1 𝑁𝑁𝑓𝑓 𝑏𝑏 + 𝑁𝑁
𝐸𝐸 𝑓𝑓
while Δ𝜀𝜀 ~ Δ𝑇𝑇𝑗𝑗
The variables a, b, c1 and c2 are material dependent constants and Nf the num-
ber of cycles to failure. Due to this correlation, even small temperature swings
should lead to a failure of the bond connection, in a linear dependence similar
to that shown in the Wöhler curves of aluminium.
In order to immediately meet some of these limitations, which are shown in

the following chapter, a new power cycling test bench concept is now being
developed, which generates part of the generated energy from switching
losses.
2. Specific Limitations in Conditions for some Devices 27
2. Specific Limitations in Conditions for some

Devices
In general, there are some limiting conditions for testing power semiconduc-
tors in order to assume that the test can at least remotely reproduce the appli-
cation. A fundamental problem is the interdependence of the test parameters.
To illustrate this, the following example is given: A test with very short
switch-on times is to be carried out to simulate the 50 Hertz ripple of the grid
current. For this purpose, the switch-on time has to be set to 10 milliseconds,
which means that a temperature swing, which in finite time leads to an end
of life, is caused by a current which is significantly above nominal current.
The reason for this behaviour lies in the thermal capacities of the individual
layers of the module structure. If very short times are used to heat up, the
energy is mainly stored in the chip, the die attach and the DCB.
Figure 11 can be used again to illustrate this behaviour: If the Zth value at
time t = 10 ms is used, it becomes clear that it is very small in comparison to
the total Rth, which leads to the fact that correspondingly more energy is nec-
essary to generate a meaningful temperature swing. In the standard power
cycling test, the only way to generate significantly more power dissipation in
the chip is to increase the current, because the gate voltage may only be varied
within certain limits, otherwise semiconductor properties will change in a
way that would never occur in the application. With a suitable design of ex-
periments this behaviour can be counteracted under typical test conditions
and a separation of the parameters becomes possible, but this is not the case
with extreme values such as the one mentioned above due to the reduced de-
grees of freedom. There are also some other aspects which are not covered
by the standard power cycling test and which will be explained in more detail
below.
For IGBTs and diodes, the basic problem is also that with very short turn-on
times, a very large current is required to generate a temperature swing, which
in a finite time leads to a failure. Diodes also lack another degree of freedom:
the gate voltage. In case that large losses are still required, care has to be
taken that the bond connection, which is the main cause of failure with such
loads, is not overstrained. In the power cycling test, the packaging technology
of the module is mainly exposed to loads, but since the component itself does
not have to switch, there are no conditions like in the application. This means
that during the normal test it is not checked whether the component still
blocks voltage and is able to switch on and off.
The behaviour of the IGBTs is similar to that of most MOSFET types,

whereby the inverse diode is used here as a temperature-sensitive parameter,
resulting in more effort during measurement, as described in Chapter 1.1.4.
This leads to the fact that often also the inverse diode is used to heat up the
component, which in the opinion of the author is to be regarded as critical,
since this diode has a negative temperature coefficient, which can lead to a
completely different behaviour than in the MOSFET mode and thus the base-
estimate of the life span in the application becomes even more difficult. Most
MOSFETs with blocking voltages greater than 80 V can be tested just as well
as IGBTs due to their strictly positive temperature coefficient.
Low voltage MOSFETs are generally considered difficult to test, as their low
RDS,on ensures that the forward voltage drop is extremely low even at com-
paratively high package currents. To illustrate this, reference is made to the
data sheet of an IRFP4004, which is delivered in the TO247 package and
allows a nominal current of ~ 200 A, which is only limited by the package.
The limit for the chip itself would be about 350A (room temperature) with
appropriate contacting. This behaviour clearly shows that it is almost impos-
sible to generate enough losses with this MOSFET in a forward direction
without exceeding the current carrying capacity of the bond connection. For
these reasons, the possibility of using the inverse diode to generate enough
losses is often used to qualify a package. There would also be the possibility
to strongly reduce the gate voltage of the device, but the transfer characteris-
tic also has a negative temperature coefficient below the temperature com-
pensation point. Again, reference should be made to the above-mentioned
data sheet to show that this solution should also be regarded as extremely
critical from the author's point of view. To generate enough losses, the gate
voltage has to be set very close to the gate threshold voltage, but the resulting
temperature will cause the channel to open further and the device to generate
fewer losses, resulting in an even more negative temperature coefficient com-
pared to the diode mode. The transfer characteristics provides a more detailed
insight into the behaviour, with a test being performed in chapter 6 and an
FEM simulation in chapter 7.
To avoid some of the limitations, there are some concepts for testing under
application-like or application-close conditions, which will be described in
the next chapter.
3. Approaches of an Application-close Power Cycling Test 30
3. Approaches of an Application-close Power

Cycling Test
The approach of using switching losses to generate power dissipation and

thus a temperature swing is not new and therefore some concepts exist which
are designed for this purpose, but it has to be taken into account that in most
cases a high DC link voltage is used.
Figure 12: Simplified circuit for inverter-like operation [74]
The circuit diagram [74] displayed in Figure 12 shows clear similarity with a
phase inverter and this is what this concept is designed for. To determine the
junction temperature, the voltage drop in the switched-on state is measured
and then the temperature is calculated using a thermal equivalent circuit dia-
gram. Due to the inverter-like operation, the modules are operated similarly
to the application and due to the inductance in the circuit, it would theoreti-
cally also be possible to operate the diodes with switching losses. From the
author's point of view, this way of testing power semiconductors is unsuitable
for the creation of lifetime models for several reasons. First of all, the junction
temperature is not determined with a method that has a high reliability and
accuracy and furthermore, ageing processes, especially solder joints, can only
be detected very poorly and it is not clear to what extent they cause an in-
crease in temperature. The effort for protection and measurement technology
for this circuit is also very high, which together with the reasons mentioned
above leads to the perception that this concept cannot be used.
A further concept, which is quite similar to the first and has also been de-
scribed by other researchers, is a complete H-bridge configuration designed
as a 3-phase or 1-phase inverter, in which an inductance and/or a resistor are
used as load.
Figure 13: Topology of a power cycling test bench for inverter like
operation [75]
With the approach explained in the following, the junction temperature was
not determined by simulation, which in the author's opinion is a much better
approach, but which reveals a number of problems. Just as in the previous

concept and other similar approaches [76], [77], [78], [79], one of the core
problems is again to ensure sufficient safety in operation, as a power cycling
test usually runs 24/7 for a few weeks to months while high DC link voltage
is present. If high power modules with currents in the thousand ampere range
are to be tested with this layout, then inductivity and resistance have to also
withstand these loads, just as the source has to provide this power and the
passive components have to probably be cooled. Another problem, not obvi-
ous at first sight, occurs even when the components are heated up. Most sili-
con devices have the property that with high temperatures and high voltages,
the blocking current increases exponentially, causing the measurement meth-
odology, such as the VCE(T)-method, which is based on using small currents,
to be affected by the reverse current, thereby affecting the virtual junction
temperature measurement. This problem is solved in [75] by means of an OP-
AMP circuit for controlling the measuring current, whereby a measuring ac-
curacy of one percent is given, which from the author's point of view is at
least to be viewed critically, as it is already difficult to achieve this resolution
in the standard power cycling test. Due to the high DC link voltage and the
fact that the VCE(T)-method is used, a comparatively low voltage has to be
measured very accurately in the switched-on state, while it is also necessary
that the high voltage does not cause any damage to the measuring system in
the blocking state.
Figure 14: Circuit for measuring VCE and withstanding high voltages [75]
In order to meet these requirements, a circuit was designed which can be seen
in Figure 14. In this form, the circuit offers protection against high voltages,
since the TVS diodes are limited accordingly, but it is necessary to limit the
current with an upstream resistor. However, it has to be noted that the volt-
age-dependent junction capacitance and the input resistance form an RC ele-
ment which has a corresponding time constant. With the simplification that
the capacitors behave as if they were connected in series and parallel to the
junction capacitance of the diode, the time constant can be calculated,
whereby it has to be noted that only after approximately 3 times tau 95% [80]
of the measured value apply.
0.5 ⋅ 470 pF + 300pF ≅ 500pF (3.1)
τ = R ⋅ C = 360 k ⋅ 0.5 n = 180 µs (3.2)
The capacitance of the diode in equation (3.1) was taken from the data sheet
[81]. The calculation of the time constant results in a value of about 500µs,
which seems acceptable as a measurement delay time. A simulation of the
input circuit, however, reveals a much longer time span until the measured
value is reached, especially if the set point jump is relatively small, which is
mainly due to the growing junction capacitance of the diode [81]. For these
reasons, according to the author, this topology is not suitable for fast and ac-
curate measurements, which is why it is necessary to develop a new concept.
The measuring circuit, however, will be applied in a modified form again in
the new concept, above all because it seems very reasonable to use an insu-
lation amplifier in case the input protection circuit fails.
In order to enable a more realistic operation, there are also test bench concepts
which do not require a high dc-link voltage and thus also make it possible to
determine the junction temperature using the VCE(T)-method.
Figure 15: Inverter-like topology for up to six half bridge-modules [82], [83]
Due to the construction, as shown in Figure 15, up to six half-bridge modules

can be tested at the same time under conditions similar to the application. The
current does not flow from DC+ to DC-, as this can lead to disadvantageous
current distribution, which would have a negative effect on the lifetime of the
modules. The pulse pattern is generated in such a way that IGBTs 1 and 4 of
the respective full bridge are controlled first and then switched on one after
the other. In the second run, switches 3 and 2 are switched on and as soon as
the third device has finished its heating time the procedure starts from the
beginning. Due to the architecture, the switch-off time with full assembly is
five times the switch-on time. Moreover, only one IGBT can be measured per
run because otherwise the measuring current would split up and lead to the
fact that it is possible to determine the junction temperature only every two
full cycles. The fact that no auxiliary switches are used can save costs and the
test is therefore much more realistic, as the semiconductors have to actively
switch off against a stray inductance, which leads to a voltage peak. Due to
the active turn off, the energy of the inductance is converted into heat in the
chip and a small temperature swing occurs.
If this concept is further developed, a variable proportion of switching losses

can be generated with appropriate dimensioning of the stray inductances and
the switching frequency.
4. New Test Bench Concept with an Adjustable Part of Switching Losses 35
4. New Test Bench Concept with an Adjustable

Part of Switching Losses
The new test bench concept adds a variable amount of switching losses to
the DC-losses and it is therefore influenced by the switching behaviour of
the semiconductors.
4.1. Basics for Switching
Non-ideal processes during the process from the blocking in the conductive
state generate so-called switching losses in the semiconductor.
Figure 16: Schematic of the switch-on behaviour of a MOSFET [1]

Figure 16 schematically shows the turn-on behaviour of a MOSFET. Switch-

on losses occur mainly during the times tri and tfv, when high voltage and high
current are simultaneously applied to the device. The gate voltage increases
until the gate threshold voltage is reached. From this point, the current begins
to rise while the full DC link voltage is applied to the device. The curve has
a peak which is caused by the reverse current peak of the previously conduc-
tive freewheeling diode. From the time of the maximum current value, the
gate voltage remains at a level known as the Miller plateau for a certain period
of time. During this time, the voltage drops to the forward voltage and the
current drops to the specified value ID. After that, the gate voltage rises to the
specified value VG and the switch-on process is completed. Similar behaviour
occurs during the switch-off process.
Figure 17: Schematic of the switch-off behaviour of a MOSFET [1]

The gate voltage drops to the level of the Miller plateau. While the gate volt-
age remains at this level, the voltage across the component rises to approxi-
mately the applied voltage. The current then begins to drop to approximately
zero. The increase of the voltage is caused by the di/dt of the turn-off slope
and the switch-on voltage peak of the freewheeling diode. If the turn-off of
an IGBT is considered, the current does not immediately drop to zero. The
tail current phase, which can be up to a few 10µs long, is caused by the clear-
ing of the flooded middle area of the component, whereby the length is
mainly determined by the DC link voltage, but is in principle dependent on
several parameters. At this point high voltage is already applied to the device,
therefore further power dissipation occurs due to the tail current phase. The
overvoltage peak during switch-off can also occur if the commutation induct-
ance is very high and dissipates its energy during freewheeling. If the voltage
level reaches the maximum breakdown voltage of the component, an ava-
lanche breakdown may occur and the component limits the voltage itself. If
switched against an extremely high inductance, the stored energy can cause
thermal destruction of the component. Modern power semiconductors such
as IGBTs and MOSFETs made of silicon or silicon carbide are usually not
damaged by the overvoltage or the avalanche breakdown, only transistors
made of gallium nitride behave differently due to their internal structure.
However, in typical applications, the components and circuits are dimen-
sioned, so that in normal operation there can be no avalanche during blocking.
The information just mentioned leads to the fact that the voltage of the active
components in the new test bench concept must be limited in order to firstly
switch closer to the application, secondly to dispense with additional uncer-
tainties and thirdly only a few components are designed and qualified for re-
petitive avalanche breakdowns. In order to effectively limit the voltage, a cir-
cuit was developed which is called an active clamping stage.
4.1.1. Active Clamping
As already mentioned above, the reverse voltage of the semiconductor may

be exceeded in high-inductance commutation circuits or when switched
against inductances due to the induced voltage.
L
C
TVS-Diode
R1 C
G VCE
R Driver RG E
Figure 18: Basic active clamping circuit
Figure 18 shows the schematic design of a circuit [84], [85] in order to effec-
tively limit the voltage at the semiconductor, which is also required, for ex-
ample, in fault cases where very high currents have to be switched off. The
TVS diode breaks through at a defined reverse voltage, whereby it is also
possible to connect several diodes in series. It than begins to recharge the
gate, whereby the current is determined by the resistors RDriver, RG and R1, as
well as by the characteristics of the gate driver. The additional capacitance
creates a capacitive displacement current and thus enables dv/dt feedback,
which prevents the reverse voltage from overshooting. This principle works
very well to intercept one-time events, or when the time interval between the
clamping is really large. The reason for this is the design of the circuit. Be-
cause while the TVS diode breaks through, several ampere flow while several
hundred volts are applied, which leads to a correspondingly high power dis-
sipation. In order to determine the power dissipation of the diode, a measure-
ment was carried out in which an extremely high inductance was switched to
obtain a correspondingly long clamping “plateau”. As can be seen from the
measurement in Figure A. 2, the clamping time is about 12.5µs and the cur-
rent is about 2.8 A, resulting in a total power loss in the diode during this
switching operation of 17.5 mWs. In the new test bench concept, a high
switching frequency is to be used, which means that considerably smaller
inductances have to be used in order to reduce the clamping time to about one
microsecond. If the measurement performed is used as an example, the en-
ergy per switching operation is reduced to around 1.4 mWs.
1.4 mWs ⋅ 7500Hz (4.1)

⋅ 1𝑠𝑠 ≅ 10.4 𝑊𝑊𝑊𝑊
1000
In the diode, this power dissipation occurs with each switch-off process,
which leads to a considerable power consumption after only one second at
relatively low switching frequencies of 7.5 kHz, as shown in equation (4.1).
A destruction will probably not occur immediately, but it can be assumed that
a permanent operation is not possible. This can be confirmed by measurement
with an infrared camera because the diode reached 120°C at the housing after
one second. These facts show that an improvement of the given circuit is in-
evitable.
4.1.2. Boosted Active Clamping
The new circuit is called boosted active clamping stage and ensures that the
current through the voltage-limiting elements does not become too high.
There are several possibilities to realize such a circuit [86], [87], [88] and it
was decided for a layout according to [89], which also makes it possible to
keep the inductance to the gate low, in order to keep possible electromagnetic
influences by the switching low. The design was created on the basis of a
design already developed by Infineon [90] and its electrical and mechanical
properties were adapted accordingly.
Figure 19: Boosted active clamping circuit [38]
The circuit, displayed in Figure 19, has also been extended by a further out-
put stage in order to further increase the amplification and thus keep the cur-
rent through the TVS diodes as low as possible. The selected circuit is a two-
stage NPN-PNP amplifier stage, whereby in the worst case a gain of hFe=50
[91] has to be calculated for the first pair of bipolar transistors and hFe=80
[92] for the second pair. Together, this still results in a gain of 4,000, which
means that the current from the previous example is reduced from 2.8 A to
700 µA and thus also the power dissipation is reduced. The RC element, in-
serted between the first and second stage, only exists in the latest revision of
the circuit board and serves to reduce oscillations occurring in the gate and
VCE voltage. Theoretically, it would also be possible to allow the device to
enter the avalanche breakdown and thereby limit the voltage and thus dissi-
pate the inductance energy, but only a few semiconductors are specified to
withstand this load repeatedly. In the case of low voltage MOSFETs espe-
cially, which will be highlighted in this thesis, there are some applications
which are dependent on the repeated insertion of large amounts of energy into
the components, which is called repetitive unclamped inductive switching.
4.2. Repetitive Unclamped Inductive Switching
A good example of unclamped inductive switching in an application is the

anti-blocking system in vehicles [93]. The MOSFET is used as a low side
switch and connects the pump of the brake circuit to the battery, while each
time the pump is switched on by the device, energy is stored in the inductor.
Each time the pump is switched off or the pressure control system is acti-
vated, the energy of the inductance is dissipated via the semiconductor, which
is driven into the breakdown. The energy brought in is low, resulting in a
lifetime of more than 50 million cycles [94]. In scientific studies on the topic
of unclamped inductive switching, significantly more energy is usually used
to make statements about ageing and the mechanisms that led to failure. Ear-
lier components often show changes in the chip characteristics, which no
longer occur thanks to better design [95], [96]. Modern components usually
only show changes in the RDS,ON, which are very probably due to aging in
packaging technology [97], [98]. It can therefore be assumed that there will
be no significant ageing as a result of switch-off loads with low energies. In
order to reproduce the application as well as possible, it is of interest to know
the ratios of switching losses to forward losses during the power cycling test.
For 1.2kV SiC-MOSFETs some degradation can be found [99], when the ap-
plied energy for the pulse is very high. Nevertheless this has to be considered
when testing these devices, especially when the test is with superimposed
switching losses. Low-voltage MOSFETs have a wide range of applications
in the automotive industry, for example ABS systems, or on computer main-
boards as voltage regulators. In most cases, however, the switching losses are
decisive, since the RDS,on of the components is very small and therefore sig-
nificant transmission losses only arise at very high currents. Components
with a higher blocking voltage are, for example, used in switching power
supplies and switched with some 100 kHz, which means that the proportion
of switching losses is dominant. Depending on the switching topology and
structure used in the specific application, the proportion of switching to for-
ward losses is approximately in the ratio of 1:1 to 2:1 [100]. IGBTs are still
used today in almost all inverter applications, whereby topology, such as 2-
level or 3-level inverters, is just as important here as the switching frequency
used for the power dissipation ratio [101]. Higher switching frequencies typ-
ically lead to more losses, but the filter can usually be reduced or the quality
of the output voltage or output current is improved. In IGBT applications in
the high current and voltage range, such as PV converters, HVDC converters
and rail converters, switching losses can reach the level of the forward losses,
but this is usually not the case [102]. In some older HVDC applications (en-
ergy transmission and distribution), higher switching frequencies are also
used, which leads to correspondingly high losses [103]. Today modern mul-
tilevel converter for high voltage applications use a very low switching fre-
quency for each switch and therefore the consequential losses are very low.
The basics for a power cycling test bench concept, which generates a part of
the energy for heating by switch-off losses as well as suitable ratio losses, are
now given, so that in the following chapters the structure, the function and
the measuring method will be explained in detail.
4.3. Test Bench Concept for Power Cycling Test with

Turn-off Losses
The new test bench is designed to test with switching losses, but without us-
ing a high DC link voltage, whereby an accurate measurement should not be
dispensed with. The basis for this is the switching against a high inductive
load, which generates an overvoltage when its energy is dissipated. This is
considerably greater than the voltage of the load current source and leads to
switch-off losses in the semiconductor.
Phase 2
Same biuld as Phase 1
Aux.-Switch Phas e 2
Aux.-Switch Phas e 1
Blocking Diode 1 Blocking Diode 1
LMain
Lσ Lσ
Measurement
PH1 Current PH1 Measurement
Current
DUT 1 Source 1 DUT 2 Source 2
Gatedriver Gatedriver
+ +
Low Voltage
clamping clamping
Current Source
PH1 Measurement
Current
DUT 3 Source 3
Gatedriver
Figure 20: Basic schematic representation of the new test bench design
As Figure 20 shows, some components from the standard load alternation test
can also be detected here, such as load or measurement current sources and
auxiliary switches, while some new parts have also been added. Their func-
tions will be explained later. From the schematic, it also becomes clear that
not every semiconductor is suitable for testing with switching losses because
it has to be able to switch off actively, which thyristor and diode are not ca-
pable of. Furthermore, the number of simultaneously testable semiconductors
per phase is limited to two switched and one permanently switched-on device.
This becomes clearer when the mode of operation is presented. The second
phase of the test bench is identical in construction to the first, whereby it
would also be possible to add a third or fourth phase, but this has not yet been
realized due to the high expenditure, the lack of transparency and space. Fur-
thermore, a heat exchanger, which keeps the coolant temperature constant,
thermocouples for recording the temperature near the base plate and a meas-
uring system for data acquisition are necessary for the operation of the test
stand. These components, as well as a personal computer for control, are nec-
essary to operate any power cycling test bench and are therefore not included
in the diagram in order reduce complexity.
The basic idea behind the function of the test bench is relatively simple: it is
switched with high frequency against the stray inductances Lσ repeatedly in
order to obtain a corresponding switch-off pulse, as already described.
Blocking Blocking Blocking Blocking

Diode 1 Diode 2 Diode 1 Diode 2
LMain LMain
Lσ Lσ Lσ Lσ
PH1 PH1 PH1 PH1
DUT 1 DUT 2 DUT 1 DUT 2
Lo w Voltage Lo w Voltage
Current So urce PH1 Current So urce PH1
DUT 3 DUT 3
Figure 21: Simplified schematic of the test bench concept with current paths
Consequently, there are two possible paths for the current to flow in, namely
PH1_DUT1 and PH1_DUT3 as well as PH1_DUT2 and PH1_DUT3, as Fig-
ure 21 shows, where the paths are marked in red. Furthermore, it can be in-
ferred that the third device under test of the respective phase has no or only a
very low stray inductance and is permanently switched on. This leads to no
switching losses and therefore it behaves like a device in the standard power
cycling test, from which, in turn, it can be concluded that this semiconductor
can be used as a reference. During the switch-on time of the respective phase,
which is, for example, one second, the current is alternatingly switched be-
tween the legs, each consisting of the device under test, a diode and the leak-
age inductance, with a selectable switching frequency. The main inductance
LMain serves as energy storage for the commutation processes within the re-
spective phase and between the phases, as well as for smoothing the current.
The energy that is implanted into the switch when it is turned off is deter-
mined directly by the size of the leakage inductance, which means that in the
best case it is designed individually for each semiconductor. The software
and the FPGA allow almost all influencing parameters, such as switching fre-
quency, overlap time of the phases and within the phase, duty cycle within
the phase, switch-on time of the phase and measurement time, to be set indi-
vidually. In practice, however, it has proved to be advantageous to make the
inductance smaller than it has to be in order to have enough room for ma-
noeuvre in the test conditions, since there is a quadratic dependence of the
current for the energy. This results in a new degree of freedom due to the
switch-off losses, which can be used, for example, to test the current depend-
ence of a model. Another advantage is that low voltage MOSFETs can now
be tested in the forward direction, as well as in the application, and it is also
possible to reproduce conditions in the application and perform detailed
measurements. Due to the small thermal resistance at very short switch-on
times or when very high temperature strokes are required, a lot of current is
required to reach the test conditions, which can lead to earlier failure of bond
wires, for example, as these are exposed to extremely high stress. With the
new test bench design it is possible to realize such test conditions without any
problems, without exceeding the specified limit values. The following chap-
ter deals with the dimensioning of stray inductances, since they also play a
decisive role in achieving the test conditions.
4.4. Dimensioning of the Stray Inductance
The leakage inductance Lσ is primarily used to generate the required switch-

ing losses because almost 100% of the energy stored in the inductor is con-
verted into heat in the semiconductor during switch-off. A very small part is
required for the control of the boosted active clamping circuit and it is con-
ceivable that the blocking diodes, due to high currents which have previously
flowed and thus lead to high temperatures, dissipate a part of the energy as
leakage current in the reverse direction.
1 (4.2)
𝐸𝐸 = ⋅ 𝐿𝐿 ⋅ 𝐼𝐼²
2
In a usual application the source voltage is about the same as in the DC-link
capacitor and therefore delivers additional energy during turn-off [1]. In this
test bench a low voltage source is used, so that the turn-off voltage is about
ten times higher. The formula can therefore be simplified to the given equa-
tion (4.2) and it is used for calculating the energy of an inductance and will
also describe the energy dissipated in the semiconductor during turn off.
Figure 22: Switching losses, 25 A, 1200 V, IGBT (part of datasheet [104])
Figure 22 shows the turn-on and turn-off losses of a FS25R12W1T4 IGBT

under given switching conditions, whereby it should be noted that almost no
turn-on losses occur with the selected test bench concept, as there is no high
DC link voltage and no free-wheeling diode can generate a reverse voltage
peak. For this reason, the size of the leakage inductance is selected in such a
way that the sum of the switch-on and switch-off energies is generated during
each switch-off process, which will be approximately 3.3 to 5.1 mJ for the
given example. Since the semiconductor is specified by the manufacturer for
this energy, it is ensured that this load will not lead to any unusual or special
fault mechanisms, as is the case, for example, in the short circuit, where large
amounts of power are dissipated in a very short time. Nevertheless, a small
rise in temperature is generated by the energy during each switching opera-
tion, which, if it reaches a certain magnitude, has to be considered during
lifetime investigations as well. During normal switching operations, this
takes less than a microsecond to switch on and off. From this it can be con-
cluded that all the energy is stored in the thermal capacity of the chip, making
it easy to calculate a temperature swing with the physical dimensions of the
semiconductor.
𝐸𝐸 𝐸𝐸
Δ𝑇𝑇𝑗𝑗 = =
𝐶𝐶𝑡𝑡ℎ ⋅ 𝑑𝑑 ⋅ 𝐴𝐴 ϱ ⋅ 𝑐𝑐𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 ⋅ 𝑑𝑑 ⋅ 𝐴𝐴 (4.3)
5 𝑚𝑚𝑚𝑚
=
𝑔𝑔 𝐽𝐽
2.34 ⋅ 703 ⋅ (0.115 ⋅ 27.2) 𝑚𝑚𝑚𝑚3
𝑐𝑐𝑚𝑚3 𝑘𝑘𝑘𝑘 ⋅ 𝐾𝐾
= 0,97 𝐾𝐾
As the calculation shows, the rise is below one Kelvin, even with the highest
switching energy, from which it can be concluded that no consideration of
this temperature swing has to take place. During dimensioning, the structure
of the test stand has to be taken into account as well, which ensures that the
values of the leakage inductances add up.
Overlapping process from PH1_DUT1 to PH1_DUT2

120,00 30,00
100,00
IC Ph1_Dut1 25,00
80,00 IC Ph1_Dut2 20,00
Current [A]
Voltage[V]
60,00 15,00
40,00 10,00
20,00 VCe Ph1_Dut1 5,00
0,00 0,00
0 2 4 6 8 10
Time [µs]
Figure 23: Current overlapping process with Lσ1=5pH and Lσ2=5µH
To demonstrate this behaviour, a very small value was selected for one of the
stray inductances in a simulation with LTspice and yet a high switching volt-
age is generated, as shown in Figure 23. If relevant literature is consulted, it
is easy to see that a similar behaviour occurs with every commutation process
in inverters [105]. The reason for the different current levels lies in the over-
lapping process itself, which is not completely illustrated, because for safety
reasons both active switches are switched on for a defined time, which is
usually 10-30 µs, resulting in a part of the current flowing in PH1_DUT2 al-
ready at time zero of the diagram. Furthermore, this prevents the main induct-
ance from freewheeling over the devices if, for whatever reason, there are
delays when switching on or premature switching off, which could otherwise
lead to damage. When a device is switched off, the associated inductance acts
as a voltage source because the current changes, and at the same time the
current of the main inductance also changes. This induces a voltage, which
causes these voltages to add up, but at the same time are limited to the break-
down voltage of the TVS diodes on the BAC board. In contrast to the inverter,
the additional energy required to switch on the other leg of the phase is sup-
plied by the main inductance, which leads firstly to an increase of the energy
requirement with higher switching frequencies and secondly to a current rip-
ple in inductance resulting from the switching and thus also in the perma-
nently switched on third device of each phase. In order to see, if the assump-
tion made for equation (4.2) is correct, the energy dissipated to the semicon-
ductor can be calculated from the simulation using the following equation.
𝑡𝑡=10µ𝑠𝑠 (4.4)
𝐸𝐸 = � 𝑈𝑈 ⋅ 𝐼𝐼 ⋅ 𝑑𝑑𝑑𝑑
𝑡𝑡=0µ𝑠𝑠
The result for equation (4.2) is 1.564 mJ, where equation (4.4) resulting in
2.015 mJ. The difference can be explained by the already given explanation
for the simplification. Because the switching voltage is, with 120 V, only
about three times higher than the source voltage resulting is a bigger error
using the equation (4.2). The dimensioning of the leakage inductances thus
also has an influence on the adjustment possibilities of the test conditions,
which makes a theoretical consideration meaningful.
4.4.1. Current Ripple and Attainable Switching Losses
Due to the commutation process of the current, a ripple will occur in the main
current in the stationary state. The following equations are written down ac-
cording to [106].
IMAX
∆Is
I0
ts
tf
Figure 24: Schematic illustration of the current ripple in the main inductance
LH [106]
As Figure 24 shows, it can be assumed that the current will rise during turn-
on time ts and fall during the turn-off time tf, resulting in the current remaining
within the limits IMAX and I0. A part of the energy is converted into switching
losses, whereby the resulting current ripple ΔIS is influenced by the source
voltage VQ, the inductivities (LH, Lσ) and the period length (ts+tf) of the
switching frequency of the device.
𝑉𝑉𝑄𝑄 𝑉𝑉𝑄𝑄 (4.5)

∆𝐼𝐼𝑠𝑠 = ⋅ 𝑡𝑡 = ⋅ 𝑡𝑡𝑠𝑠
𝐿𝐿𝐻𝐻 + 𝐿𝐿σ 𝑠𝑠 𝐿𝐿
𝐿𝐿𝐻𝐻 ⋅ (1 + 𝜎𝜎 )
𝐿𝐿𝐻𝐻
During the current fall time tf, the current of a device under test falls to zero
and it is determined by the ratio of the two leakage inductances to the main
inductance, as the following equation shows:
𝑑𝑑𝑑𝑑𝑓𝑓 𝑑𝑑𝑑𝑑𝑓𝑓 (4.6)

⋅ 𝐿𝐿σ1 + ⋅ 𝐿𝐿
∆𝐼𝐼𝑓𝑓 = 𝑑𝑑𝑑𝑑 𝑑𝑑𝑑𝑑 σ2 ⋅ 𝑡𝑡 .
𝑓𝑓
𝐿𝐿𝐻𝐻
As already described above, the entire system behaves during the commuta-
tion time as if against both stray inductances are switched off, which means
that the individual values no longer play a role and can thus be simplified. It
can therefore be assumed that each inductance represents exactly half of the
total commutation inductance, which allows the following simplification to
be used:
𝐿𝐿𝜎𝜎1 = 𝐿𝐿𝜎𝜎2 = 𝐿𝐿𝜎𝜎 . (4.7)
This results in the following equation:
𝑑𝑑𝑑𝑑𝑓𝑓 (4.8)
2⋅ ⋅ 𝐿𝐿
∆𝐼𝐼𝑓𝑓 = 𝑑𝑑𝑑𝑑 σ ⋅ 𝑡𝑡 .
𝑓𝑓
𝐿𝐿𝐻𝐻
The time it takes for the current to fall (tf) is determined by the maximum
current IMAX and the change in current during switch-off dif/dt:
𝐼𝐼𝑀𝑀𝑀𝑀𝑀𝑀 𝐼𝐼0 + Δ𝐼𝐼𝑠𝑠 (4.9)

𝑡𝑡𝑓𝑓 = = .
𝑑𝑑𝑑𝑑𝑓𝑓 𝑑𝑑𝑑𝑑𝑓𝑓
𝑑𝑑𝑑𝑑 𝑑𝑑𝑑𝑑
If the current in the main inductance has reached a steady state, it can be
assumed that the absolute value of the rising current (ΔIs) is equal to that of
the falling current (ΔIf):
Δ𝐼𝐼𝑠𝑠 = Δ𝐼𝐼𝑓𝑓 . (4.10)

If now (4.8) and (4.6) are used, the following equation results:
𝑑𝑑𝑑𝑑𝑓𝑓 (4.11)
𝑉𝑉𝑄𝑄 2⋅ ⋅ 𝐿𝐿
⋅ 𝑡𝑡𝑠𝑠 = 𝑑𝑑𝑡𝑡 𝜎𝜎 ⋅ 𝐼𝐼0 + Δ𝐼𝐼𝑠𝑠 .
𝐿𝐿𝐿𝐿 𝐿𝐿𝐻𝐻 𝑑𝑑𝑑𝑑𝑓𝑓
𝐿𝐿𝐻𝐻 ⋅ (1 + )
𝐿𝐿𝐻𝐻 𝑑𝑑𝑑𝑑
Solve after I0:
𝑉𝑉𝑄𝑄 (4.12)
𝐼𝐼0 = ⋅ 𝑡𝑡𝑠𝑠 − Δ𝐼𝐼𝑠𝑠 .
𝐿𝐿
2 ⋅ 𝐿𝐿𝜎𝜎 ⋅ (1 + 𝜎𝜎 )
𝐿𝐿𝐻𝐻
Insert of ΔIs:
𝑉𝑉𝑄𝑄 𝑉𝑉𝑄𝑄 (4.13)

𝐼𝐼0 = ⋅ 𝑡𝑡𝑠𝑠 − ⋅ 𝑡𝑡𝑠𝑠 .
𝐿𝐿 𝐿𝐿
2 ⋅ 𝐿𝐿𝜎𝜎 ⋅ (1 + 𝜎𝜎 ) 𝐿𝐿𝑀𝑀 ⋅ �1 + 𝜎𝜎 �
𝐿𝐿𝐻𝐻 𝐿𝐿𝐻𝐻
Simplify:
2 ⋅ 𝐿𝐿𝜎𝜎 (4.14)
𝐿𝐿𝐻𝐻 (1 − )
𝐿𝐿𝐻𝐻
𝐼𝐼0 = 𝑉𝑉𝑄𝑄 ⋅ 𝑡𝑡𝑠𝑠
𝐿𝐿
𝐿𝐿𝐻𝐻 ⋅ 2 ⋅ 𝐿𝐿𝜎𝜎 ⋅ (1 + 𝜎𝜎 )
𝐿𝐿𝐻𝐻
On condition that the main inductance LH is considerably greater than the

leakage inductances Lσ, the following simplification can be made:
𝐿𝐿𝜎𝜎 (4.15)
≈0.
𝐿𝐿𝐻𝐻
Thus I0 can be simplified as follows:
1 (4.16)
𝐼𝐼0 = 𝑉𝑉𝑄𝑄 ⋅ 𝑡𝑡𝑠𝑠 .
2 ⋅ 𝐿𝐿𝜎𝜎
It follows:
Δ𝐼𝐼𝑠𝑠 → 0 . (4.17)
The following example illustrates the behaviour well:
ts = 33.3 µs (f = 15 kHz), LMain = 1 mH, Lσ = 7 µH und VQ = 15 V.
15 𝑉𝑉 (4.18)
Δ𝐼𝐼𝑠𝑠 = ⋅ 33.3 µ𝑠𝑠 ≈ 0.497 𝐴𝐴
1.007 𝑚𝑚𝑚𝑚
𝑡𝑡𝑠𝑠 ⋅ 𝑉𝑉𝑄𝑄 33.3 µ𝑠𝑠 ⋅ 15 𝑉𝑉 (4.19)

𝐼𝐼𝑚𝑚𝑚𝑚𝑚𝑚 ≈ 𝐼𝐼0 = = ≈ 35.71 𝐴𝐴
2 ⋅ 𝐿𝐿𝜎𝜎 2 ⋅ 7 µ𝐻𝐻
As the example shows, the 0.5 A ripple is small compared to the 35.7 A and
can therefore be neglected. This calculation was also shown in [82].
If the equations (4.8) and (4.16) are considered, it becomes quite clear that
the ratio between the ripple current and the maximum current are defined by
the ratio of the inductances, by a given switching frequency and source volt-
age.
𝐿𝐿𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀 (4.20)
Δ𝐼𝐼𝑠𝑠 = 𝐼𝐼𝑚𝑚𝑚𝑚𝑚𝑚 ⋅
2 ⋅ 𝐿𝐿𝜎𝜎
This behaviour leads to the fact that the high-frequency ripple current can no
longer be neglected above a certain level of stray inductance.
The achievable switching losses can now be calculated for a given source
voltage stray inductance.
2 ⋅ 𝐿𝐿𝜎𝜎 ⋅ 𝐼𝐼𝑀𝑀𝑀𝑀𝑀𝑀 ² 𝑉𝑉𝑄𝑄 ² ⋅ 𝑡𝑡𝑠𝑠 2 (4.21)

𝐸𝐸𝑂𝑂𝑂𝑂𝑂𝑂,𝑀𝑀𝑀𝑀𝑀𝑀 = =
2 4 ⋅ 𝐿𝐿𝜎𝜎
For the example selected above, this results in EOFF, Max = 35.71 mJ.
From (4.21) the achievable switching losses can be calculated as a function

of the switching frequency at a given voltage.
1200 V
600 V
1700 V
SiC
Figure 25: Switching losses as a function of switching frequency and stray

inductance, from [38]
Figure 25 shows which operating conditions must be set, so that the level of
switching losses PSW corresponds to the level of conduction losses PDC. Each
point corresponds to a module, whereby the calculation is based on the values
from the Infineon simulation tool IPOSIM [107]. For the calculation, nominal
current and forward voltage drop at nominal current were used for the DC
power dissipation and then the necessary switching frequency was deter-
mined using the switching losses. If the achievable switching losses for vari-
ous inductances are plotted using the 15 V source voltage given in this case,
it can be seen at which inductance the operating point can be reached at all or
whether a higher source voltage is required if necessary or the switching fre-
quency must be increased. Three groups (600, 1200 and 1700 V) are formed,
which are defined by the blocking voltage of the components because the
switching losses also increase with increasing blocking voltage. Furthermore,
two 1200 V SiC-MOSFETs were also included as an example. In order to test
MOSFETs and SiC-MOSFETs as well, some modifications have to be made,
as already described in chapter 1.1.4.
4.5. Special Setup for Si and SiC MOSFETs
The passive solution with diodes is out of the question for the protection of
the measuring current sources, since several hundred volts can be applied
during switching operation, with which several tens of diodes would have to
be used. This is absolutely impractical. Furthermore, the source should also
be able to supply a correspondingly high voltage. This is not the case, which
leads to the solution to switch the measuring current with the use of an extra
semiconductor.
Auxiliary Switch Auxiliary Switch

e.g. IGBT for meas uring
current
+ Driver 1 DUT 1
Driver
Power Source
IMeas
+
Figure 26: Power cycling circuit for test in MOSFET mode with a switch for
measurement current source protection
As Figure 26 shows, an IGBT is used in the test bench to switch the measur-
ing current, although in principle any semiconductor that switches fast
enough and has the necessary blocking voltage could be used. The disad-
vantage of this method, however, is that an additional driver is required for
each component, which increases the probability of the overall system failure,
and also another signal has to be generated by the measurement system,
which can lead to an additional digital output module necessary to be used.
Just like the measuring current sources, the measuring system has to be pro-
tected against high voltages as well, which will be discussed in the next chap-
ter.
4.6. Measurement Algorithm and necessary Hard-

ware
Before explaining in which way and at what time measured values are deter-
mined, it is necessary to take a look at the hardware that significantly con-
tributes to the quality of the result.
4.6.1. Measurement Hardware
The measuring system has a maximum input voltage of ±10 V, and can isolate
40V from the analogue ground, which is the reason why the analogue isola-
tion must be increased, since voltages up to 1200 V can occur. In order to
implement this project, an investigation on the subject of "isolation amplifi-
ers" was carried out in advance [108], which came to the conclusion that the
"AD215" from “Analog Devices” [109]was the best of the tested products,
whereby it should be mentioned that the requirements are very high and there-
fore only a few components fulfilled them. However, this component must
also be protected from excessively high voltages, as the circuit increases the
insulation, but the maximum input voltage is still ±10 V, which is why a pro-
tective circuit was developed. In earlier tests [83], this component proved to
be very robust, but the circuit is not transferable, since high voltages only
occur for a very short time. The main challenge in producing the circuit board
is the high demand on dielectric strength, whereby amplitudes in the range of
100-600 mV have to be measured very precisely shortly after an overvoltage.
In addition, the frequency response has to be correspondingly short and no
temperature drift is allowed to occur, which is a major problem, since the
repeated voltage loads also generate heat in the resistors.
Figure 27: Circuitry of the analogue amplifier board [38]
Figure 27 is showing the important parts of the PCB, while the complete cir-
cuit diagram can be seen in appendix Figure A. 3 and an image of the board
in appendix Figure A. 4. The protection of the measuring system was realized
by the resistors R1 - R10 and the TVS diodes D1, D3 - D6, which derive the
overvoltage according to ± 15 V. When dimensioning the resistors, on the
one hand the power dissipation has to be taken into account, on the other hand
the resistors should not be set too high, because the junction capacitance of
the TVS diodes and the resistance value form an RC-element with a corre-
sponding time constant. The following calculation was used for the thermal
dimensioning: Switching frequency: 250 kHz, VCE(DS), Max: 1200 V, Clamping
time: One µs.
1 1 (4.22)
𝑡𝑡 = = = 4 µ𝑠𝑠
𝑓𝑓 250 𝑘𝑘𝑘𝑘𝑘𝑘
This results in a duty cycle of 1/4, which means that a voltage of 1200 V is
applied during 1/4 of the time of high-frequency switching, so that it must be
assumed for the calculation that the total voltage across the resistors drops,
which at the same time reflects the worst case.
𝑈𝑈 ⋅ 𝑈𝑈 1200 𝑉𝑉 ⋅ 1200 𝑉𝑉 1 (4.23)

𝑃𝑃 = ⋅ 𝐷𝐷 = ⋅ = 36 𝑊𝑊
𝑅𝑅 10 𝑘𝑘Ω 4
As can be seen from formula (4.23), in the worst case a power dissipation of
36W, or considerably more if the voltage is increased, can occur, which
means that the circuit must be actively cooled. Despite the active cooling and
the fact that the power dissipation is divided between ten resistors, high-per-
formance resistors have to be used, here in the TO247 housing with a maxi-
mum rated power dissipation of ten watts per unit, which also has to have an
insulation capability.
In order to obtain the measured values as quickly as possible after a clamping

process, a double diode (D1) of type BAV199 with ultra-short blocking re-
covery time is used, which is additionally biased by resistors R12 and R13.
As already mentioned, the isolation amplifier is an AD215BY with a cut-off
frequency of 120 kHz (3 dB), which is completely sufficient for determining
the measured values, since during high-frequency operation a measurement
with high quality due to electromagnetic interference does not appear to be
reasonable. The potentiometer can be used to change the limit frequency,
which is in the range of megahertz, which serves to suppress the interference
generated by the isolation amplifier itself. The remaining circuit serves to
generate a supply voltage with the least possible noise, whereby care has been
taken to keep the coupling capacitance of the DCDC converters as low as
possible in order to enable measurement at high potential if required. In order
not to have to consider the already mentioned cut-off frequency of the circuit
and to obtain a result as accurate as possible similar to the procedure of the
standard power cycling test, a special pulse pattern for measuring was also
developed.
4.6.2. Measurement Algorithm
As already mentioned in chapter 4.3, high-frequency switching within one

phase is used to heat the components, but this means that the virtual junction
temperature is not measured during this time because, firstly, the electronic
magnetic interference is too great and, secondly, depending on the switching
frequency, the dynamics of the isolation amplification and the sampling rate
of the measuring system are insufficient. In order to counteract this problem,
a selectable measuring time was defined between the heating periods of the
phases, in which the components can be electrically measured as in the stand-
ard power cycling test bench.
Overlapping process Overlapping process

phase 2 - phase 1 phase 1 - phase 2
high frequency meas. ph.2 Vce(hot) meas. ph.2 Tjmax meas. ph.1 Vce(hot) meas. ph.1 Tjmax
operation phase 2 meas. ph.1 Tjmin meas. ph.1 Vce(cold) high frequency meas. ph.2 Tjmin meas. ph.2 Vce(cold) high frequency
(e.g. 2 s) operation phase 1 operation phase 2
(e.g. 2 s) (e.g. 2 s)
500µs 500µs 500µs 500µs
Voltage
Vce(cold) Vce(hot)
UPH1-DUT1
Tjmin Tjmax
UPH1-DUT2
ILoad
Current
IPH1-DUT1
IMeas
IPH1-DUT2
Figure 28: Pulse pattern for high frequency operation and measurement
Figure 28 shows the quality characteristics of the voltage and current of a

phase, highlighting that in order to improve the representation, the amplitudes
should be neglected. The measuring system has to output a corresponding
pulse sequence which ensures that the measurement corresponds to this form.
The greatest challenge here is the simultaneous evaluation of different meas-
ured values in different phases, since, as the figure shows, during the overlap
process TJ,max and VCE,cold are measured at the same time in phase one and
phase two, for example. A further problem arises if the construction of the
test bench is considered, since it is not possible to measure the two switching
devices simultaneously, due to the fact that otherwise load and measuring
current would divide uncontrollably, which would not lead to a reasonable
result. For this reason, the semiconductors can only be measured at every
second cycle, which is also the case for the optional third module for program
technical reasons. This procedure works very well in theory, but in reality
there are technical problems with the measurement, which will be discussed
in the following chapter.
4.6.3. Challenges during the Measurement
In contrast to the curves depicted in Figure 28, the waveforms in the operation
of the test bench are significantly different. The behaviour of the load current
changes in such a way that a proper measurement becomes a big challenge.
During operation, the source has to supply sufficient voltage to drive the re-
quired load current, which is fine under stable conditions or in the steady
state. However, the invented switching algorithm turns out to be a challenge,
since in switching operation a much higher voltage is required to drive the
current than during the short measuring time, which has already been shown
in chapter 4.4. Due to the structure of the source, very large capacitances
(several hundred millifarad) are built in on the output side, which leads to a
large overshoot of the current relative to the load jump when a load shedding
takes place, which happens exactly during the measurement time.
VCE Ph1_Dut1 IC Ph2 VCE Ph2_Dut1

60 12
50 10
40 8
Current [A]
Voltage [V]
30 VCE,cold 6
20 4
Tvj, min
10 2
0 0
1 1,5 2 2,5 3 3,5 4
Time [s]
Figure 29: Overlapping process, 500µs measurement period, sampling rate

100 kHz, data from power cycling programme
VCE Ph1_Dut1 IC Ph2 VCE Ph2_Dut1

60 12
50 10
40 8
Current [A]
Voltage [V]
30 6
20 4
10 2
0 0
1 2 3 4 5
Time[ms]
Figure 30: Overlapping process, 1000µs measurement period, sampling rate

100 kHz, data from power cycling programme
Figure 29 and Appendix Figure A. 5 show the behaviour of the current and,
as can be seen, the amplitude rises to a maximum of approximately 46 A,
whereby only 42 A was specified, which corresponds to a deviation of around
10 %. A longer measurement time of 1000 µs, as chosen for the recording in
Figure 30, only aggravates the problem as expected. With this measurement
the current rises to about 50 A, which leads to an increase of about 20% com-
pared to the set value. As already mentioned, the current source behaves as
used in constant voltage mode due to the output capacities, which in turn
leads to an uncontrolled current. Due to environmental influences on the ca-
bling as well as the auxiliary switches and ageing of the packaging technol-
ogy of the device, the load is very likely to change. This slow load change
during the measurement period will cause the current to change in the course
of the test, which in turn causes a change in the voltage drop of the devices
under test. A change in the voltage drop is unsightly in the best case, but in
the worst case it can lead to a falsification of the measurement results, making
an evaluation more difficult or impossible. In order to bypass this behaviour,
a current set-value search was implemented as the first attempt, which en-
sures that the correct current within a tolerance band is searched for beyond
the overlap process. This procedure was used in the first tests as described in
chapter 5.2 to obtain a much smoother current. This method has proven to be
easy to implement, but it also has its limitations, because the forward voltage
drop has to be determined during the high frequency operation, which is only
possible under certain conditions. A first important criterion is the switching
frequency, because if it is too high it is not possible to determine a measured
value. Furthermore, a software filter has to be implemented which can clearly
distinguish between too high and too low values. In the first tests, a five-wire
installation cable was wound onto a PVC pipe as leakage inductance in order
to achieve the required value. This comparatively simple construction turned
out to be perfectly suitable in several respects, because oscillations were sup-
pressed by switching due to the relatively high resistance, the resulting mag-
netic field is not subject to major changes and the coupling capacitance to
earth can be increased by the free fifth wire, which has a positive effect on
the measured value quality. This design made it possible to obtain a clean
measured value during switching operations without any problems. Due to
the test bench structure, oscillations in the current occur after the overlap pro-
cess, which are determined by the control in the source, the large main in-
ductance and the high frequency operation. Due to the changes in the envi-
ronmental variables, different oscillations occur as a result, which is why
there can be no fixed time for the search in the current. This in turn represents
a small uncertainty factor, since the component heats up after switching on
and thus has a slightly different temperature when measuring at a different
time, which can be neglected from the point of view of the author. In later
tests a different inductance had to be used. In order to realize a higher current,
as it is necessary for testing the low voltage MOSFETs, the total resistance
of the system has to be significantly reduced, which leads to the fact that the
current set-value search can no longer be applied because very strong oscil-
lations occur. The removal of the resistor also results in an extreme reduction
in the damping of the entire system, which means that the current regulation
of the source becomes unstable and can no longer generate a direct current.
For this reason, a defined damping resistor had to be installed again, which
has a sufficient current carrying capacity and damping but at the same time
does not generate a too large voltage drop, since the current source can only
provide a limited voltage. A tram braking resistor was classified as suitable,
but with a value of 200 mΩ it was too high. A second resistor was connected
in parallel to achieve the required value. When testing the low voltage
MOSFETs, as found in chapter 6.1, a current of 127 A had to be set to achieve
the required temperature swing, which led to the outside temperature of the
resistor rising to over 400 °C, which was measured with an infrared camera.
Safe operation with such high temperatures is only permitted with special
protective features, which is another reason for developing a separate current
controller for this test bench.
4.6.4. Current Source for Fast Regulation
The challenge in this case is the development of a current control for this
application scenario with the extremely high dynamics of the value to be con-
trolled. In order to obtain a reasonable measured value during the measure-
ment time, the current has to be regulated within 100µs and there must not be
any oscillations in high frequency operation, whereby there must not be any
influence of other measured variables during regulation. Including a power
source is not an option, as most standard sources are based on a switched
power supply for efficiency reasons, have a very large output capacitance and
a very long rise time due to their design. The self-constructed low set adjust-
ers with current control, which are used, for example, for old test bench types,
are not used mainly for EMC reasons, but due to their very large inductance
they also have the disadvantage that they can only react relatively slowly to
load jumps. For these reasons, a concept was developed which allows ex-
tremely fast regulation but does not cause any disturbances during the meas-
uring time, featuring a robust design. As a basis for this design the already
existing concept of the cross regulator [110] was chosen. However, the FPGA
cannot be used for regulation, since the limit frequency of the analogue output
module is 100kHz [111], which is at least ten times too slow, whereby stabil-
ity criteria have not yet been taken into account, which further increase the
time until the stationary final value is reached. Therefore, an analogue regu-
lator has to be used, which is much faster, but cannot simply change its prop-
erties via software.
IGBT
(FZ900R12KE4)
A +
Analog OPV
Regulator
DC ±12V Suply
Vref
Figure 31: Simplified circuit for the line regulator [112]
The simplified structure of the control loop is shown in Figure 31, in which
the remaining test stand is not shown for the sake of clarity. The source shown
in the figure as DC is in reality a variable transformer with B6 rectifier at the
output, which leads to a high ripple of the resulting voltage [113]. The ana-
logue controller is an OPV of type NE5534AP [114] which has the charac-
teristics of a PID controller due to a respective circuit [115]. To measure the
current, a closed loop compensated current transducer type LEM LF 310-S
[116] was used, which has a cut-off frequency of 100 kHz, whereby the reac-
tion time for small jumps is specified as 0.5µs, which means that control can
be implemented with it. The reference voltage is specified by an analogue
output module through the measuring system and can thus also ensure that a
different current flows in the different phases of the test bench and thus rep-
resent the function of the cross regulator. If the current is not regulated, the
current follows the voltage and has a 300 Hz ripple. If a large capacitor is
used as an energy storage and to smooth the voltage at the output of the rec-
tifier, this has the advantage that the line regulator no longer has to regulate
the ripple, but the disadvantage is that this energy storage has to be safely
charged and discharged and current peaks can occur during load jumps. For
these reasons, a capacity has been dispensed with, which however, as already
mentioned, leads to an increased demand on the regulator. The OPV changes
the gate voltage at the IGBT until the voltage generated by the current flow-
ing through the LEM converter is equal to the reference voltage. However,
there has to be sufficient control reserve to compensate the ripple, to absorb
the voltage drop of the regulator and to compensate for any increase in the
voltage drop of the devices under test. The specified source voltage should
also not be too high, otherwise the power dissipation of the IGBT will largely
increase. A voltage drop of about three volts has proven to be a reasonable
value. Depending on the given voltage, the IGBT operates close to the gate
threshold voltage, whereby it can be assumed that a negative temperature co-
efficient always prevails and that the component is therefore at an operating
point not intended for this purpose for a longer period of time.
100 10
IPH1
Current [A]
80 IPH2 8
VCE [V]
60 6
40 4
20 2
VCE, PH1,S1
0 0
300 500 700 900 1100 1300
Time [µs]
Figure 32: Overlapping Process with line regulator, 100 kHz sampling rate
The figure shows how the commutation process between the two phases be-
haves with the line regulator. The measurement data for this originate from
the power cycling programme and were recorded with a sampling rate of
100 kHz, which means that only a limited statement can be made for the con-
trol process itself. It is noticeable, however, that no change in the total current
can be detected, especially not during the measuring time, which leads to the
assumption that the controller fulfils its task satisfactorily. The slight oscilla-
tions in the current are caused by the high frequency operation, but there is
no 300 Hz ripple detectable, because it has been eliminated by the regulator.
5. Test Results with IGBTs 69
5. Test Results with IGBTs
IGBTs are commonly used in many applications, therefore the first test series
were performed with this type of device. The first tests consider whether the
test bench is able to produce reliable and comparable data, which are the tests
with the 25 A IGBT carried out in chapter 5.2.
5.1. Modules with Baseplate
It is expected, that modules with different packaging technology will give

different lifetimes and failure mechanisms, which is the reason that also tests
with modules with baseplate were performed. As device an Econo-style pack-
age (FS150R12KT4) was used which has a nominal current of 150 A and a
blocking voltage of 1,200 V. This package has six IGBTs inside forming a
three phase inverter, where each phase has its own DCB.
The first test was designed to be close to the tests for the modules without
baseplate (see chapter 5.2). Because of the design of the test bench only one
water cooling plate was mounted. Due to the layout of the copper adapter
plates it is only possible to mount four devices, which is fortunately the num-
ber of necessary switching devices. The DC devices were tested on a standard
power cycling test bench equipped with a similar measurement system, to get
comparable results.
1.000.000
Nf
100.000
70,00 75,00 80,00 85,00 90,00
∆Tj [K]
CIPS DC SW_150A SW_106A
Figure 33: Reached number of cycles for Econo-package; ton = 2 s;

IC = 150/106 A; Tj,max = 125 °C, fSwitch = 25000/22000 Hz
As Figure 33 shows, the results are very close to the expected value repre-
sented by the CIPS model. Furthermore there is only a very small difference
between the switched devices, displayed as “SW”, and the IGBTs tested on a
standard test bench (“DC”).
120,0 95,0
∆Tj
115,0 90,0
Rth,jhs and VCE [%]
110,0 85,0
∆Tj [K]
105,0 80,0
100,0 75,0
VCE RTH
95,0 70,0
0 50000 100000 150000 200000 250000
Nf
Figure 34: Course of module #0531, IGBT 9; ton = 2 s; IC = 150 A;

Tvj,max = 125 °C, DC
120,0 95,0
115,0 90,0
Rth,jhs and VCE [%]
110,0 ∆Tj 85,0
∆Tj [K]
105,0 80,0
VCE
100,0 75,0
RTH
95,0 70,0
0 50000 100000 150000 200000 250000
Nf
Figure 35: Course of module #0427, IGBT 1; ton = 2 s; IC = 150 A;

Tvj,max = 125 °C, fSwitch = 22,000 Hz
Both groups reached end of life due to a volatile rise of VCE of more than five
percent, shown in Figure 34 and Figure 35, which indicate bond wire failures.
The switched test with less current (“SW_106A”) was performed to detect
the current dependency of this package. The data reveals, that there is no de-
pendency of the current, which is probably caused by the high number of
bond wires and the low current per bond with 9.4 A (6.7 A for “SW_106A”)
per bond foot.
The same type of module was also used to perform a test, where the standard
power cycling test can just reach a significant temperature swing, while using
a current over the rated specification, as shown in chapter 2. But with switch-
ing losses it is possible to achieve basically any swing, if the cooling condi-
tions are suitable. The turn-on time was chosen to be as short as possible and
to be in the area of a net frequency with 10 ms. In the first test it was necessary
to exceed the current rating also by 10 % to reach the required conditions and
to have a stable current. In order to facilitate a classification of the test, a
relatively high swing of 50 K was chosen first.
Figure 36: Reached number of cycles Econo-package; ton = 10 ms; IC = 165 A;

Tj,max = 175 °C [112]
Figure 36 shows the number of cycles reached with the specified conditions.
As the datasheet reveals, the junction temperature is too high, as the maxi-
mum determined value for switching operation is 150 °C. The CIPS model
seems to fit pretty well, but this is just caused by coincidence, due to the fact
that with a temperature swing of 50 K only a few data points are available and
the ton-dependency cannot be used to extrapolate from the second range to
milliseconds, see [117]. The power loss density in a test with short on time is
usually very high, which will result in a greater difference between the actual
junction temperature and the measured one temperature [60], [117]. There-
fore, a 3D FEM simulation was done to find the actual value of the junction
temperature, which is also shown in the figure above. The data reveals that
the difference is about 7.2 K, which is very high especially for tests with a
low temperature swing, because the error then is quite high [40]. The classi-
fication of the results is not easy, because there are not many reference values,
if the module type is taken into account, there are no results. Nevertheless,
the number of cycles is in the range between Manufacturer A and B from
[117], but a different package (for traction applications) was used there.
Because of the exceeded maximum junction temperature, which is even

higher if the simulations results are considered, a second test was performed,
with a longer turn-on time of 20 ms, a lower current of 150 A and a lower
maximum junction temperature of 150 °C.
100.000.000
CIPS Switched DC
10.000.000
Nf
1.000.000
45,00 47,00 49,00 51,00 53,00 55,00
∆Tj [K]
Figure 37: Reached number of cycles Econo-package; ton = 20 ms;

IC = 150/276 A; Tj,max = 150 °C, Tj,max, error = 2.27 K(276 A) | 2.05 K(150 A)
As Figure 37 shows, the number of cycles until end of life is more than dou-
bled in comparison to the first test. The parameters have changed to a longer
heating time, which also results in a lower maximum junction temperature.

The current was also set to the specified maximum of the data sheet. Due to
the change of more than one parameter, it is quite difficult to compare the test
results, but the second test is more close to the application because the initial
parameters are in the specified save operating area. For the test of the perma-
nently switched on devices 1.8 times of the rated current was used to achieve
the same conditions as for the test with switching losses. The reason for the
lower cycles count is clearly the overrun of the current rating. In case such
test conditions have to be achieved, the test bench with switching losses has
the advantage of not being bound to a certain current to reach significant
losses. A compensation of the temperature swing is necessary, but has not
been performed yet, due to the varying current and the difficult cooling con-
ditions for the DC-devices. A 3D-FEM simulation was performed to correct
the maximum junction temperature. The difference between the results is
small despite the fact that for the DC-test a very high current has been used.
A further test with an even lower temperature swing was performed. The
maximum junction temperature was set to 150 °C, as in the test before, so that
only two parameter are changed, which are the temperature swing of 30 K
and the turn-on time of 10 ms.
100.000.000
ton = 20 ms
ton = 10 ms
10.000.000
Nf
CIPS for 20 ms
1.000.000
25,00 30,00 35,00 40,00 45,00 50,00 55,00
∆Tj [K]
Figure 38: Reached number of cycles Econo-package; ton = 10 ms; IC = 150 A;

Tj,max = 150 °C, Tj,max, error = 3.51 K and data from test with ton = 20 ms
As Figure 38 shows, the number of cycles until end of life with a lower tem-
perature swing is increasing. The reason why the old test data is shown, is to
make clear that the CIPS model does not apply to these test conditions. In
case the correct input parameters are used for the 10 ms test the model pre-
dicts a lower lifetime than reached, while the distance to the 20 ms test is quite
high, which is caused by a to high steepness of the model.
As shown in this chapter the number of cycles is higher while not using ex-
treme high current and it also increases with lower temperature swing, which
is quite as expected. A 3D-FEM simulation showed that the error of the max-
imum junction temperature is about 3.5 K, leading to an actual mean temper-
ature swing of 33 K. The course of the tests reveals quite uncommon behav-
iour for these short on times.
120 90
Rth,jhs and VCE [%]
115 80
∆Tj
110 70
∆Tj [K]
RTH
105 60
100 50
VCE
95 40
0,0E+00 1,0E+07 2,0E+07
Nf
Figure 39: Course of module #0043, IGBT 3; ton = 20 ms; IC = 150 A;

Tj,max = 150 °C, fswitch = 10,000 Hz
Figure 39 shows a typical course of a device from the test with ΔTj = 50 K.
Obviously a rise in the thermal resistance is visible, but also jumps in VCE
after 20 million cycles can be observed. The usual failure mechanism for
these short on-times is bond wire lift off. The jumps in VCE indicate this, but
it did not lead to an end of life of this IGBT. Nevertheless, some devices
reached the end of their lifetime because of an increase of the voltage drop.
120 60,0
Rth,jhs and VCE [%]
115 58,0
∆Tj
110 56,0
∆Tj [K]
VCE
105 54,0
RTH
100 52,0
95 50,0
0,E+00 2,E+06 4,E+06 6,E+06 8,E+06 1,E+07
Nf

Tj,max = 150 °C, DC
To be able to compare the test with superimposed switching losses, a DC-test

was performed. As Figure 40 shows the reason for end of life was several
sudden rises of the voltage drop, whereas only a small increase in thermal
resistances was recorded, which can be ascribed to the cooling conditions.
120,0 70,0
RTH
Rth,jhs and VCE [%]
115,0 60,0
110,0 50,0
∆Tj [K]
VCE
105,0 ∆Tj 40,0
100,0 30,0
95,0 20,0
0,0E+00 5,0E+07 1,0E+08
Nf

Tj,max = 150 °C, fswitch = 11200 Hz
For the test with ΔTj = 30 K, where a sample can be seen in Figure 41, this
behaviour becomes clearer. The VCE shows only a small rise and there are no
jumps visible at all. This behaviour can be observed for every tested device
with these conditions.
Figure 42: SAM-Image of an Figure 43: SAM-Image of #0531,

untested device IGBT 1, ΔTj = 50 K, DC
Figure 44: SAM-Image of #0054, Figure 45: SAM-Image of #0052,

IGBT 3, ΔTj = 50 K IGBT 3, ΔTj = 30 K
The SAM images shown in Figure 42 to Figure 45 reveal that mostly all of
the bond feet are missing, or not visible. The differences in the way of deg-
radation are, however, quite remarkable. For the DC-test there is no change
in the solder layer visible, which concludes with the course of the test shown
in Figure 40. The images from the test with the superimposed switching
losses, however, show that there is degradation of the solder layer. In Figure
44 some bond feet are missing and some are lift off, which also concludes to
the recorded data in Figure 39. A statement about the state of health of the
bond feet cannot be made from the SAM-image of the 30K-test due to the
massive degradation of the solder layer.
The root cause for this behaviour is subject to further research. The reason
for the low cycles count and the clear wire failures for the DC-Test is obvi-
ously the massive exceeding of the rated current. Nevertheless, it is not ex-
pected that temperature swings in the region from 20 to 50K lead to a failure
in the chip solder. The courses of the tests and the SAM images reveal that
there is degradation of the solder layer. One possible explanation might be
the observations made by [24]. The power density is designated as the reason
for the change of the start of the crack growth, whereas less density means
the grow starts from the edge. The power density for such tests is extremely
high, which could lead to an even different error pattern. In Figure A. 8 the
red circles show the other IGBTs tested with also a swing of 50K, whereas it
becomes visible as if only some parts of the IGBT’s solder are degraded. In
the 30K-test the behaviour gets more distinctive, due to the shorter turn-on
time. The red circle in Figure 42 and Figure 45 show the pattern of the bond
feet. A very similar appearance can also be found in the degradation.
5.2. Modules without Baseplate
A 25 A IGBT [104] from Infineon from the Easy series with a blocking volt-
age of 1200 V was chosen for the first tests.
130 110
125 105
Rth.jhs and VCE [%]
120 100
115 Rth 95
ΔTJ [K]
110 ΔTj 90
105 85
100 80
VCE
95 75
0 50000 100000 150000 200000 250000 300000
Nf
Figure 46: Device #039, IGBT 1, ton = 1 s, IC = 28 A, Tj,min = 30 °C, 50 %

switching losses, fswitch = 12.5 kHz
An example of a course can be seen in Figure 46, while it is typical for these
modules that the thermal resistance increases, where also a VCE increase is
visible. The number of cycles achieved is in line with the expected value for
this type of module, whereby the unsteady behaviour of the thermal resistance
is due to the current regulation problems already mentioned in chapter 4.6.3.
A total of three tests were carried out for this module type, varying the tem-
perature swing, the percentage of switching losses and the current.
1.000.000
Nf
100.000
50,00 60,00 70,00 80,00 90,00 100,00 110,00 120,00
∆TJ [K]
CIPS 2008 extrapolated for ton=1s IGBT4, deltaTj=80K, steady ON
IGBT4, deltaTj=80K, 66% IGBT4, deltaTj=100K, 66%
Figure 47: Power cycling results of FS25R12W1T4, ton = 1 s
Figure 47 shows an overview of the tests performed, with the first fact to
notice being that the average lifetime is with 66 - 70% below the expectation
of the CIPS model. The results show that there is no dependence of the num-
ber of cycles on the amount of switching losses for the used test conditions.
It should be noted that the noise of the results can lead to a masking of the
dependency. The fact that there is no difference between switched and non-
switched devices is undoubtedly a good result for the manufacturer, because
in this test the test specimen has to be able to block voltage, actively switch
off and withstand thermomechanical stress, very much like in the application.
As already mentioned, in the course of the test of this component there is a
continuous increase in the voltage drop and the thermal resistance, whereby
it is noticeable that this starts right at the beginning. Sudden rises, typical for
a heel crack or bond wire lift off, are not visible, which gives reason to believe
that the slow rise is due to solder degradation, changes in the top metallization
or a mixture of both.
Figure 48: FS25R12, untested, Figure 49: Device with changes in

photo trough silicone gel metallization, Tj,max = 150 °C,
∆Tj = 80 K
If Figure 48 and Figure 49 are compared, it becomes clear that after the power
cycling test, changes in the metallization are visible with the microscope,
usually referred to as reconstruction, explaining a part of the increasing volt-
age drop.
Figure 50: Untested device with cell structure visible
Figure 50 shows, again, that the cell structure of a new module is clearly rec-
ognizable, whereby it should be noted that the brown sludge, which is caused
by the removal of the silicone gel, should not influence the result.
Figure 51: Bond foot with metalli- Figure 52: Bond foot with metalli-
zation changings, device 00041 zation changings, device 00023
The brown copper sludge becomes visible again, but it is quite obvious that
the aluminium has changed significantly compared to the new state. Figure
51 and Figure 52 also show that this change appears to be more concentrated
around the bond feet, indicating the temperature dependence of the changes.
A pull test, as it is usually done to qualify a bond connection, showed that the
force needed to release the connection to the chip was small and the bond
lifted off [118]. In case the connection is untested, the bond will tear at the
loop where it is pulled [119], [120], while the applied force is about 5-10 N.
The poor bonding of the bond at the end of its life shows that slow crack
growth, as it is well known with such modules, can contribute to a slow in-
crease in the voltage drop. For further analysis, the module was examined
using an ultrasound microscope.
Figure 53: DCB device 00023
As expected, the ceramic and copper of the DCB do not show any damage,
see Figure 53.
Figure 54: Chip solder of device 00023
The solder layer of the chip of this module shows clear degradation, whereas
it started from the centre of the chip, as Figure 54 shows. The material content
datasheet [121] reveals that no lead-containing solders are used and it is
RoHS compliant, therefore it can be assumed that a tin-silver-copper solder
has been used, which in turn supports the investigations from [24]. The results
in the paper show that lead solder layers start to degrade from the edge, while
tin-silver solder layers ages from the centre. However, from the author's point
of view, it is to be expected that other mechanical properties will also influ-
ence the behaviour of the soldering.
A second test was carried out in which a module without base plate was also
used, but the current class of the IGBTs was significantly higher and thus the
chip size is larger. This applies for a FS75R12W1T4, which has a rated cur-
rent of 75 A and a rated voltage of 1,200 V.
1.000.000 CIPS
DC 1s
Switched_1s
DC 0.5s
Switched 0.5s
Nf
100.000
60,00 70,00 80,00 90,00 100,00
∆TJ [K]
Figure 55: Test results for FS75R12W1T4 (ton = 0.5 s, 68.5 A; ton = 1 s, 60 A
Tj,max=150 °C, 50 % switching losses, fswitch = 11-12 kHz, CIPS model for
ton = 1 s)
As can be seen from Figure 55, the behaviour is similar to the results obtained
from the modules with a lower current class. Surprisingly, a lower switch-on
time does not result in a higher number of cycles, not as predicted by the
lifetime model.
Figure 56: SAM image after test; module# 475, ton = 1 s
As already observed before, even modules with a switch-on time of one sec-
ond show a very clear destruction of the chip solder, which can be seen from
the SAM image in Figure 56. Because of this, no statement can be made about
the bond interconnection or metallization, since the ultrasonic waves no

longer penetrate the top of the chip.
Figure 57: SAM image after test; module #037; left: ton = 1 s; right: ton = 0.5 s;
solder layer and bonds (top image)
In Figure 57 a comparison can be made between the ton- times. The destruc-
tion of the solder layer on the right side, which was turned on for 0.5 seconds,
is noticeably smaller than on the left. Due to the degradation of the solder
layer only parts of the metallization are visible, but still there are bond feet
on the upper right side of the SAM image.
135 110
Rth,jhs and VCE [%]
ΔTj
125 100
ΔTj [K]
Rth
115 90
VCE
105 80
95 70
0 100000 200000 300000
Nf
Figure 58: Test course of #037, IGBT 9; ton = 0.5 s; IC = 68.5 A;

Tvj,max = 145 °C, 50 % switching losses, fswitch = 8.5 kHz
The diagram of module #037, displayed Figure 58, shows a course which is
similar to the other tested devices. The thermal resistance is rising slowly
until the very end, where the change is rapidly increasing. The voltage drop
shows a slow, but not stepwise increase, which did not reach the end of life
criteria of 105 %. This behaviour was observed and discussed before in the
test of FS25R12.
Module #475 #475 #475 #475 #037 #037

Test Ref [N] 1. [N] 3. [N] 4. [N] 5. [N] 6. [N]
Bond 1 5.34 5.66 3.85 5.80 2.92 3.87
Bond 2 6.50 1.80 0.64 1.16 0.35 1.51
Bond 3 6.89 0.80 0.37 0.38 0.36 0.46
Bond 4 6.86 0.36 0.38 0.38 0.46 0.70
Bond 5 6.76 0.28 0.48 0.57 0.76 1.40
Bond 6 6.74 0.30 2.29 1.26 3.96 4.51
Average 6.72 0.82 0.95 0.84 1.47 3.87
Table 1: Results of a bond pull test for module #475 and #037
Table 1 shows the results of a bond pull test performed on several chosen
IGBTs. The test named with “Ref” is an untested IGBT, therefore it is used
as reference to be able to compare it with the tested ones. The average is the
trimmed mean value, where the maximum and the minimum of data is ig-
nored.
Bond feet
Bottom systems Top systems
2 1 Bond 1
Bond 2
Bond 3
3/5 6 Gate bond
Bond 4
4 Bond 5
Bond 6
Figure 59: Tested systems and positions of the bonds on the chip
Figure 59 shows the position of the tested chip and the position of the pulled
bond wire. As the table shows the bond of the gate was not tested, because
no abnormalities were found during the static measurement. The results show
that the used force for the tests three and four of module #475 is very low and
therefore the connection between wire and metallization has been severely
weakened. The comparison between 0.5 and 1.0 seconds turn-on time in mod-
ule #037 reveals a slightly higher force for the IGBT with the lower heating
time. The reason for the difference between the tests is probably the higher
energy density for the test with 0.5 seconds turn-on time. During the bond
pull test it was observed that the bonds, which were not aligned (left side of
the chip) tended to be rather loose, compared to the bonds on the right side
of the chip. The reason is probably a higher temperature in the bond foot,
because the location of the bond feet on the chip shows that some a closer to
the centre.
What follows is a short conclusion for this sub-chapter.
The results clearly show that the selected module’s main ageing mechanism
is solder layer degradation, no matter which ton is used if it is higher than 0.5
seconds. The damage of the solder layer always starts from the centre of the
chip. The results show no dependency on switching losses, which is caused
by the triggered failure mechanism, hence the solder will not be influenced
by the level of the current or the way the losses are generated in the chip. The
test results shows only a small difference between 0.5 and one second heating
time, which is unexpected. It should be noted that the noise of the results can
lead to a masking of the dependency. The steady final value of the thermal
resistance is already reached after one second, but at 0.5 seconds the value is
very close, which is a possible reason for the lack of difference. Through the
most common lifetime models a current dependency is given. For modules
without baseplate and very good bond wire interconnections this seems to be
not the case and a revision with more recent data is suggested. One possible
way is to distinguish between modules with and without baseplate and dis-
crete.
In the following chapter a closer look to IGBTs in discrete housings is given.

With regard to the different packing technology it is expected that the influ-
ence of switching losses also varies.
5.3. IGBTs in Discrete Housings
At first, a 40 A IGBT from Infineon (IKW40T120, International Rectifier,

[122]) was tested in a discrete housing.
10.000.000
Switched DC
1.000.000
Nf
100.000 IC = 43 A
IC = 56 A
Discrete
10.000 Model
65,0 70,0 75,0 ΔTJ [K] 80,0 85,0 90,0
Figure 60: Power cycling results IKW40T120, Tj,min = 75-80 °C, 50% switch-
ing losses, fswitch = 8.5-9 kHz
The tests performed can be seen in Figure 60, where it is noticeable that these
discrete IGBTs have a very good performance since Δthey reach a lot more
cycles than expected by the discrete model [58].
115 90
110 88
86
VCE [%]
ΔTj [K]
105 VCE
84
100 82
ΔTJ
95 80
0 100000 200000 300000 400000
Nf
Figure 61: IKW40T120, #006, ton = 2 s, IC = 56.5 A, Tj,min = 81.5 °C, DC device
An exemplary course of a permanently switched-on DUT can be seen in Fig-

ure 61, where the cause of failure is a sudden increase in the voltage drop.
125 95,0
120 92,5
115 90,0
VCE [%]
ΔTJ [K]
110 VCE 87,5
105 85,0
100 ΔTJ 82,5
95 80,0
0 200000 400000 600000 800000
Nf
Figure 62: IKW40T120, #002, ton = 2 s, IC = 56.5 A, Tj,min = 83 °C, 50 % switch-

ing losses, fswitch = 7.5 kHz
In contrast to the switched test device in Figure 62, the first bond wire failure
on DC devices already leads to reaching the set limit, which was at
Tj,max = 175 °C in this test. The reason for this is in the way in which the power
losses are generated in the component and which temperature and chip char-
acteristic dependencies are involved. Active switching off results in an
amount of energy which is only slightly dependent on temperature and is not
dependent on the voltage drop of the component and can therefore be re-
garded as almost constant. A bond wire defect therefore leads to a higher
temperature rise in a permanently switched-on test specimen than if the com-
ponent is partly heated by switching losses. However, this behaviour cannot
explain the difference between the switched and continuously turned-on de-
vices, because the increase in the collector-emitter voltage drop is present in
the same way and was also used as a failure criterion. As already mentioned
in Chapter 1.2, there is a new improved lifetime model for discrete compo-
nents, which does not cover as many possibilities as the CIPS model, but at
one point it offers a decisive advantage. The dependence on current in the
model for power modules is about β4 = -0.717 [49], while newer publications
for discrete devices of the same author tend to indicate a factor of -2.36 [59].
Since in pulsed operation the RMS value of the current at the same switch-
on to switch-off time is smaller by a factor of 1.414 than for DC, a correct
current dependence must be used to permit a comparison of the results.
10.000.000
1.000.000
Nf
100.000
60,00 65,00 70,00 75,00 80,00
ΔTj [K]
DC Switched Discrete_switched Discrete_DC
Figure 63: Power cycling results for discrete device IKW40T120, test results
compared with discrete lifetime model from [59], ton = 2 s, IC = 56.5 A, Tj,min
= 83 °C, 50 % switching losses
IKW40T120, test results with discrete lifetime model
Figure 63 shows the results with the corrected factor and the corresponding
RMS current value, whereby the initial life K was the only one of the existing
factors to be adjusted to 1∙E13. The results show that the switched device
reaches a higher number of cycles, but this is no longer the case if the correct
model is taken into account. In order to determine the exact cause of the error,
several test specimens were examined and the mould compound was re-
moved. The failure analysis showed that a heel crack occurred for all tested
specimens.
Figure 64: Heel crack in IKW40T120 after removal of transfer mould
Figure 64 shows a remarkable break on the side of the bonding wire, whereby
it is also noticeable that only a minor change in the metallization is detectable,
which can be regarded as unusual due to the high junction temperature. The
changes of the bonding wire at the point where the tool has set for bonding
can be traced back to the mechanical stress in combination with the very
strongly corrosive acids during the detachment of the mould.
Figure 65: SAM, IKW40T120, De- Figure 67: SAM, IKW40T120, De-
vice 021, chip solder, after vice 021, chip surface, after
Figure 66: SAM, IKW40T120, De- Figure 68: SAM, IKW40T120, De-
vice 001, chip solder, after vice 001, chip surface, after
The solder layer of the IGBT show no visible degradation, when compared
to the diode, as shown Figure 65 and Figure 66. However, some voids can be
found. From the images of the chip surface an evaluation is difficult, but the
bond feet are still clearly visible, which fits well with the observations made
during the removal of the mould compound.
The second test with discrete IGBTs was performed with a 650 V device,
where the clamping voltage was also 400 V. In contrast to the first test with
moulded devices, there is only one bond wire, which carries the current. This
means that the current density is very high. In contrast to the test in chapter
5.2, the IGBT used has a lower blocking voltage of 650 V and the mould
compound was produced by a different manufacturer.
100000
Nf
10000
80,00 85,00 90,00 95,00 100,00
ΔTj [K]
Discrete Model Switched DC
Figure 69: Lifetime of IKW20TN60, Tj,min = 60 °C; IC = 32.1 A, 50 % switching

losses, ton = 2 s
As Figure 69 shows, no difference or only a very small difference between

switched and continuously turned-on devices under test can be determined,
which is also due to the high scattering of the results. The model, which is
visible in the diagram, is again the lifetime model used for discrete compo-
nents, whereby again only the initial life K with 5∙E11 has been adapted to the
IGBT. Now the relatively achieved lifetime of the switched (177 %) and non-
switched (126 %) test specimens can be calculated and compared. In case that
the current dependency applies to these components at all, the result should
be approximately the same for both, as in the test with IKW40T120. Since
this is obviously not the case, a failure analysis of the relevant IGBTs has
been performed.
Figure 70: SAM, IKW20TN60, De- Figure 72: SAM, IKW20TN60, De-
vice 0190, chip surface, before vice 0190 chip solder, before
Figure 71: SAM, IKW20TN60, De- Figure 73: SAM, IKW20TN60, De-
vice 0190, chip surface, after vice 0190 chip solder, after
As Figure 69 to Figure 73 show, that no degradation can be detected in the

chip solder, although the surface of the chip around the bond foot shows
changes. The removal of the encapsulation of the test specimens made it pos-
sible to establish that the cause of the defect was bond wire lift-off.
6. Test Results with MOSFETs 97
6. Test Results with MOSFETs
With the new test concept it is also possible to carry out tests on MOSFETs
with the corresponding modifications as mentioned in chapter 1.1.4. How-
ever, it is absolutely necessary to switch the measuring current, since during
the high frequency operation a voltage up to 1000 V can be applied, which
leads to the fact that first of all a lot of diodes would be needed and secondly
the measuring current source would have to overcome the forward voltage of
the diodes. In the following, low voltage MOSFETs were tested, which, as
already mentioned in chapter 2, can only be power cycled with high effort.
6.1. Low Voltage Si MOSFETs
As a first test a module with low voltage MOSFETs in standard packaging

technology (soldered die attach and aluminium bond wires) was used, which
has a rated current of 300 A and a blocking voltage of 40 V.
1.000.000
CIPS
Switched
Nf
DC
100.000
40,00 45,00 50,00 55,00 60,00
ΔTj [K]
Figure 74: Reached number of cycles; Tj,max = 150 °C; Iload = 70 A; ton = 2 s,
80 % switching losses, fswitch = 15 kHz, TO247, DC-Devices tested with low
VGS (3 to 5 V)
As Figure 74 shows the reached number of cycles is quite different between

switched and permanently turned on devices. The relatively reached lifetime
is quite low for the DC devices compared to the CIPS model, which were
tested with low gate voltage to generate sufficient losses. The prevailing neg-
ative temperature coefficient is most likely the root cause for this behaviour.
Figure 75: SAM, tested Device, Figure 76: SAM, new Device
Test#2, ΔTj = 80 K (see Figure 78)
The SAM images, shown in Figure 75 and Figure 76, were taken before and
after the second test with 80 K temperature swing. The current was raised to
80A, while the rest of the conditions were the same. Strong modifications can
be found at the metallization and the picture also indicates bond wire lift off
as a failure mechanism, which is complementary to the test course shown in
Figure 77. The solder layer shows no degradation at all.
140 100
130 95
ΔTJ
120 90
Δ Tj in K
VDS in %
VDS
110 85
100 80
90 75
80 70
0 50000 100000 150000
number of cycles
Figure 77: Low voltage MOSFET with 90% switching losses, switched De-
vice, ton = 2 s, ID = 80 A, TJ,min = 71 °C
Because low voltage modules are not very common and expensive, the fol-
lowing tests were performed with discrete devices.
A discrete component with a rated current of 195A, which is limited by the

packaging and connection technology, was selected as the component,
whereby the blocking voltage is 40V [123]. With a RDS,on of 1.35 mΩ, this is
still a semiconductor with a relatively high resistance, yet the rated current
for the package type (TO247) is very high.
1.000.000
Test #3
100.000
Nf
Test #1
Test #2
DC Switched DiscreteIGBT
Discrete SWSW
10.000
55 60 65 70 75 80 85
ΔTj [K]
Figure 78: Performed tests on IRFP4004, failure criteria for switched De-
vices: 5 % VDS increase, Tj,max = 150 °C, ton = 2 s, see also Table 2, discrete
model [59]
In “Test #2” with a temperature swing of about 80 K (see Figure 78), the
inverse diode of the MOSFET was used to generate sufficient power dissipa-
tion for the permanently switched-on devices. The switched semiconductors
have reached a temperature swing of 20 K at the load current of 128 A with-
out switching losses, so that for this test about 75 % switching losses were
superimposed. For “Test #1” the DC-devices were operated in forward mode,
but with a very low gate voltage. By testing these components also new chal-
lenges arise in the measurement and evaluation of test results.
0,200
0,190 120%
110%
VDS_cold [V]
0,180
105%
0,170
0,160
0,150
0 100000 200000 300000
Nf
Figure 79: Voltage drop at load current (128 A) for low voltage MOSFET,
test conditions see Figure 78 Test#2, failure criteria (see box)
As can be seen in Figure 79, the voltage drop at the load current is relatively
low (153 mV), which also means that with a usual failure limit of VDS,cold
+ 5 %, the absolute value by which the voltage may rise is 7.65 mV. The first
challenge is the reliable detection of this low voltage and secondly it is clear
that at ~160 mV the component has not yet failed and therefore the failure
limit should be set to 120 % or higher [38]. When looking at the measured
values, it can be seen that the distance of the switched test specimens from
the test with about 60 K temperature swing is higher than in the already men-
tioned test. In this test, the permanently switched on MOSFETs were also
operated in MOSFET mode, but the gate voltage was greatly reduced, close
to the gate threshold voltage, resulting in an even stronger negative tempera-
ture coefficient than in the inverse diode test.
Current, Current, Discrete IGBT Discrete IGBT

DC [A] RMS [A] model, DC model, switched
Test #1 108 76.37 72% 100% *
Test #2 128 90.51 130% 100% *
Test #3 90.7 64.13 - 103%
Table 2: Used current and reached number of cycles relative to the discrete
model
Figure 80: IRFP4004 with removed encapsulation
Figure 80 shows that there is no change in the metallization and that the bond-
ing feet are still connected to the chip.
Figure 81: Heel crack in Figure 82: Heel cracks in

device 012, Test#2 (Figure 78), device 013, Test#2 (Figure 78)
Nf = 99,500 Nf = 106,000
Figure 81 and Figure 82 reveal that end of life has been reached due to heel
crack, which could also be determined in all test specimens that were exam-
ined. The SAM pictures taken show that there is no degradation of the chip
solder, which coincides with the measured value of the thermal resistance.
Figure 83: SAM, IRFP4004, chip Figure 85: SAM, IRFP4004,

surface, untested device chip surface, device 0015 Test#1
(Figure 78), Nf = 456,000
Figure 84: SAM, IRFP4004, Figure 86: SAM, IRFP4004,

solder, untested device solder, device 0015 Test#1 (Figure
78), Nf = 408,000
As Figure 83 and Figure 85 indicate, the metallization shows visible changes,

but the bond feet are still sufficiently connected. The solder layer (see Figure
84 and Figure 86) show no visible degradation. Device #0015 was tested in
forward mode with superimposed switching losses.
Another test on low voltage MOSFETs was performed to see if a slightly

higher reverse voltage would cause a difference in the results. Due to the
higher blocking voltage, the RDS,on is much higher and therefore as much cur-
rent flows through the bond wires. This results in a much lower temperature
of the wires [124].
1.000.000
100.000
Nf
10.000
70,00 75,00 80,00 85,00 90,00
ΔTj [K]
DC Switched Discrete SW
IGBT SW DC DC
Discrete IGBT
Figure 87: Lifetime of IRFP064N, TJ,min = 60-65 °C; IC = 42 A, discrete IGBT

models from [59], ton = 2 s, 80 % switching losses, fswitch = 10,5 kHz, ,
Tj,max = 150 °C
As in the previous chapters, the discrete lifetime model was used for the rep-
resentation in Figure 87, whereby the initial lifetime factor was changed to
k = 1.1∙E12, resulting in an average of 105 % for the permanently switched on
test objects (diode). For the switched MOSFETs, the current dependence re-
sults in a longer time until end of life, which, however, cannot be fully
mapped by the model, since the average lifetime is about 150 % and thus 1.5
times higher than by the model predicted. The failure mechanism of the tested
devices was found to be bond wire heel crack. One of the reason for this is,
probably, the very high current per bond and the geometry of the wire.
In the following a short chapter conclusion is given.
The test bench is able to test low voltage MOSFETs for the first time in for-
ward mode with superimposed switching losses and usual gate voltage, which
is closer to the application. Due to the different operation modes (low gate
voltage, diode-mode) a clear distinction can be made between the reached
number of cycles. The current dependency of the model for discrete devices
cannot map the results in a satisfying way. In case a gate voltage is used,
which is close to the gate threshold voltage, the lifetime, compared to the
switched devices, is lower by factor 3-4. The reason for this behaviour is pre-
sumably the different temperature coefficient in the operation modes. In for-
ward mode a positive dependency of the voltage drop with temperature is
prevailing, whereas in the diode mode a negative dependency dominates.
This will lead to current crowding at hot spots, which will lead again to more
heat and this behaviour will be worse if the negativity of the coefficient is
higher, which is the case with a very low gate voltage. To give a better state-
ment about this, a 3D-FEM simulation is carried out (see chapter 7).
The MOSFET mode can also be applied to SiC-MOSFETs and because these
devices show, due to their mechanical properties, a different lifetime, it is
expected that there is also an influence if they are tested with switching
losses.
6.2. SiC MOSFETs
Because of their good electrical properties, silicon carbide MOSFETs have

become increasingly popular in all types of applications especially where
high switching frequencies and high power densities are requested. The very
low switching losses allow to increase the frequency and therefore to reduce
the size of passive components such as inductors and filters. The low switch-
ing energies and the very small chip size have to be considered during the
setup of the test bench because otherwise the stray inductances are too high,
which will lead to a temperature swing per turn off, which is too high and
then has to be considered in the lifetime. The first test device is a SCT2080KE
from ROHM, which has a nominal current of 40 A at 25 °C and a blocking
capability of 1200 V.
1.000.000
DC Switched
Discrete
100.000 model
Nf
10.000
65,00 70,00 75,00 80,00 85,00 90,00
ΔTJ [K]
Figure 88: Test on SCT2080KE, ID = 37 A, Tj,max = 125 °C, 50 % switching

losses, fswitch = 13 kHz, discrete IGBT model from [59]
As Figure 88 shows the scattering of the reached number of cycles is very

high. The root cause for this behaviour is not quite clear, one possible reason
are fluctuations in the manufacturing process. The number of cycles predicted
by the discrete model are higher than the test results. A similar behaviour was
observed before [125], whereas the difference was higher. A dependency be-
tween switched and permanently turned on devices cannot be found, which
is also caused by the high scattering. Yet a failure analysis was performed,
but with SAM it was not possible to penetrate to the devices.
7. Analysis of Si Low-voltage MOSFETs Results with FEM 107
7. Analysis of Si Low-voltage MOSFETs Results

with FEM
As already mentioned in chapter 6.1 the lifetime of low voltage MOSFETs

operated in forward mode with low gate voltage or diode mode is significant
lower compared to the operation with the usual gate voltage and switching
losses. Current crowding is presumed caused by the negative temperature co-
efficient as a reason for this behaviour. To get the information about the be-
haviour of the current within the semiconductor, a 3D FEM simulation is per-
formed, while Ansys is used as simulation software.
Figure 89: 3D model of a discrete Si MOSFET [126]
Figure 89 shows the 3D model of an IRFP4004, which is used to perform a

thermal electric simulation. Very important for the quality of the results is the
meshing process, which can be very challenging, due to the complicated
structure. The mesh for the bond wires and the metallization for example have
to be very narrow to have a fine resolution in this area. The mould compound
on the other hand is of less interest, but cannot be omitted either, due to the
thermal effects. The finer the mesh is the more elements and nodes have to
be considered, which will lead to very long computing times and extensive
memory use, which it not necessary for example the behaviour of the lead
frame. Therefore, different element sizes have been used and the proper tran-
sition between these is the main difficulty.
Name Thickness Material

Metallization / Bond 4 µm Aluminium
Chip 200 µm (estimated) Silicon
Chip solder 50 µm Sn96.5Ag3.5
Baseplate 2.3 mm Copper
TIM 250 µm TIM KU-CG
Table 3: Material data for Si MOSFET Simulation
Table 3 shows the used materials and thicknesses of the layers, whereas more
detailed information, such as temperature dependency, can be found in the
table Figure A. 6. The thermal electric simulation was performed with two
operation modes: Forward mode, which equals a resistance with positive co-
efficient with a fixed part of energy disposed in the chip to represent the
power cycling test with superimposed switching losses, and diode mode
where a resistance with a negative coefficient was used. The virtual junction
temperature was determined by the “1/3” method, represented by the follow-
ing equation [29], [127].
𝑇𝑇𝑚𝑚𝑚𝑚𝑚𝑚 − 𝑇𝑇𝑚𝑚𝑚𝑚𝑚𝑚 (7.1)

𝑇𝑇𝑣𝑣𝑣𝑣 = 𝑇𝑇𝑚𝑚𝑚𝑚𝑚𝑚 −
3
The temperature swing calculated with the equation (7.1) was adapted to be
in the range of the of the power cycling test (see chapter 6.1), which is to be
represented. The simulated maximum junction temperature swing of 85.3 K
is about 5 K too high, which is caused by the actual varieties on the test bench
and probably also by some inaccuracies of the simulation parameters and ma-
terial properties.
160
140
Tvj [°C]
120
100
80
60
0 1 2 3 4
t [s]
Figure 90: Simulated chip temperature for a power cycle [126] using equa-
tion (7.1)
Figure 90 shows the course of the simulated virtual junction temperature for
one power cycle, under the condition that the complete system is in stationary
state. The temperature swing and the minimum junction temperature are ad-
justed to the conditions prevailing in “Test #2”.
Figure 91: Simulated surface temperature at the end of the power cycle for a
low voltage MOSFET with superimposed switching losses [126]
Figure 92: Simulated surface temperature at the end of the power cycle for a
low voltage MOSFET operated in inverse diode mode [126]
Figure 91 shows the thermal electric simulation for a Si-MOSFET with the
usual gate voltage and superimposed switching losses. In Figure 92 the same
conditions are used, but the MOSFET is operated in inverse diode mode and
therefore no switching losses are added. When comparing the two images it
becomes apparent that the maximum temperature is a lot higher for the sim-
ulation in the diode mode and the maximum is reached at another position.
While in MOSFET mode the centre of the die and the bond wire with the
shortest length reaches the maximum, in diode mode, the first stich of the
wires exhibits the highest temperatures.
Figure 93: Current density at the end Figure 94: Current density at the
of the power cycle [A/m²], chip sur- end of the power cycle [A/m²],
face, MOSFET-mode [126] chip surface, diode-mode [126]
Figure 93 and Figure 94 show the current density, while the low voltage
MOSFET is operated in both modes. The scale is the same for both simula-
tions and it becomes apparent that the current density for the diode mode is a
lot higher, which explains the different behaviour of the temperatures. Fur-
thermore, the edge of the die has to carry less current, when a negative tem-
perature coefficient is used.
Figure 95: SAM Images, devices from Test #1 (Figure 78), Tj,max = 150 °C, ton
= 2 s, ID = 108 A, ΔTj = 60 K
The comparison between the SAM images, shown in Figure 95, and the cur-
rent density simulation reveal the apparent relationship between the operation
modes, when contrasted with Figure 85. In the test with superimposed switch-
ing losses, the current density is lower, which leads to a stronger degradation
of the metallization and the bond foot.
Due to the characteristics of Ansys, currently only a temperature dependent

resistance characteristic can be implemented as a property of conductivity,
which clearly leads to results that do not correspond to reality.
Figure 96: Behaviour of a temperature dependent resistance versus actual

diode characteristics
Figure 96 shows the problem with using a resistance characteristic as substi-

tute for the nonlinear diode behaviour regarding the temperature dependency.
The impact in case of a real semiconductor conduction is implemented, but

as the image indicates, it is expected that the current crowding becomes
worse. More recent research data shows that this assumption is correct [128].
Figure 97: Destroyed MOSFET, Figure 98: Simulation hot spot out-
tested in diode mode [126], after side of housing [126]
turning off the main inductance
As Figure 97 and Figure 98 show, the simulation is able to reproduce the

reality. The bond wires are the hottest part of the device and this is also shown
by the device, which was tested until end of function. In the following a short
conclusion of this chapter is given.
The simulation shows that the influence of the operation mode of the
MOSFET can lead to a strong difference in the temperature distribution. The
diode mode exhibits also significant current crowding, especially when a di-
ode characteristic is implemented, which is not based on resistance behav-
iour. The performed simulations can reproduce the reality in the satisfying
way.
8. Conclusion and Outlook 113
8. Conclusion and Outlook
The results show that the test bench is able to test semiconductors with su-
perimposed switching losses. The additionally induced stress caused by the
turn-off voltage and the alternation of the gate voltage had no effect on the
results with the tested semiconductors. The amount of switching losses can
be adjusted by the size of the stray inductances and switching frequency. With
the installation of the current source for fast regulations a higher source volt-
age is also possible, which allows the usage of a higher frequency and a
smaller stray inductance, to reduce the amount of energy per turn-off. This is
important for devices with small chip areas and low switching energies, such
as SiC and GaN semiconductors. The new current source also allows to get
reliable measured values during the measurement time, which is very im-
portant for a statement about the end of life.
The test bench concept shows that it is capable to produce results which are
the same as in the standard power cycling test, as is very important to have a
comparability for certain types of modules. The lifetime for IGBT modules
without baseplate shows no change, when turn off losses are superimposed,
which is caused by the way those devices are degrading. Obviously the age-
ing of the chip solder is not influenced in a visible way, which is not very
surprising, because the temperature distribution in devices tested the standard
way and devices with switching losses have to be very similar because of the
positive temperature coefficient of the forward voltage drop of the IGBT,
subject to the condition, that the bond wires are not overstressed. Therefore,
the occurring stress in the solder layer is equivalent and so is the lifetime,
which is also shown by the results. For the tested modules without baseplate,
no new failure mechanisms and no changes in the semiconductor character-
istics were found in the range from a 60 K to 110 K temperature swing while
the maximum junction temperature was between 105 °C and 150 °C at the
beginning of the test. One of the reasons of the partly high deviation in the
lifetimes are the different sizes of the copper of the DCB as well as the posi-
tion of the semiconductor inside the module. Modules with bigger chips and
a gate in the centre of the semiconductor as well as a more regularly designed
DCB were also tested. The failure mechanism was the same and so was the
influence of the switching losses. This also means that the observed current
dependency is very small, because the RMS value for the current is lower for
the devices tested with switching losses.
For modules with a baseplate a reference test was performed, which lead to
bond wire lift off, which is different to the previously mentioned devices. The
results reveal that there is no change in lifetime for heating times in the sec-
ond range, when this kind of module is tested with superimposed switching
losses. As shown in chapter 1.2 most models for lifetime prediction use a
current dependency. In case that there is a direct current dependency, this
would be revealed in the test carried out, because the root mean square values
of the current is less for the switched devices by a factor of 1.41 due to the
chopped current, under the condition that the turn-off and the turn-on time
are the same. The observed current dependency was very small, for a temper-
ature swing of about 80 K and a maximum junction temperature of 150°C,
while the current was changed from 150 A to effectively 75 A. The reason for
this behaviour is most probably that the current through the bond wire does
not influence the lifetime of the wire in this packaging as predicted by com-
mon lifetime models such as the CIPS model. This should be investigated
further.
The results for modules with baseplate for short turn-on times are quite inter-
esting. In the performed standard power cycling test the current was exceeded
by a factor of 1.84, which lead to bond wire failures, which is an expected
behaviour. The corresponding test with superimposed switching losses does
not only have a lifetime a lot higher, but also a degradation of the solder layer
occurred, which was not as expected. The performed 3D-FEM simulations
reveal that there is a high error in the measured maximum junction tempera-
ture, which was also observed before [117]. Furthermore, it is shown that the
measurement error has only a small current dependency. In both cases (high
current and superimposed switching losses) the main part of the energy is
dissipated within the chip resulting in a high energy density. But with very
high current also the bond wires generate more heat and therefore a small
difference can be observed. Nevertheless, this shows that a current depend-
ency is prevailing, at least if the current is exceeded. The SAM images did
show an uncommon mode of failure. The solder layer was degraded, but the
crack grow started within the area of the chip, but not from the centre. For
some IGBTs the pattern shows that only a specific, relatively clearly sepa-
rated part features a crack grow. This concludes with the observed unsteady
course of the test. This failure mode should be investigated further.
The results of transfer moulded devices show a clear difference conversely to

the tests with modules, except for MOSFETs made of SiC. In case standard
packaging technology is used for SiC dies, the higher mismatch of the coef-
ficient of thermal expansion (CTE) is named as reason for a lower lifetime
and a higher rate of solder degradation. In the TO-package such a kind of
degradation has not been observed until now, neither in SiC nor with silicon
devices, which is quite interesting, because the mismatch between the lead
frame made of copper and the die is a lot higher than the mismatch between
a DCB and the die. So obviously other influencing factors from material sci-
ence have to be considered, such as stiffness. Still, the results for SiC
MOSFETs in the TO-247 package show no change, if a test with switching
losses is performed compared to a DC-test. In case this kind of device is pack-
aged in a module, the same behaviour as for baseplate-less modules is ex-
pected, if the same packaging technology is used. For MOSFETs made of
SiC the shift of the gate threshold voltage has a major influence on the char-
acteristics of the device. Because of the superimposed switching losses addi-
tional stress is induced, which can lead to a positive or negative shift of the
gate threshold voltage. This should be subject to further investigations, as
well as tests with SiC-MOSFETs packed in modules.
IGBTs in transfer moulded packages have a higher current dependency than

IGBTs packaged in modules. The test with superimposed switching losses
shows this behaviour in a very clear way and the main failure mechanism is
bond wire heel crack. The reasons why a heel crack is the main cause of fail-
ure in transfer moulded devices are not quite clear, but it is expected that the
used moulding material plays a major role as well as the wire geometry. The
tested semiconductors have a very high lifetime with more than five times the
value predicted by the CIPS model. The switched devices show a higher
lifetime compared to the continuously turned on semiconductors, but if the
current dependency of the lifetime for this kind of devices is considered, the
results are close to each other within manufacturing uncertainties. A depend-
ency has been found within a temperature swing from 70 to 80 K and a max-
imum junction temperature of 145 to 155 °C, while the current was changed
from 56 A to 30 A. One of the tests did not show a higher lifetime for the
switched IGBTs, which was not expected. A failure analysis revealed bond
wire lift off as mechanism, which is similar to IGBTs packaged in a module
with baseplate. These devices were the only one from the tested, which
showed this behaviour. The voltage class was lower with 600 V, than the pre-
viously tested and the manufacturer used only one bond wire, resulting in a
high current per bond. The publication [59] claims that the developed model
and current dependency can also be applied for the devices with lower break-
down voltage. This should be investigated further.
Low voltage MOSFETs, with a blocking capability of less than 80V were
tested in module style packaging and in TO-housing. Due to their character-
istics it is very challenging to perform an accelerated lifetime test using the
MOSFET-forward mode with nominal gate voltage and current. As an exam-
ple the test of the IRFP4004 can be used, see chapter 6.1. As the datasheet
gives, the package is limited to 195A, but it is very challenging to bring such
high a current through the small pins into the device. For a test 124 A are
used, which resulted in an temperature swing of 20 K without superimposed
switching losses and it can therefore not be used as an accelerated test. Be-
cause of this behaviour, this kind of devices are often tested through the in-
verse diode, which provide easily enough losses to get a reasonable fast life-
time test. The fact that this operation mode will lead to a negative temperature
coefficient is mostly ignored or has to be accepted. A test with very low gate
voltage, which was also performed in this work, can also give enough losses,
but it has to be considered that the temperature coefficient is more negative
compared to the inverse diode mode. Due to this reason a power cycling test
with superimposed switching losses was performed and the ratio between DC
to switching losses was about 1:3, which is comparable to real applications.
The results show that a higher number of cycles can be achieved, in case the
test method with switching losses is used. A current dependency was found,
which was similar to the one observed for IGBTs in transfer moulded devices,
within a temperature swing from 60 to 80 K and a maximum junction temper-

ature of 145-155 °C, while the current was changed from 124 A to 64 A. The
difference between “MOSFET-forward with low gate voltage”-mode and in-
verse diode mode can be traced to back to current crowding caused by the
higher negative temperature coefficient. Nevertheless, it is also possible that
the observed current dependency between MOSFET-forward mode and in-
verse diode mode is influenced by current crowding, which would result in a
higher value. The performed simulation was able to reproduce the different
behaviours in a sufficient way, despite just a resistance characteristic could
be used to represent the semiconductor from the electrical point of view.
More recent approaches use a better characteristic for the diode behaviour,
which will lead to even more accurate results and a better understanding.
For the future more test on SiC devices should be performed in TO and mod-
ule packaging to be able to find a clearer statement about the dependency on
switching losses. Furthermore, a test with GaN devices is a good opportunity
to make sure that this type is able to survive a long time in application. Right
until now, the user has to stay within the specified blocking voltage, other-
wise the device can be destroyed permanently. Furthermore, hard switching,
as performed with the superimposed switching losses, is still an issue with
GaN semiconductors [129].
9. Acknowledgement 118
9. Acknowledgement
This research work has been carried out during 2016 and 2020 at the institute
of Power Electronics and Electromagnetic Compatibility, Faculty of Electri-
cal Engineering and Information Technology, Chemnitz University of Tech-
nology.
At first I would like to thank Prof. Dr. Josef Lutz for his guidance, advisory
support and his critical thoughts about this work. His way of thinking and
analysing things will certainly contribute in my future work.
In this context I would also like to thank Dr. Reinhold Bayerer for the discus-
sions and his strong technical contribution as well as the initiation for this
project.
The colleagues and students of the Chair of Power Electronics and EMC also
deserve a thank you, in particular Cesare Künzel whom I have to thank for
his untiring dedication for this project and this thesis.
I also like to thank Christian Herold, the supervisor of my master thesis,

which was the basis of this work.
Christian Schwabe also deserves big thanks due to his contributions and work
for the performed tests as well as great contribution for several papers. The
results of his master thesis are also part of this work, especially chapter 7.
I would also like to thank the ECPE (European Center for Power Electronics)
for their financial support in the form of two projects as part of their research
programme.
My wife Miriam deserves a special thank for her patience and her support.
Without her this work would probably not exist.
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Appendix 136
Appendix
Figure A. 1: circuit diagram of gate drive unit for power cycling

Appendix 137
Figure A. 2: Clamping, with Lσ=400µH, red = VCE(100 V/div),

blue = IC (5 A/div), orange = IZ_Rog (1 A/div), purple = EZ (20 mWs/div),
5 µs/div
Appendix 138
Figure A. 3: Isolation Amplifier circuit

Appendix 139
Figure A. 4: Isolation Amplifier board

Appendix 140
Figure A. 5: Oscilloscope record of the overlap process at TMeasure = 500 µs,

Red VCE in 100 V/div, Blue IC in 5 A/div, 500 µs/div
Name Material Therm. Conduc- Specific heat ca- Specific

tivity [W/m∙K] pacity [J/kg∙K] resistance [µΩ∙m]
Metalliza- Aluminium 237 @ 0 °C 837 @ 0 °C 0.0273 @ 17 °C
tion / Bond 240 @ 100 °C 984 @ 200 °C 0.034 @ 75 °C
Chip Silicon 172.76 @ 0 °C 691 @ 0 °C 106 @ 25 °C
136.53 @ 60 °C 825 @ 200 °C 984 @ 125 °C
118.84 @ 100 °C
Solder Sn96.5Ag3.5 57.3 @ 25 °C 219@ 0 °C 0,133 @ 50 °C
Connectors / Copper 398 @ 27 °C 381 @ 0 °C 0.0173 @ 25 °C
Baseplate 357 @ 727 °C 415 @ 100 °C 0.0206 @ 75 °C
TIM KU-CG 1.9@ 25 °C
Figure A. 6: Material data for simulation of Si MOSFET
Figure A. 7: Course of module #0427, IGBT 1; ton = 2 s; IC = 150 A;

Tj,max = 125 °C, fSwitch = 22000 Hz
141
Figure A. 8: SAM-Image of #0054, ΔTJ = 50 K, Econo-package, test condi-

tions see Figure 41

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Power Cycling With Switching Losses

Von der Fakultät für Elektrotechnik und Informationstechnik der Techni-

zur Erlangung des akademischen Grades

von M.Sc. Peter Seidel

Tag der Einreichung: 03.07.2020

Gutachter: Prof. Dr.-Ing. Josef Lutz

Tag der Verteidigung: 07.12.2020

Titel: Power Cycling with Switching Losses

Dissertation an der Fakultät für Elektrotechnik der Technischen Universi-

Power electronics, Semiconductor, Power cycling test, Switching losses,

4.6.2. Measurement Algorithm .................................................................. 60

Symbols and Abbreviations

S Source, semiconductor or blocking

1. Power Cycling Lifetime

1.1. Power Cycling-induced Ageing Mechanisms and

1.1.1. Overview of Packaging Technologies and their

Figure 1: Schematic structure of a power module

As Figure 1 shows, the chip is attached to a copper-clad (DCB) ceramics by

improved packaging technologies, such as sintering the chip or copper bond

Figure 2: Transistor outline package [1]

A sketch of the structure of this type of devices is shown in Figure 2. Its

Figure 3: Schematic structure of press pack IGBT [2]

Figure 4: Deformation of a Press Pack under load (factor: 500) [4]

The consequences, as shown in Figure 4, are poorly or no longer electrically

1.1.2. Failure Mechanisms in Power Modules and Discrete

As already mentioned in the previous chapter, the modules in standard pack-

1.1.3. Basic Structure of a Test Bench for DC Power Cycling

Figure 5: Schematic representation of the structure of a power cycling test

cycled by constantly switching on and off. For these reasons, an improved

Auxiliary Switch Auxiliary Switch Auxiliary Switch

Low Voltage Phase 1 Phase 2

Figure 6: Schematic representation of the structure of a power cycling test

1.1.4. Modifications for SiC MOSFET Operation

In particular, silicon carbide MOSFETs, which have become increasingly us-

Figure 7: Proposed trench SiC MOSFET from Infineon AG with asymmetric

VGate DUT 1,2...N

VGate Auxiliary Switch

Figure 8: Pulse pattern for MOSFET power cycling - load current in

1.1.5. Measurement Accuracy, Limits and Consequences

Figure 10: Measurement time points and behaviour of semiconductor with

1.1.6. Thermal Resistance and Thermal Impedance Spec-

𝑇𝑇𝑗𝑗,𝑚𝑚𝑚𝑚𝑚𝑚 − 𝑇𝑇𝑠𝑠,ℎ𝑜𝑜𝑜𝑜 (1.1)

𝑇𝑇𝐽𝐽 (𝑡𝑡) − 𝑇𝑇𝑠𝑠,ℎ𝑜𝑜𝑜𝑜 (1.2)

Figure 11: Measured transient thermal resistance at the beginning and at

resistance. When the device then is heated up completely for a ZTH-measure-

1.2. Empirical Power Cycling Lifetime Models

Recent publications on transfer moulded devices show clear differences to

𝛥𝛥𝛥𝛥 = 𝛥𝛥𝜀𝜀𝑝𝑝𝑝𝑝 + 𝛥𝛥𝜀𝜀𝑒𝑒𝑒𝑒 + 𝛥𝛥𝜀𝜀𝑐𝑐𝑐𝑐 (1.9)

𝛥𝛥𝛥𝛥 = 𝛥𝛥𝜀𝜀𝑝𝑝𝑝𝑝 + 𝛥𝛥𝜀𝜀𝑒𝑒𝑒𝑒 (1.10)

In order to immediately meet some of these limitations, which are shown in

2. Specific Limitations in Conditions for some

The behaviour of the IGBTs is similar to that of most MOSFET types,

3. Approaches of an Application-close Power

The approach of using switching losses to generate power dissipation and

Figure 12: Simplified circuit for inverter-like operation [74]

approach, but which reveals a number of problems. Just as in the previous

0.5 ⋅ 470 pF + 300pF ≅ 500pF (3.1)

τ = R ⋅ C = 360 k ⋅ 0.5 n = 180 µs (3.2)

Due to the construction, as shown in Figure 15, up to six half-bridge modules

If this concept is further developed, a variable proportion of switching losses

4. New Test Bench Concept with an Adjustable

4.1. Basics for Switching

Figure 16: Schematic of the switch-on behaviour of a MOSFET [1]

Figure 16 schematically shows the turn-on behaviour of a MOSFET. Switch-