Area reserved for document binding

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3DSPWR*
3DSPWR* 3DSPRD*
3DSPRD* 3DSPRCS*
3DSPRCS* 3DSPD[23:0]
3DSPD[23:0] 3DSPA0
3DSPA0 3DSPIRQB
3DSPIRQB 3DSPIRQA
3DSPIRQA 3DSPHCS*
M1 3DSPHCS* HA[2:0]
DSPHA[2:0] HD[7:0]
P17100-G HD[7:0]

HA[2:0] DSPRESET* DSPCLK0 DSPRESET* HA[2:0]

0DSPHCS* HD[7:0] CLK DSPCLK3CLK HD[7:0]
0DSPHCS* DSPHWR* HCS HCS
DSPHWR* DSPHRD* HWR* TCK TCK HWR*
DSPHRD* HRD* TMS TMS HRD*
HRRQ TDI TDI HRRQ NC
MOSI TDO TDO MOSI NC
MISO/SDA MISO/SDA NC
0DSPIRQA SCK SCK NC
TDI 0DSPIRQA 0DSPIRQB IRQA DSP0 DSP3 IRQA
TDI TDO_DSP 0DSPIRQB IRQ0 IRQB HCKT HCKT IRQB IRQ3
TDO_DSP TCK TDI HTRQ SCKT SCKT HTRQ
TCK TMS TCK FST FST
TMS TDO_FPGA TMS DSP_MODE HCKR HCKR DSP_MODE
TDO_FPGA TEST_RESET TDO 0DSPA0 SCKR SCKR
TEST_RESET TEST_RESET 0DSPA0 0DSPD[23:0] A0 FSR FSR A0
0DSPD[23:0] D[23:0] SDO5/SDI0 SDO5/SDI0 D[23:0]

SDO5_1/SDI0_1
SDO4_1/SDI1_1
SDO2_1/SDI3_1

SDO2_1/SDI3_1
SDO4_1/SDI1_1
SDO5_1/SDI0_1
ATMEL_RESET* 0DSPRCS*
ATMEL_RESET* MOSI 0DSPRCS* 0DSPRD* RCS SDO4/SDI1 SDO4/SDI1 RCS
MOSI MISO/SDA 0DSPRD* 0DSPWR* RD SDO3/SDI2 SDO3/SDI2 RD
MISO/SDA SCK 0DSPWR* WR WR

SCKR_1

SCKR_1
SCKT_1

SCKT_1
SDO0_1

SDO0_1
SCK SDO1 SDO1

FSR_1

FSR_1
FST_1

FST_1
SCL
SCL SDA
SDA

FPGA_PROGRAM
FPGA_PROGRAM* FPGA_DONE FPGA_PROGRAM*
FPGA_DONE ATMELCLK FPGA_DONE DSP_MODE
ATMELCLK DSPRESET* ATMELCLK FPGA
DSPRESET* RYBY DSPRESET*
RYBY

RESET* SDA RYBY

RESET* DHRST RESET* SCL RCS0* RESET*
DHRST SRESET* DHRST RCS0* SDCLK0 RCS0*

SCKT_1
FST_1
SCKR_1
FSR_1
SDO5_1/SDI0_1
SDO4_1/SDI1_1
SDO2_1/SDI3_1

SDO0_1

SDO0_1

SDO2_1/SDI3_1
SDO4_1/SDI1_1
SDO5_1/SDI0_1
FSR_1
SCKR_1
FST_1
SCKT_1
SRESET* SRESET* SDCLK0 SDCLK1 SDCLK0
SDCLK1 DQM[7:0] SDCLK1
RS232_RX DQM[7:0] SDCAS* DQM[7:0] 1DSPWR* SDO1 SDO1
RS232_RX RS232_TX RS232_RX SDCAS* SDRAS* SDCAS* 1DSPWR* 1DSPRD* WR WR
RS232_TX RS232_TX SDRAS* SDCKE SDRAS* 1DSPRD* 1DSPRCS* RD SDO3/SDI2 SDO3/SDI2 RD
SDCKE SDCS0* SDCKE 1DSPRCS* 1DSPD[23:0] RCS SDO4/SDI1 SDO4/SDI1 RCS
SDCS0* DP[7:0] SDCS0* 1DSPD[23:0] 1DSPA0 D[23:0] SDO5/SDI0 SDO5/SDI0 D[23:0]
DP[7:0] SDBA[1:0] DP[7:0] 1DSPA0 A0 FSR FSR A0
SDBA[1:0] SDMA[11:0] SDBA[1:0] SCKR SCKR
SDMA[11:0] DSP_MODE HCKR HCKR DSP_MODE
TDI_PPC D[63:0] IRQ1 FST FST IRQ2
TDI_PPC TCK_PPC TDI FOE* 1DSPIRQB HTRQ SCKT SCKT HTRQ
TCK_PPC TMS_PPC TCK WE* 1DSPIRQB 1DSPIRQA IRQB HCKT HCKT IRQB
TMS_PPC TDO_PPC TMS PPC_MEM 1DSPIRQA IRQA DSP1 DSP2 IRQA
TDO_PPC TRST_PPC TDO NC SCK SCK NC
RESET* TRST_PPC TRST* AS* NC MISO/SDA MISO/SDA NC
AS* AS* NC MOSI TDO TDO MOSI NC
INTERFACE NC HRRQ TDI TDI HRRQ NC
SDMA10 HRD* TMS TMS HRD*
C/BE[3:0] SDMA[11:0] SDMA[8:4] SDMA10 1DSPHCS* HWR* TCK TCK HWR*
RESET* C/BE[3:0] DEVSEL C/BE[3:0] SDMA[11:0] D[63:0] SDMA[8:4] 1DSPHCS* HCS DSPCLK1 DSPCLK2 HCS
DEVSEL FRAME DEVSEL D[63:0] FOE* D[63:0] HD[7:0] CLK CLK HD[7:0]
FRAME IRDY FRAME FOE* WE* FOE* HA[2:0] DSPRESET* DSPRESET* HA[2:0]
IRDY IRDY WE* RCS1* WE*
AD[31:0] RCS1* SDCLK2 RCS1*
AD[31:0] PAR AD[31:0] SDCLK2 SDCLK2 2DSPHCS*
PAR REQ PAR IRQ[4:0] 2DSPHCS* 2DSPIRQA
REQ GNT REQ0 IRQ[4:0] 2DSPIRQA 2DSPIRQB
FIREWIRE GNT PERR GNT0 2DSPIRQB 2DSPA0
PERR SERR PERR 2DSPA0 2DSPD[23:0]
SERR STOP SERR 2DSPD[23:0] 2DSPRCS*
STOP TRDY STOP 2DSPRCS* 2DSPRD*
TRDY PCLK TRDY PPC 2DSPRD* 2DSPWR*
PCLK PCLK 2DSPWR*

IRQ4
INTA_FPGA DSPCLK[3:0]
DSPCLK[3:0]
Designer
TC Electronic A/S MAR
Title Module title
POCO FW POCOFW
Number Revision Previous page
P17100 GAE 1
Date Filename Page / of
8-28-2006_21:02 1 / 10
 Area reserved for document binding

Best printed and viewed on sheetsize A4

D+3V3

C573 C574 C575 C576 C577 C8 C579 C580 C581 C582 C583 C584 C585 C9 C587

100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n

DGND D+3V3
IC17
A16 35 27
A15 34 A18 VCC1 9
D+1V8 A14 33 A17 VCC2
D+3V3 A13 32 A16 C496 C497
A12 24 A15
C503 C590 C589 C591 C592 C593 A11 23 A14 100n 100n
A10 22 A13

126

129
119
111
103
45
18
91
56

95
49
20

86
80
74

57
65

38

25
10u 100n 100n 100n 100n 100n A9 A12

8
C502 21
A8 20 A11 DGND

VCCP
VCCQL3
VCCQL2
VCCQL1
VCCQL0
VCCQH2
VCCQH1
VCCQH0

VCCA2
VCCA1
VCCA0
VCCD3
VCCD2
VCCD1
VCCD0
VCCC1
VCCC0

VCCH

VCCS0
VCCS1
22n A18 18 A10
A7 17 A9
A8

TP94
DGND DGND A6 16 30 D7
46 A5 15 A7 D7 29 D6
TP84 PCAP 55 A4 14 A6 D6 26 D5
EXTAL CLK A3 5 A5 D5 25 D4
23 99 A17 A2 4 A4 D4 12 D3
HRRQ HTRQ 24 HACK/HRRQ/PB15 A17 98 A16 A1 3 A3 D3 11 D2
HTRQ HCS 30 HOREQ/HTREQ/PB14 A16 97 A15 A0 2 A2 D2 8 D1
HCS HWR* 21 HCS*/HA10/PB13 A15 94 A14 A17 1 A1 D1 7 D0
HWR* HRD* 22 HDS*/HWR*/PB12 A14 93 A13 A[18:0] A0 D0
HRD* HA[2:0] HA2 31 HRW*/HRD*/PB11 A13 92 A12
HA[2:0] HA1 32 HA2/HA9/PB10 A12 89 A11 6
HA0 33 HA1/HA8/PB9 A11 88 A10 31 CE 10
HD[7:0] HD7 34 HA0/HAS/PB8 A10 85 A9 13 OE GND1 28
HD[7:0] HD6 35 H7 A9 84 A8 WE GND2
HD5 36 H6 A8 83 A7 512KX8
HD4 37 H5 A7 82 A6 DGND
HD3 40 H4 A6 79 A5 D+3V3
HD2 41 H3 A5 78 A4 IC18
HD1 42 H2 A4 77 A3 A16 35 27
HD0 43 H1 A3 76 A2 A15 34 A18 VCC1 9
NC 3 H0 A2 73 A1 A14 33 A17 VCC2
HREQ* A1 72 A0 A0 A13 32 A16 C498 C499
143 A0 A0 A12 24 A15
MOSI R99 2 MOSI A11 23 A14 100n 100n
D+3V3 144 SS* 70 CS0 A10 22 A13
MISO/SDA 10k MISO AA0/RAS0* A12
1 69 A18 A9 21
SCK SCK AA1/RAS1* 51 R606 A8 20 A11
AA2/RAS2* RCS A18 18 A10 DGND
27R4 A9
15 52 NC A7 17
SCKR 13 SCKR IC20 CAS* 68 R616 A6 16 A8 30 D15
FSR 60 FSR RD* 67 R617 A5 15 A7 D7 29 D14
SCKR_1 SCKR_1 WR* 27R4 A6 D6
59 DSP56367 27R4 A4 14 26 D13
FSR_1 17 FSR_1 A3 5 A5 D5 25 D12
HCKR 14 HCKR 133 D23 A2 4 A4 D4 12 D11
SCKT 53 SCKT D23 132 D22 R607 A1 3 A3 D3 11 D10
SCKT_1 12 SCKT_1 D22 131 D21 R608 RD A0 2 A2 D2 8 D9
FST FST D21 27R4 WR A1 D1
50 128 D20 27R4 A17 1 7 D8
FST_1 16 FST_1 D20 125 D19 A0 D0
HCKT 11 HCKT D19 124 D18
SDO5/SDI0 10 SDO5/SDI0 D18 123 D17 6
SDO4/SDI1 48 SDO4/SDI1 D17 122 D16 31 CE 10
SDO5_1/SDI0_1 138 SDO5_1/SDI0_1 D16 121 D15 13 OE GND1 28
SDO4_1/SDI1_1 7 SDO4_1/SDI1_1 D15 118 D14 WE GND2
SDO3/SDI2 6 SDO3/SDI2/SDO3_1/SDI2_1 D14 117 D13 512KX8
SDO2_1/SDI3_1 5 SDO2/SDI3/SDO2_1/SDI3_1 D13 116 D12 DGND
SDO1 4 SDO1/SDO1_1 D12 115 D11 D+3V3
SDO0_1 R557 28 SDO0/SDO0_1 D11 114 D10 IC19
DSP1 DGND ACI D10
LD6 10k NC 27 113 D9 A16 35 27
680R 29 ADO D9 110 D8 A15 34 A18 VCC1 9
D+3V3 TIO0 D8 109 D7 A14 33 A17 VCC2
R565 R558 61 D7 A16
108 D6 A13 32 C500 C501
DGND PINIT/_NMI D6 107 D5 A12 24 A15
TP81 10k D5 A14
44 106 D4 A11 23 100n 100n
DSPRESET* RESET* D4 105 D3 A10 22 A13
137 D3 102 D2 A9 21 A12
IRQA 136 MODA/IRQA* D2 101 D1 A8 20 A11
IRQB 135 MODB/IRQB* D1 100 D0 D[23:0] A18 18 A10 DGND
DSP_MODE 134 MODC/IRQC* D0 A7 17 A9
MODD/IRQD* A6 16 A8 30 D23
141 62 A5 15 A7 D7 29 D22
TCK 140 TCK TA* 63 R553 DGND A4 14 A6 D6 26 D21
TDI TDI BR* NC 10k A5 D5
142 71 A3 5 25 D20
TMS NOT_USED 139 TMS BG* 64 R554 DGND A2 4 A4 D4 12 D19
TDO TDO BB* 10k D+3V3 A3 D3
R552
10k A1 3 11 D18
R102 A0 2 A2 D2 8 D17
A17 1 A1 D1 7 D16
GNDQ3
GNDQ2
GNDQ1
GNDQ0

GNDA3
GNDA2
GNDA1
GNDA0

GNDD3
GNDD2
GNDD1
GNDD0

GNDC1
GNDC0

0R0
GNDS1
GNDS0
GNDH

A0 D0
GNDP

6
31 CE 10
47

127
90
54
19

96
87
81
75

130
120
112
104

66
58

39
26
9

13 OE GND1 28
WE GND2
512KX8
DGND
short stuff with 128kx8 SRAM
DGND
D[23:0]
Designer
TC Electronic A/S MAR
Title Module title
POCO FW DSP
Number Revision Previous page
P17100 GAE 1
Date Filename Page / of
8-28-2006_21:02 10 / 10
 Area reserved for document binding

Best printed and viewed on sheetsize A4

D+3V3

C529 C530 C531 C532 C533 C553 C535 C536 C537 C538 C539 C540 C541 C556 C543

100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n

DGND D+3V3
IC42
A16 35 27
A15 34 A18 VCC1 9
D+1V8 A14 33 A17 VCC2
D+3V3 A13 32 A16 C383 C409
A12 24 A15
C460 C546 C545 C547 C548 C549 A11 23 A14 100n 100n
A10 22 A13

126

129
119
111
103
45
18
91
56

95
49
20

86
80
74

57
65

38

25
10u 100n 100n 100n 100n 100n A9 A12

8
C468 21
A8 20 A11 DGND

VCCP
VCCQL3
VCCQL2
VCCQL1
VCCQL0
VCCQH2
VCCQH1
VCCQH0

VCCA2
VCCA1
VCCA0
VCCD3
VCCD2
VCCD1
VCCD0
VCCC1
VCCC0

VCCH

VCCS0
VCCS1
22n A18 18 A10
A7 17 A9
DGND DGND A6 16 A8 30 D7

TP4
46 A5 15 A7 D7 29 D6
TP563 PCAP 55 A4 14 A6 D6 26 D5
EXTAL CLK A3 5 A5 D5 25 D4
23 99 A17 A2 4 A4 D4 12 D3
HRRQ HTRQ 24 HACK/HRRQ/PB15 A17 98 A16 A1 3 A3 D3 11 D2
HTRQ HCS 30 HOREQ/HTREQ/PB14 A16 97 A15 A0 2 A2 D2 8 D1
HCS HWR* 21 HCS*/HA10/PB13 A15 94 A14 A17 1 A1 D1 7 D0
HWR* HRD* 22 HDS*/HWR*/PB12 A14 93 A13 A[18:0] A0 D0
HRD* HA[2:0] HA2 31 HRW*/HRD*/PB11 A13 92 A12
HA[2:0] HA1 32 HA2/HA9/PB10 A12 89 A11 6
HA0 33 HA1/HA8/PB9 A11 88 A10 31 CE 10
HD[7:0] HD7 34 HA0/HAS/PB8 A10 85 A9 13 OE GND1 28
HD[7:0] HD6 35 H7 A9 84 A8 WE GND2
HD5 36 H6 A8 83 A7 512KX8
HD4 37 H5 A7 82 A6 DGND
HD3 40 H4 A6 79 A5 D+3V3
HD2 41 H3 A5 78 A4 IC43
HD1 42 H2 A4 77 A3 A16 35 27
HD0 43 H1 A3 76 A2 A15 34 A18 VCC1 9
NC 3 H0 A2 73 A1 A14 33 A17 VCC2
HREQ* A1 72 A0 A0 A13 32 A16 C410 C411
143 A0 A0 A12 24 A15
MOSI R31 2 MOSI A11 23 A14 100n 100n
D+3V3 144 SS* 70 CS0 A10 22 A13
MISO/SDA 10k MISO AA0/RAS0* A12
1 69 A18 A9 21
SCK SCK AA1/RAS1* 51 R600 A8 20 A11
AA2/RAS2* RCS A18 18 A10 DGND
27R4 A9
15 52 NC A7 17
SCKR 13 SCKR IC1 CAS* 68 R612 A6 16 A8 30 D15
FSR 60 FSR RD* 67 R613 A5 15 A7 D7 29 D14
SCKR_1 SCKR_1 WR* 27R4 A6 D6
59 DSP56367 27R4 A4 14 26 D13
FSR_1 17 FSR_1 A3 5 A5 D5 25 D12
HCKR 14 HCKR 133 D23 A2 4 A4 D4 12 D11
SCKT 53 SCKT D23 132 D22 R601 A1 3 A3 D3 11 D10
SCKT_1 12 SCKT_1 D22 131 D21 R602 RD A0 2 A2 D2 8 D9
FST FST D21 27R4 WR A1 D1
50 128 D20 27R4 A17 1 7 D8
FST_1 16 FST_1 D20 125 D19 A0 D0
HCKT 11 HCKT D19 124 D18
SDO5/SDI0 10 SDO5/SDI0 D18 123 D17 6
SDO4/SDI1 48 SDO4/SDI1 D17 122 D16 31 CE 10
SDO5_1/SDI0_1 138 SDO5_1/SDI0_1 D16 121 D15 13 OE GND1 28
SDO4_1/SDI1_1 7 SDO4_1/SDI1_1 D15 118 D14 WE GND2
SDO3/SDI2 6 SDO3/SDI2/SDO3_1/SDI2_1 D14 117 D13 512KX8
SDO2_1/SDI3_1 5 SDO2/SDI3/SDO2_1/SDI3_1 D13 116 D12 DGND
SDO1 4 SDO1/SDO1_1 D12 115 D11 D+3V3
SDO0_1 R496 28 SDO0/SDO0_1 D11 114 D10 IC44
DSP2 DGND ACI D10
LD21 10k NC 27 113 D9 A16 35 27
680R 29 ADO D9 110 D8 A15 34 A18 VCC1 9
D+3V3 TIO0 D8 109 D7 A14 33 A17 VCC2
R375 R497 61 D7 A16
108 D6 A13 32 C412 C413
DGND PINIT/_NMI D6 107 D5 A12 24 A15
TP52 10k D5 A14
44 106 D4 A11 23 100n 100n
DSPRESET* RESET* D4 105 D3 A10 22 A13
137 D3 102 D2 A9 21 A12
IRQA 136 MODA/IRQA* D2 101 D1 A8 20 A11
IRQB 135 MODB/IRQB* D1 100 D0 D[23:0] A18 18 A10 DGND
DSP_MODE 134 MODC/IRQC* D0 A7 17 A9
MODD/IRQD* A6 16 A8 30 D23
141 62 A5 15 A7 D7 29 D22
TCK 140 TCK TA* 63 R289 DGND A4 14 A6 D6 26 D21
TDI TDI BR* NC 10k A5 D5
142 71 A3 5 25 D20
TMS NOT_USED 139 TMS BG* 64 R288 DGND A2 4 A4 D4 12 D19
TDO TDO BB* 10k D+3V3 A3 D3
R293
10k A1 3 11 D18
R7 A0 2 A2 D2 8 D17
A17 1 A1 D1 7 D16
GNDQ3
GNDQ2
GNDQ1
GNDQ0

GNDA3
GNDA2
GNDA1
GNDA0

GNDD3
GNDD2
GNDD1
GNDD0

GNDC1
GNDC0

0R0
GNDS1
GNDS0
GNDH

A0 D0
GNDP

6
31 CE 10
47

127
90
54
19

96
87
81
75

130
120
112
104

66
58

39
26
9

13 OE GND1 28
WE GND2
512KX8
DGND
short stuff with 128kx8 SRAM
DGND
D[23:0]
Designer
TC Electronic A/S MAR
Title Module title
POCO FW DSP
Number Revision Previous page
P17100 GAE 1
Date Filename Page / of
8-28-2006_21:02 10 / 10
 Area reserved for document binding

Best printed and viewed on sheetsize A4

D+3V3

C594 C595 C596 C597 C598 C10 C600 C601 C602 C603 C604 C605 C606 C11 C608

100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n

DGND D+3V3
IC21
A16 35 27
A15 34 A18 VCC1 9
D+1V8 A14 33 A17 VCC2
D+3V3 A13 32 A16 C509 C510
A12 24 A15
C516 C611 C610 C612 C613 C614 A11 23 A14 100n 100n
A10 22 A13

126

129
119
111
103
45
18
91
56

95
49
20

86
80
74

57
65

38

25
10u 100n 100n 100n 100n 100n A9 A12

8
C515 21
A8 20 A11 DGND

VCCP
VCCQL3
VCCQL2
VCCQL1
VCCQL0
VCCQH2
VCCQH1
VCCQH0

VCCA2
VCCA1
VCCA0
VCCD3
VCCD2
VCCD1
VCCD0
VCCC1
VCCC0

VCCH

VCCS0
VCCS1
22n A18 18 A10
A7 17 A9
A8

TP95
DGND DGND A6 16 30 D7
46 A5 15 A7 D7 29 D6
TP117 PCAP 55 A4 14 A6 D6 26 D5
EXTAL CLK A3 5 A5 D5 25 D4
23 99 A17 A2 4 A4 D4 12 D3
HRRQ HTRQ 24 HACK/HRRQ/PB15 A17 98 A16 A1 3 A3 D3 11 D2
HTRQ HCS 30 HOREQ/HTREQ/PB14 A16 97 A15 A0 2 A2 D2 8 D1
HCS HWR* 21 HCS*/HA10/PB13 A15 94 A14 A17 1 A1 D1 7 D0
HWR* HRD* 22 HDS*/HWR*/PB12 A14 93 A13 A[18:0] A0 D0
HRD* HA[2:0] HA2 31 HRW*/HRD*/PB11 A13 92 A12
HA[2:0] HA1 32 HA2/HA9/PB10 A12 89 A11 6
HA0 33 HA1/HA8/PB9 A11 88 A10 31 CE 10
HD[7:0] HD7 34 HA0/HAS/PB8 A10 85 A9 13 OE GND1 28
HD[7:0] HD6 35 H7 A9 84 A8 WE GND2
HD5 36 H6 A8 83 A7 512KX8
HD4 37 H5 A7 82 A6 DGND
HD3 40 H4 A6 79 A5 D+3V3
HD2 41 H3 A5 78 A4 IC22
HD1 42 H2 A4 77 A3 A16 35 27
HD0 43 H1 A3 76 A2 A15 34 A18 VCC1 9
NC 3 H0 A2 73 A1 A14 33 A17 VCC2
HREQ* A1 72 A0 A0 A13 32 A16 C511 C512
143 A0 A0 A12 24 A15
MOSI R100 2 MOSI A11 23 A14 100n 100n
D+3V3 144 SS* 70 CS0 A10 22 A13
MISO/SDA 10k MISO AA0/RAS0* A12
1 69 A18 A9 21
SCK SCK AA1/RAS1* 51 R609 A8 20 A11
AA2/RAS2* RCS A18 18 A10 DGND
27R4 A9
15 52 NC A7 17
SCKR 13 SCKR IC24 CAS* 68 R618 A6 16 A8 30 D15
FSR 60 FSR RD* 67 R619 A5 15 A7 D7 29 D14
SCKR_1 SCKR_1 WR* 27R4 A6 D6
59 DSP56367 27R4 A4 14 26 D13
FSR_1 17 FSR_1 A3 5 A5 D5 25 D12
HCKR 14 HCKR 133 D23 A2 4 A4 D4 12 D11
SCKT 53 SCKT D23 132 D22 R610 A1 3 A3 D3 11 D10
SCKT_1 12 SCKT_1 D22 131 D21 R611 RD A0 2 A2 D2 8 D9
FST FST D21 27R4 WR A1 D1
50 128 D20 27R4 A17 1 7 D8
FST_1 16 FST_1 D20 125 D19 A0 D0
HCKT 11 HCKT D19 124 D18
SDO5/SDI0 10 SDO5/SDI0 D18 123 D17 6
SDO4/SDI1 48 SDO4/SDI1 D17 122 D16 31 CE 10
SDO5_1/SDI0_1 138 SDO5_1/SDI0_1 D16 121 D15 13 OE GND1 28
SDO4_1/SDI1_1 7 SDO4_1/SDI1_1 D15 118 D14 WE GND2
SDO3/SDI2 6 SDO3/SDI2/SDO3_1/SDI2_1 D14 117 D13 512KX8
SDO2_1/SDI3_1 5 SDO2/SDI3/SDO2_1/SDI3_1 D13 116 D12 DGND
SDO1 4 SDO1/SDO1_1 D12 115 D11 D+3V3
SDO0_1 R571 28 SDO0/SDO0_1 D11 114 D10 IC23
DSP3 DGND ACI D10
LD4 10k NC 27 113 D9 A16 35 27
680R 29 ADO D9 110 D8 A15 34 A18 VCC1 9
D+3V3 TIO0 D8 109 D7 A14 33 A17 VCC2
R579 R572 61 D7 A16
108 D6 A13 32 C513 C514
DGND PINIT/_NMI D6 107 D5 A12 24 A15
TP82 10k D5 A14
44 106 D4 A11 23 100n 100n
DSPRESET* RESET* D4 105 D3 A10 22 A13
137 D3 102 D2 A9 21 A12
IRQA 136 MODA/IRQA* D2 101 D1 A8 20 A11
IRQB 135 MODB/IRQB* D1 100 D0 D[23:0] A18 18 A10 DGND
DSP_MODE 134 MODC/IRQC* D0 A7 17 A9
MODD/IRQD* A6 16 A8 30 D23
141 62 A5 15 A7 D7 29 D22
TCK 140 TCK TA* 63 R567 DGND A4 14 A6 D6 26 D21
TDI TDI BR* NC 10k A5 D5
142 71 A3 5 25 D20
TMS NOT_USED 139 TMS BG* 64 R568 DGND A2 4 A4 D4 12 D19
TDO TDO BB* 10k D+3V3 A3 D3
R566
10k A1 3 11 D18
R103 A0 2 A2 D2 8 D17
A17 1 A1 D1 7 D16
GNDQ3
GNDQ2
GNDQ1
GNDQ0

GNDA3
GNDA2
GNDA1
GNDA0

GNDD3
GNDD2
GNDD1
GNDD0

GNDC1
GNDC0

0R0
GNDS1
GNDS0
GNDH

A0 D0
GNDP

6
31 CE 10
47

127
90
54
19

96
87
81
75

130
120
112
104

66
58

39
26
9

13 OE GND1 28
WE GND2
512KX8
DGND
short stuff with 128kx8 SRAM
DGND
D[23:0]
Designer
TC Electronic A/S MAR
Title Module title
POCO FW DSP
Number Revision Previous page
P17100 GAE 1
Date Filename Page / of
8-28-2006_21:02 10 / 10
 Area reserved for document binding

Best printed and viewed on sheetsize A4

D+3V3

C552 C4 C554 C555 C5 C6 C558 C559 C560 C561 C562 C563 C564 C7 C566

100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n

DGND D+3V3
IC13
A16 35 27
A15 34 A18 VCC1 9
D+1V8 A14 33 A17 VCC2
D+3V3 A13 32 A16 C483 C484
A12 24 A15
C490 C569 C568 C570 C571 C572 A11 23 A14 100n 100n
A10 22 A13

126

129
119
111
103
45
18
91
56

95
49
20

86
80
74

57
65

38

25
10u 100n 100n 100n 100n 100n A9 A12

8
C489 21
A8 20 A11 DGND

VCCP
VCCQL3
VCCQL2
VCCQL1
VCCQL0
VCCQH2
VCCQH1
VCCQH0

VCCA2
VCCA1
VCCA0
VCCD3
VCCD2
VCCD1
VCCD0
VCCC1
VCCC0

VCCH

VCCS0
VCCS1
22n A18 18 A10
A7 17 A9
A8

TP93
DGND DGND A6 16 30 D7
46 A5 15 A7 D7 29 D6
TP47 PCAP 55 A4 14 A6 D6 26 D5
EXTAL CLK A3 5 A5 D5 25 D4
23 99 A17 A2 4 A4 D4 12 D3
HRRQ HTRQ 24 HACK/HRRQ/PB15 A17 98 A16 A1 3 A3 D3 11 D2
HTRQ HCS 30 HOREQ/HTREQ/PB14 A16 97 A15 A0 2 A2 D2 8 D1
HCS HWR* 21 HCS*/HA10/PB13 A15 94 A14 A17 1 A1 D1 7 D0
HWR* HRD* 22 HDS*/HWR*/PB12 A14 93 A13 A[18:0] A0 D0
HRD* HA[2:0] HA2 31 HRW*/HRD*/PB11 A13 92 A12
HA[2:0] HA1 32 HA2/HA9/PB10 A12 89 A11 6
HA0 33 HA1/HA8/PB9 A11 88 A10 31 CE 10
HD[7:0] HD7 34 HA0/HAS/PB8 A10 85 A9 13 OE GND1 28
HD[7:0] HD6 35 H7 A9 84 A8 WE GND2
HD5 36 H6 A8 83 A7 512KX8
HD4 37 H5 A7 82 A6 DGND
HD3 40 H4 A6 79 A5 D+3V3
HD2 41 H3 A5 78 A4 IC14
HD1 42 H2 A4 77 A3 A16 35 27
HD0 43 H1 A3 76 A2 A15 34 A18 VCC1 9
NC 3 H0 A2 73 A1 A14 33 A17 VCC2
HREQ* A1 72 A0 A0 A13 32 A16 C485 C486
143 A0 A0 A12 24 A15
MOSI R92 2 MOSI A11 23 A14 100n 100n
D+3V3 144 SS* 70 CS0 A10 22 A13
MISO/SDA 10k MISO AA0/RAS0* A12
1 69 A18 A9 21
SCK SCK AA1/RAS1* 51 R603 A8 20 A11
AA2/RAS2* RCS A18 18 A10 DGND
27R4 A9
15 52 NC A7 17
SCKR 13 SCKR IC16 CAS* 68 R614 A6 16 A8 30 D15
FSR 60 FSR RD* 67 R615 A5 15 A7 D7 29 D14
SCKR_1 SCKR_1 WR* 27R4 A6 D6
59 DSP56367 27R4 A4 14 26 D13
FSR_1 17 FSR_1 A3 5 A5 D5 25 D12
HCKR 14 HCKR 133 D23 A2 4 A4 D4 12 D11
SCKT 53 SCKT D23 132 D22 R604 A1 3 A3 D3 11 D10
SCKT_1 12 SCKT_1 D22 131 D21 R605 RD A0 2 A2 D2 8 D9
FST FST D21 27R4 WR A1 D1
50 128 D20 27R4 A17 1 7 D8
FST_1 16 FST_1 D20 125 D19 A0 D0
HCKT 11 HCKT D19 124 D18
SDO5/SDI0 10 SDO5/SDI0 D18 123 D17 6
SDO4/SDI1 48 SDO4/SDI1 D17 122 D16 31 CE 10
SDO5_1/SDI0_1 138 SDO5_1/SDI0_1 D16 121 D15 13 OE GND1 28
SDO4_1/SDI1_1 7 SDO4_1/SDI1_1 D15 118 D14 WE GND2
SDO3/SDI2 6 SDO3/SDI2/SDO3_1/SDI2_1 D14 117 D13 512KX8
SDO2_1/SDI3_1 5 SDO2/SDI3/SDO2_1/SDI3_1 D13 116 D12 DGND
SDO1 4 SDO1/SDO1_1 D12 115 D11 D+3V3
SDO0_1 R543 28 SDO0/SDO0_1 D11 114 D10 IC15
DSP0 DGND ACI D10
LD2 10k NC 27 113 D9 A16 35 27
680R 29 ADO D9 110 D8 A15 34 A18 VCC1 9
D+3V3 TIO0 D8 109 D7 A14 33 A17 VCC2
R551 R544 61 D7 A16
108 D6 A13 32 C487 C488
DGND PINIT/_NMI D6 107 D5 A12 24 A15
TP80 10k D5 A14
44 106 D4 A11 23 100n 100n
DSPRESET* RESET* D4 105 D3 A10 22 A13
137 D3 102 D2 A9 21 A12
IRQA 136 MODA/IRQA* D2 101 D1 A8 20 A11
IRQB 135 MODB/IRQB* D1 100 D0 D[23:0] A18 18 A10 DGND
DSP_MODE 134 MODC/IRQC* D0 A7 17 A9
MODD/IRQD* A6 16 A8 30 D23
141 62 A5 15 A7 D7 29 D22
TCK 140 TCK TA* 63 R539 DGND A4 14 A6 D6 26 D21
TDI TDI BR* NC 10k A5 D5
142 71 A3 5 25 D20
TMS NOT_USED 139 TMS BG* 64 R540 DGND A2 4 A4 D4 12 D19
TDO TDO BB* 10k D+3V3 A3 D3
R538
10k A1 3 11 D18
R91 A0 2 A2 D2 8 D17
A17 1 A1 D1 7 D16
GNDQ3
GNDQ2
GNDQ1
GNDQ0

GNDA3
GNDA2
GNDA1
GNDA0

GNDD3
GNDD2
GNDD1
GNDD0

GNDC1
GNDC0

0R0
GNDS1
GNDS0
GNDH

A0 D0
GNDP

6
31 CE 10
47

127
90
54
19

96
87
81
75

130
120
112
104

66
58

39
26
9

13 OE GND1 28
WE GND2
512KX8
DGND
short stuff with 128kx8 SRAM
DGND
D[23:0]
Designer
TC Electronic A/S MAR
Title Module title
POCO FW DSP
Number Revision Previous page
P17100 GAE 1
Date Filename Page / of
8-28-2006_21:02 10 / 10
 Area reserved for document binding

Best printed and viewed on sheetsize A4

D+3V3
D+3V3 TP58 D+3V3
L10
AVDD
C93 C89 C92 C86 C87 C88 BDS3/3/4.6-4S2
C44
C58 C57 C56 C47 C46
1n0 1n0 1n0 100n 100n 100n 10u
100n 100n 100n 100n 100n
D+3V3 TP57 D+3V3
L9

116
AD[31:0] DGND

16
30
46

70
72
81
85
90
93
98
AD[31:0]

3
C59 IC8 C83 BDS3/3/4.6-4S2
C41 D+3V3
DGND

VDDP1
VDDP2
VDDP3
VDDP4
VDDP5

AVDD1
AVDD2
AVDD3
AVDD4
AVDD5
AVDD6
AVDD7
100n 1n0 10u
D+3V3 110 103 L8
DGND R40RESET* 112 G_RST* PLLVDD PGND PGND TP59 BDS3/3/4.6-4S2
4 X2 R55 108 PCI_CLK 7
27R4 R33 DGND PCI_CLKRUN* DVDD1
VDD IC10 10k 53 19 C60 C63 C66 C69 C71 C74 C76 C80 C39
NC 1 INH* 1 3 PCLK PCI_RST DVDD2 27
OUT 3 2 IN Y1 5 27R4
118 DVDD3 40 100n 100n 100n 100n 100n 100n 100n 100n 10u
AD31
GND D+3V3 6 OE Y2 7 R34 DSPCLK3 R60 AD30 120 PCI_AD31 DVDD4 56
33.0000MHz2 D+3V3 4 VDD Y3 8 10k AD29 121 PCI_AD30 DVDD5 65 C61 C62 C68 C70 C72 C75 C78 C82 DGND
DGND GND Y4 R3627R4 DSPCLK2 AD28 122 PCI_AD29 DVDD6 111
DGND CY2304NZZC-1 DGND AD27 124 PCI_AD28 DVDD7 123 1n0 1n0 1n0 1n0 1n0 1n0 1n0 1n0
27R4 R37 PCI_AD27 DVDD8
DSPCLK1 AD26 125 107 D+1V8
AD25 127 PCI_AD26 REG_EN* 61 D+3V3
R3827R4 DSPCLK0DSPCLK[3:0] AD24 128 PCI_AD25 REG18_1 126
DSPCLK[3:0] 5 PCI_AD24 REG18_2 C109
27R4 AD23 NSQA6V8AW5T2G
AD22 6 PCI_AD23 101 C94 C96 TPA0+ 1 5 TPB0+
AD21 8 PCI_AD22 FILTER0 102 C32
AD20 9 PCI_AD21 FILTER1 100n 100n 100n
AD19 10 PCI_AD20 64 DGND TPA0- 3 4 TPB0-
AD18 11 PCI_AD19 PC0 63 DGND DGND DGND R63 R64 1u0
PCI_AD18 PC1 DGND 56R2 56R2

MX-53984-0611
AD17 13 62 D31 2
AD31 AD16 14 PCI_AD17 PC2 DGND 6

BDS3/3/4.6-4S2
AD15 29 PCI_AD16 100 5 10 CGND
AD14 31 PCI_AD15 R0 99 R61 TP65 4 9 97-787
PCI_AD14 R1 6k34 TP64 CONNECT
AD13 33 LD8 3 8 1 2
AD12 34 PCI_AD13 67 R51 R66 R65 2 7
PCI_AD12 CNA D+3V3 56R2 56R2 NC BR8
AD11 35 69 1
PCI_AD11 CPS R41 PY1112H-TR 680R J8
AD10 37 AVDD C122 C123 CGND CGND CGND
AD9 38 PCI_AD10 R62
PCI_AD9 390k 5k11 220p L7
AD8 39 79 TPBIAS0 10n
AD7 42 PCI_AD8 TSB43AB23 TPBIAS0 78 TPA0+
44 PCI_AD7 TPA0+ 77 DGND DGND DGND CGND
AD6 TPA0- NSQA6V8AW5T2G
AD5 45 PCI_AD6 TPA0- 75 TPB0+ TPA1+ 1 5 TPB1+
AD4 47 PCI_AD5 TPB0+ 74 TPB0- C35
AD3 48 PCI_AD4 TPB0-
AD2 49 PCI_AD3 DGND TPA1- 3 4 TPB1-
AD1 50 PCI_AD2 88 TPBIAS1 R70 R69 1u0
PCI_AD1 TPBIAS1 56R2 56R2

MX-53984-0611
AD0 52 87 TPA1+ D32 2
PCI_AD0 TPA1+ 86 TPA1- 6

BDS3/3/4.6-4S2
TPA1- 83 TPB1+ 5 10 CGND
4 TPB1+ 82 TPB1- 4 9 97-787
114 PCI_IDSEL TPB1- 3 8 1 2
GNT C/BE[3:0]C/BE[3] 2 PCI_GNT* R67 R68 2 7
C/BE[3:0] PCI_BE3* 56R2 56R2 NC BR10
C/BE[2] 15 96 TPBIAS2 1
18 PCI_BE2* TPBIAS2 95 TPA2+ C126 C124 J10 CGND CGND CGND
IRDY 21 PCI_IRDY* TPA2+ 94 TPA2- R71
DEVSEL 24 PCI_DEVSEL* TPA2- 92 TPB2+ 5k11 220p L6 10n
PERR 25 PCI_PERR* TPB2+ 91 TPB2-
SERR 28 PCI_SERR* TPB2- C97 DGND DGND DGND CGND
C/BE[1] NSQA6V8AW5T2G
C/BE[0] 41 PCI_BE1* 105 TPA2+ 1 5 TPB2+
26 PCI_BE0* XI C38
PAR 22 PCI_PAR 106 X1 15P
STOP 20 PCI_STOP* XO TP54 TP53 24.5760MHZ C108 DGND DGND TPA2- 3 4 TPB2-
TRDY 17 PCI_TRDY* 68 R84 R83 1u0
PCI_FRAME* PHY_TEST_MA D+3V3 56R2 56R2

MX-53984-0611
FRAME NC 117 55 R58 D33 2
115 PCI_PME* CYCLEIN 54 R59 D+3V3TP63TEST2TP56 15P 6

BDS3/3/4.6-4S2
PCI_REQ* CYCLEOUT 10k DGND LD9
REQ 109 58 R56 5 10 CGND
10k TEST3TP55

PLLGND
PCI_INTA
DGND10

INTA_FPGA GPIO2 57 D+3V3 4 9

DGND1
DGND2
DGND3
DGND4
DGND5
DGND6
DGND7
DGND8
DGND9

AGND1
AGND2
AGND3
AGND4
AGND5
AGND6
AGND7
LD10 PY1112H-TR 680R 97-787
R94 GPIO3 59 R57 3 8 1 2
D+3V3 SCL 60 D+3V3 R81 R82 2 7
1k0 SDA BR1112H-TR 680R 56R2 56R2 NC BR11
D+3V3 1
104 TP60 J11
113
119

C139 C129 CGND CGND CGND

12
23
32
36
43
51
66

71
73
76
80
84
89
97 R87
1

IC9
R29 R19 8 1 C142 5k11 220p L5 10n
PGND 2K7 2K7 7 VCC A1 2
NOT_USED NOT_USED
DGND 6 WP A2 3 100n DGND DGND DGND CGND
DGND DGND 5 SCL A3 4
SDA GND
256X8
R53 R52 DGND
220R 220R NOT_USED

DGND DGND TP61TP62

Designer
TC Electronic A/S MAR
Title Module title
POCO FW FIREWIRE
Number Revision Previous page
P17100 GAE 1
Date Filename Page / of
8-28-2006_21:02 3 / 10
 Area reserved for document binding

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D[63:0]
D[63:0]
SDMA[11:0]
SDMA[11:0]
SDBA[1:0]
SDBA[1:0]
DQM[7:0]
DQM[7:0] IC28 IC27 IC30 IC29
SDMA0 23 2 D48 SDMA0 23 2 D32 SDMA0 23 2 D16 SDMA0 23 2 D0
SDMA1 24 A0 D0 4 D49 SDMA1 24 A0 D0 4 D33 SDMA1 24 A0 D0 4 D17 SDMA1 24 A0 D0 4 D1
SDMA2 25 A1 D1 5 D50 SDMA2 25 A1 D1 5 D34 SDMA2 25 A1 D1 5 D18 SDMA2 25 A1 D1 5 D2
SDMA3 26 A2 D2 7 D51 SDMA3 26 A2 D2 7 D35 SDMA3 26 A2 D2 7 D19 SDMA3 26 A2 D2 7 D3
SDMA4 29 A3 D3 8 D52 SDMA4 29 A3 D3 8 D36 SDMA4 29 A3 D3 8 D20 SDMA4 29 A3 D3 8 D4
SDMA5 30 A4 D4 10 D53 SDMA5 30 A4 D4 10 D37 SDMA5 30 A4 D4 10 D21 SDMA5 30 A4 D4 10 D5
SDMA6 31 A5 D5 11 D54 SDMA6 31 A5 D5 11 D38 SDMA6 31 A5 D5 11 D22 SDMA6 31 A5 D5 11 D6
SDMA7 32 A6 D6 13 D55 SDMA7 32 A6 D6 13 D39 SDMA7 32 A6 D6 13 D23 SDMA7 32 A6 D6 13 D7
SDMA8 33 A7 D7 42 D56 SDMA8 33 A7 D7 42 D40 SDMA8 33 A7 D7 42 D24 SDMA8 33 A7 D7 42 D8
SDMA9 34 A8 D8 44 D57 SDMA9 34 A8 D8 44 D41 SDMA9 34 A8 D8 44 D25 SDMA9 34 A8 D8 44 D9
SDMA10 22 A9 D9 45 D58 SDMA10 22 A9 D9 45 D42 SDMA10 22 A9 D9 45 D26 SDMA10 22 A9 D9 45 D10
SDMA11 A10/AP D10 47 D59 SDMA11 A10/AP D10 47 D43 SDMA11 A10/AP D10 47 D27 SDMA11 A10/AP D10 47 D11
35 A11 D11 35 A11 D11 35 A11 D11 35 A11 D11
SDBA1 21 48 D60 SDBA1 21 48 D44 SDBA1 21 48 D28 SDBA1 21 48 D12
SDBA0 A12/BS1 D12 50 D61 SDBA0 A12/BS1 D12 50 D45 SDBA0 A12/BS1 D12 50 D29 SDBA0 A12/BS1 D12 50 D13
20 A13/BS0 D13 20 A13/BS0 D13 20 A13/BS0 D13 20 A13/BS0 D13
51 D62 51 D46 51 D30 51 D14
D14 53 D63 D14 53 D47 D14 53 D31 D14 53 D15
D15 D15 D15 D15
49 49 49 49
VCCQ4 43 VCCQ4 43 VCCQ4 43 VCCQ4 43
VCCQ3 9 VCCQ3 9 VCCQ3 9 VCCQ3 9
VCCQ2 3 D+3V3 VCCQ2 3 D+3V3 VCCQ2 3 D+3V3 VCCQ2 3 D+3V3
DQM7 39 VCCQ1 DQM5 39 VCCQ1 DQM3 39 VCCQ1 DQM1 39 VCCQ1
DQMU VCC3 27 DQMU VCC3 27 DQMU VCC3 27 DQMU VCC3 27
DQM6 15 14 DQM4 15 14 DQM2 15 14 DQM0 15 14
DQML VCC2 1 DQML VCC2 1 DQML VCC2 1 C323 DQML VCC2 1
WE* 16 VCC1 100n C326 C616 WE* 16 VCC1 100n C322 C615 WE* 16 VCC1 100n C325 C617 WE* 16 VCC1 100n C320 C618
WE* WE* WE* WE*
SDRAS*18 52 C324 100n 100n SDRAS* 18 52 C321 100n 100n SDRAS* 18 52 C323 100n 100n SDRAS* 18 52 C319 100n 100n
SDCAS*17 RAS* GNDQ4 46 SDCAS* 17 RAS* GNDQ4 46 SDCAS* 17 RAS* GNDQ4 46 SDCAS* 17 RAS* GNDQ4 46
SDCS0* 19 CAS* GNDQ3 12 SDCS0* 19 CAS* GNDQ3 12 SDCS0* 19 CAS* GNDQ3 12 SDCS0* 19 CAS* GNDQ3 12
CS* GNDQ2 6 CS* GNDQ2 6 CS* GNDQ2 6 CS* GNDQ2 6
GNDQ1 DGND GNDQ1 DGND GNDQ1 DGND GNDQ1 DGND
GND3 54 GND3 54 GND3 54 GND3 54
SDCLK038 41 SDCLK0 38 41 SDCLK1 38 41 SDCLK1 38 41
SDCKE 37 CLK GND2 28 SDCKE 37 CLK GND2 28 SDCKE 37 CLK GND2 28 SDCKE 37 CLK GND2 28
CKE GND1 CKE GND1 CKE GND1 CKE GND1
4Mx16 4Mx16 4Mx16 4Mx16

WE*
SDRAS*
SDCAS*
SDCS0*
SDCLK0
SDCLK1
SDCKE

D+3V3
IC4
DP[7:0] DP0 37 31
DP[7:0] DP1 13 A19 VCC1 30
DP2 40 A18 VCC0
DP3 1 A17 38 SDBA1 TP1
DP4 2 A16 NC2 29
DP5 3 A15 NC1 11 DGND
DP6 4 A14 NC0
DP7 5 A13 TP
SDBA0 6 A12 R516
SDMA1036 A11 1k0
SDMA9 7 A10
SDMA8 8 A9 DGND
SDMA7 14 A8 35 D0
SDMA6 15 A7 D7 34 D1
SDMA5 16 A6 D6 33 D2
SDMA4 17 A5 D5 32 D3
SDMA3 18 A4 D4 28 D4
SDMA2 19 A3 D3 27 D5
SDMA1 20 A2 D2 26 D6
SDMA0 21 A1 D1 25 D7
A0 D0
RCS0* 22 12 RYBY
RCS0* FOE* 24 CE* RY/BY*
FOE* WE* 9 OE* 39
10 WE* GND1 23
RESET* RESET*GND0
1Mx8 DGND
RYBY Designer
D+3V3 D+3V3 TC Electronic A/S MAR
100n 100n Title Module title
POCO FW PPC_MEM
C327 C328 Number Revision Previous page
DGND DGND P17100 GAE 1
Date Filename Page / of
8-28-2006_21:02 5 / 10
 Area reserved for document binding

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D[63:0]
0DSPD[23:0] D[63:0]
1DSPD[23:0] 0DSPD[23:0]
2DSPD[23:0] 1DSPD[23:0]
3DSPD[23:0] 2DSPD[23:0]
SDMA[8:4] 3DSPD[23:0]
0DSPIRQB SDMA[8:4]
IRQB TP46

2DSPRD*
0DSPIRQA IC25

SDCLK2

1DSPA0
IRQA TP48 SDMA7 2 4

RCS1*
A Y0 0DSPHCS*

WE*
0DSPRD* SDMA8 3 5
RD TP49 B D+3V3;16Y1 6 1DSPHCS*
0DSPWR* DSPHCS* 1 DGND;8 Y2 7 2DSPHCS*
WR TP50 G Y3 3DSPHCS*
74LVC139APWR

2DSPD3
2DSPD0
2DSPD15
2DSPD6
2DSPD5
2DSPD16
2DSPD18
2DSPD14
2DSPD1
2DSPD9
2DSPD8
2DSPD4
2DSPD7
2DSPD10
1DSPD23
2DSPD20
2DSPD19
2DSPD11
2DSPD23
1DSPD15

1DSPD9
1DSPD0
1DSPD11
1DSPD13

2DSPD2
1DSPD8
1DSPD1
1DSPD12
1DSPD19
1DSPD17
1DSPD16
1DSPD6
1DSPD2
2DSPD12
1DSPD7
1DSPD5
1DSPD4
1DSPD14
1DSPD22
0DSPRCS*
CS TP51 IC25
14 12
TP68 13 A Y0 11 NC
B D+3V3;16Y1 10 NC
R96 15 DGND;8 Y2 9 NC
IC26 NC
D+3V3 G Y3

A10
A11
A12
A13
A14

B10
B11
B12
B13

C10
C11
C12

D10
D11
D12
E10
E11
1k0

A3
A4
A5
A6
A7
B3
B4
B5
B6
B7
C4
C5
C6
C7
D5
D6
D7
D8
E6
E7

B8
C8

A8
A9

B9

C9

D9
74LVC139APWR

IO0-0
IO0-1
IO0-2
IO0-3
IO0-4
IO0-5
IO0-6
IO0-7
IO0-8
IO0-9
IO0-10
IO0-11
IO0-12
IO0-13
IO0-14
IO0-15
IO0-16
IO0-17
IO0-18
IO0-19

GCK2
GCK3

IO1-0
IO1-1
IO1-2
IO1-3
IO1-4
IO1-5/WRITE*
IO1-6/CS*
IO1-7
IO1-8
IO1-9
IO1-10
IO1-11
IO1-12
IO1-13
IO1-14
IO1-15
IO1-16
IO1-17
IO1-18
IO1-19
IO1-20
IO1-21
D+3V3 IC31
R536 T2 C13 2 18 D24
NOT_USED DGND R537 M0 TDI TDI TP434 3 A1 Y1 17 D25
10k R93 1k0 R1 M1 TMS
B1
TMS 1k0 A2 Y2
1k0 R3 A2 4 16 D26
R43 D+3V3 A15 M2 TCK B14 TCK R88 5 A3 Y3 15 D27
AS* 1k0 CCLK TDO TDO A4 Y4
R16 D+3V3 6 14 D28
FPGA_PROGRAM* T15 PROGRAM* B16 D0 DGND 7 A5 Y5 13 D29
FPGA_DONE DONE IO2-0/D0 2DSPD22 8 A6 Y6 12 D30
C15
3DSPD15 H4 IO2-1//BUSY C16 D33 10k 9 A7 Y7 11 D31
3DSPD14 H3 IO7-22 IO2-2 D14 1DSPD20 R11 A8 Y8
3DSPD11 H2 IO7-21 IO2-3 D15 1DSPD21 ZEROFILL 1 20
3DSPD13 H1 IO7-20 IO2-4 D16 D53 19 OE1* VCC 10 D+3V3
3DSPD10 G5 IO7-19 IO2-5 E13 1DSPD10 TP362 OE2* GND DGND
3DSPD16 G4 IO7-18 IO2-6 E14 1DSPD18 74LVC541APWR
3DSPD12 G3 IO7-17 IO2-7 E15 D1 1k0 IC32
G2 IO7-16 IO2-8/D1 E16 D23 R86 2 18 D56
2DSPRCS* G1 IO7-15 IO2-9 1DSPD3 3 A1 Y1 17 D57
2DSPWR* F12
F5 IO7-14 IO2-10 F13 D40 DGND 4 A2 Y2 16 D58
1DSPRD* 3DSPD17 F4 IO7-13 IO2-11 D2 5 A3 Y3 15 D59
F14
F3 IO7-12 IO2-12/D2 F15 D21 6 A4 Y4 14 D60
DSPRESET* F2 IO7-11 IO2-13 D52 7 A5 Y5 13 D61
1DSPRCS* F16
F1 IO7-10 IO2-14 G12 D11 8 A6 Y6 12 D62
1DSPWR* E4 IO7-9 IO2-15 D41 9 A7 Y7 11 D63
2DSPA0 G13
E3 IO7-8 IO2-16 G14 D10 A8 Y8
1DSPIRQA E2 IO7-7 IO2-17 D3 1 20
2DSPIRQB G15
E1 IO7-6 IO2-18/D3 G16 D51 19 OE1* VCC 10 D+3V3 D+3V3 D+3V3
2DSPIRQA 2DSPD13 D3 IO7-5 IO2-19 D55 OE2* GND DGND
H13
2DSPD17 D2 IO7-4 IO2-20 H14 D16 74LVC541APWR
D1 IO7-3 IO2-21 H15 D50 10k 10k
1DSPIRQB 2DSPD21 C2 IO7-2 IO2-22 D20 IC11 R97 R98
H16
C1 IO7-1 FOE* IO2-23 2 18
DSP_MODE IO7-0 3 A1 Y1 17 DSPHRD*
J13 D54 WE*
3DSPD6 P2 IO3-0 J14 D4 SDMA6 4 A2 Y2 16 DSPHA2DSPHA[2:0] DSPHWR*
3DSPD3 P1 IO6-22 IO3-1/D4 J15 D17 SDMA5 5 A3 Y3 15 DSPHA1 DSPHA[2:0]
0DSPD6 N3 IO6-21 IO3-2 J16 D18 SDMA4 6 A4 Y4 14 DSPHA0
3DSPD7 N2 IO6-20 IO3-3 K12 D46 7 A5 Y5 13 NC
N1 IO6-19 IO3-4 K13 TP67 8 A6 Y6 12 NC
3DSPWR* 0DSPD21 M4 IO6-18 IO3-5 K14 D43 0DSPIRQA R95 9 A7 Y7 11 NC
0DSPD20 M3 IO6-17 IO3-6 K15 D49 DGND A8 Y8
IO6-16 IO3-7 K16 SDMA7 1k0
3DSPD4 M2 DSPHDEN 1 20
3DSPD5 M1 IO6-15 IO3-8 L12 D12 19 OE1* VCC 10 D+3V3
0DSPD4 L5 IO6-14 IO3-9 L13 D5 OE2* GND DGND
0DSPD5 L4 IO6-13 IO3-10/D5 L14 D22 74LVC541APWR
L3 IO6-12 IO3-11 L15 D34
3DSPRD* 3DSPD18 L2 IO6-11 IO3-12 L16 D6 IC12
3DSPD19 L1 IO6-10 IO3-13/D6 M13 D19 HD[7:0] HD7 14 15 D0
3DSPD0 K5 IO6-9 IO3-14 M14 D44 HD[7:0] HD6 17 A1 B1 16 D1
3DSPD1 K4 IO6-8 IO3-15 M15 D37 D+3V3 HD5 18 A2 B2 19 D2
3DSPD2 K3 IO6-7 IO3-16 M16 HD4 21 A3 B3 20 D3
3DSPD23 K2 IO6-6 IO3-17
D+3V3;E8,F7,F8,E9,F9,F10,G11,H11,H12,J11,J12,K11,L9,L10,M9,L7,L8,M8,J5,J6,K6,G6,H5,H6
N14 D39 ATMELCLK HD3 22 A4 B4 23 D4
3DSPD22 K1 IO6-5 D+1V8;C3,C14,D4,D13,E5,E12,M5,M12,N4,N13,P3,P14 IO3-18 N15 10k A5 B5
3DSPD8 J4 IO6-4 IO3-19 N16 SDMA8
DGND;A1,A16,B2,B15,F6,F11,G7,G8,G9,G10,H7,H8,H9,H10,J7,J8,J9,J10,K7,K8,K9,K10,L6,L11,R2,R15,T1,T16SDMA10 R12
3DSPD9 J3 IO6-3 IO3-20 P15 DSPHDEN DSPHDEN 13
3DSPD21 J2 IO6-2 IO3-21/INIT* P16 D7 OE*
D+3V3;24
IO5-20
IO5-19
IO5-18
IO5-17
IO5-16
IO5-15
IO5-14
IO5-13
IO5-12
IO5-11
IO5-10

IO4-21
IO4-20
IO4-19
IO4-18
IO4-17
IO4-16
IO4-15
IO4-14
IO4-13
IO4-12
IO4-11
IO4-10

IO6-1 IO3-22/D7
GCK0
GCK1

3DSPD20 J1
IO5-9
IO5-8
IO5-7
IO5-6
IO5-5
IO5-4
IO5-3
IO5-2
IO5-1
IO5-0

IO4-9
IO4-8
IO4-7
IO4-6
IO4-5
IO4-4
IO4-3
IO4-2
IO4-1
IO4-0

DGND;12
IO6-0 74CBTLV3384PWR
M6
M7
N5
N6
N7
N8
P4
P5
P6
P7
P8
R4
R5
R6
R7
R8
T3
T4
T5
T6
T7

T9
T8

M10
M11
N10
N11
N12
N9
P10
P11
P12
P13
P9
R10
R11
R12
R13
R14
R9
T10
T11
T12
T13
T14

IC12
HD2 3 2 D5
A1 B1
0DSPD11
0DSPD14
0DSPD2
0DSPD1

0DSPD0
0DSPD3
0DSPD18
0DSPD10
0DSPD16
0DSPD7
0DSPD12
0DSPD13
0DSPD23
0DSPD15

0DSPD19

0DSPD22
0DSPD17
0DSPD9

D36
D8

D47
DSPHCS*
0DSPD8

D14
D45

D42

D13
D32
D15
ZEROFILL

D35
D9
D38
D48

HD1 4 5 D6
HD0 7 A2 B2 6 D7 DSP host port
8 A3 B3 9
TP66 680R 11 A4 B4 10 PY1112H-TR
DGND A5 B5 D+3V3
TP527 R369
LD17
NC 1 HOST
OE* TP436 NOT_USED
3DSPA0

0DSPRCS*
3DSPRCS*

FOE*

0DSPRD*

D+3V3;24
3DSPIRQB

0DSPWR*

0DSPA0

3DSPIRQA

TEST_RESET

0DSPIRQB

DGND;12
74CBTLV3384PWR

D+1V8 D+3V3
Designer
TC Electronic A/S MAR
Title Module title
100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n
POCO FW FPGA_S2E
C107 C105 C15 C103 C131 C130 C128 C53 C52 C23 C136 C135 C133 C132 C145 C310 C315 C311 Number Revision Previous page
P17100 GAE 1
Date Filename Page / of
DGND DGND 8-28-2006_21:02 6 / 10
 Area reserved for document binding

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Unconnected nets
MPC8245 Reset configuration
SDCS1* NC Pull-up Netname Pull-downFunction
SDCS2* NC Internal Pull-up
AS* 1: Peripheral logic Clock Output
SDCS3* NC
SDCS4* NC D32 R4
SDCS5* NC DGND11: 8 bit databus For ROM/FLASH chip select #0 (RCS0)
1k0
SDCS6* NC NOT_USED
SDCS7* NC Internal Pull-up
FOE*
GNT1 NC
GNT2 NC Internal Pull-up
MAA0 1: The MPC8245 is configured for address map B
GNT3 NC
GNT4 NC SRESET* 4 IC3 TP2 RESET
LD7
REQ1 NC D+3V3;14 6 R2 TP9 PPC_PWR MAA1 1k0
REQ2 NC 5 DGND;7 BR1112H-TR D+3V3 Internal Pull-up DGND 1: MPC8245 is a PCI master (host) device
1k0 R3 NOT_USED
REQ3 NC
REQ4 NC 74LV08 10R
IC3 R380
SDCLK3 NC 1 C422 C431 MAA2 1k0
DA2 NC DHRST D+3V3;14 3 TP10 DGND 0: PCI arbiter enabled
R5
DA15 NC 2 DGND;7 IC2 2u2 2u2
DA14 NC RESET* TP476 MCP
DA13 NC 74LV08 CKO_DA14 DGND DGND D+3V3 D+3V3
LED pull-up PCI output hold delay value

DA12 NC HRST_CPU AVDD SDCKE

MCP TP467 HRST_CTRL* AVDD2 10R Internal Pull-up
DA11 NC LD5 C432 C433R381
R18 R79 R80

Control
MCP
D+3V3 2k2 MCP* 2u2 2u2 2k2 2k2 PMAA0 1k0
BR1112H-TR 1k0 DGND 2k2 NMI SDA DGND Driver capability for the memory signals

I2C
D+3V3 R77 SMI* SDA SDA R26 01: 40 Ohm drive capability
SCL DGND DGND
SRESET* 2k2 R76 SRESET* SCL F2 QACK SCL PMAA1 1k0
D+3V3 TBEN QACK/DA0 Internal Pull-up DGND
R75 2k2 R72 NOT_USED
D+3V3 CHKSTOP_IN* DA2
R74 DA2 PMAA2 1k0
Driver capability for the PCI and EPIC controller output signals.
DA[15:11]
DA[15:11] D[31:0] D[63:0] DGND 0: 40 Ohm drive capability on PCI/EPIC signals
TCK TCK DH[31:0] D[63:0] R73
D[63:32]
TDI TDI DL[31:0] DQM[7:0]
TDO TDO CAS/DQM[7:0] SDCS[7:0]* SDCS0* DQM[7:0] QACK 1k0
1 No clock flip
TMS TMS RAS/CS[7:0] DP[7:0] SDCS0* Internal Pull-up DGND
TRST* TRST* PAR/AR[7:0] DP[7:0] R78 NOT_USED

Debug
SDMA[11:0]
NC MAA0 SDMA[11:0] SDBA[1:0] SDMA[11:0]

Memory
MAA1 MAA0 SDBA[1:0] SDBA[1:0] RCS0* 1k0
1: Boot ROM is located on local processor/memory data bus.

MAA2 MAA1 D1,G1,G2,E1

SDCLK[3:0]
Internal Pull-up DGND
MAA2 SDRAM_CLK[3:0] SDCLK2 R14 NOT_USED
NC
PMAA0 MIV PLL_CFG[4:0] SDCLK1
PMAA1 PMAA0 PLL_CFG[4:0] SDCLK0 GNT4
1: Debug address disabled

PMAA2 PMAA1 Internal Pull-up

PMAA2
110R SDRAM_SYNC_OUT
D+3V3 10k TEST0 SDRAM_SYNC_IN SDMA01k0
0: DUART unit signals enabled
D+3V3 10k R304 DRDY* Internal Pull-up DGND
D+3V3 R510 RTC AS* AS* R512
R511 MPC8245L FOE* FOE*
NC
AD[31:0] AD[31:16] INTA* WE* WE* SDMA11k0
1: Extended addressing mode disabled.
AD[31:0] AD[15:0] AD[31:16] CKE SDCKE DGND SRESET, TBEN, CHKSTOP_IN, TRIG_IN, and TRIG_OUT available.
AD[15:0] SDRAS* SDRAS* R513 NOT_USED
GNT[4:0]
D+3V3 GNT0 REQ[4:0] GNT[4:0] SDCAS* SDCAS*
REQ0 REQ[4:0] RCS0* RCS0*
DGND NC OSC_IN RSC1* RCS1* 2k2
R502 R503 R504 R505 R506 R507 R508 R509 NC PCICLK4 RSC2* NC R514
D+3V3 PLL configuration
Config
10k 10k 10k 10k 10k 10k 10k 10k PCI_SYNC_OUT RSC3*
PCLK PCI_SYNC_IN 1k0 PLL_CFG0 1k0
PCI
Jumper setting: [4:0] = "11101"
DEVSEL DEVSEL* SIN1 RS232_RX D+3V3 DGND PCI clk: 33 MHz (input)
IDSEL SOUT1 RS232_TX R6 R515 NOT_USED
NC CPU clk: 266 MHz (output)
FRAME FRAME* SIN2/CTS1* NC 1k0 PLL_CFG1 1k0 Mem clk: 133 MHz (output)
IRDY IRDY* SOUT2/RTS1* D+3V3 DGND
TRDY TRDY* R8NOT_USED R364
STOP STOP* IRQ4 IRQ[4:0] 1k0 PLL_CFG2 1k0
LOCK* IRQ4/L_INT IRQ[4:0] D+3V3 DGND
EPIC

IRQ3 R9 R365 NOT_USED

PAR PAR IRQ3/S_FRAME IRQ2
SERR SERR* IRQ2/SRST IRQ1 1k0 PLL_CFG3 1k0
PERR C/BE[3:0] PERR* IRQ1/SCLK IRQ0 D+3V3 DGND
C/BE[3:0] C/BE[3:0] IRQ0/SINT R10 R366 NOT_USED
SIGNAL=PPC_PWR;AA24,AC16,AC19,AD12,AD6,AD9,C15,C18,C21,D11,D8,F3,H23,J3,L23,M3,R24,T4,V24,W4
SIGNAL=D+3V3;U3 1k0 PLL_CFG4 1k0
TP6 SIGNAL=D+3V3;AB24,AD20,AD24,C14,C20,C24,E24,G24,J23,K24,M24,P24,T23,Y24 D+3V3 DGND
R42 R13 R367 NOT_USED
SIGNAL=D+3V3;AB3,AB4,AC10,AC11,AC8,AD10,AD13,AD15,AD3,AD5,AD7,C10,C12,C3,C5,C7,D13,D5,D9,E3,G3,H4,K4,L4,N3,P4,R3,U3,V4,Y3
10k SIGNAL=DGND;W3,V23,V2,T3,T24,R4,R23,P3,N24,M4,M23,L3,L24,J4,J25,H24,F4,F25,D3,D24,D21,D18,D15,D12,C8,C4
SIGNAL=DGND;C23,C16,C13,C11,B9,B6,B25,B2,AE25,AE21,AE2,AE18,AD4,AD23,AD19,AD16,AD14,AD11,AC9,AC6,AC3,AC24,AC15,AC12,AA23,AA2
DGND TP5 D+3V3;Y23,P23,G23,D23,D20,AC23,AC20
Testpoints
TP15TP35TP37TP38

FOE*

WE*

RCS0*

RCS1*
D+3V3

100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n C469 C470
C34 C33 C110 C111 C112 C29 C28 C27 C26 C113 C24 C22 C21 C120 C19 C18 C16 C209 C121 C213 C127 C115 C117 C118 C220 C119 C222 C223 C224 C228 C229 C230 C231 C114 C204 C210 C211 C217 C225 C226 220u 220u

DGND
PPC_PWR Designer
TC Electronic A/S MAR
Title Module title
100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n C471
POCO FW PPC
C51 C50 C49 C48 C45 C43 C42 C40 C37 C36 C205 C206 C207 C208 C104 C106 C116 220u Number Revision Previous page
P17100 GAE 1
DGND
Date Filename Page / of
8-28-2006_21:02 4 / 10
 Area reserved for document binding

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J7
D+3V3 Power for PPC and DSP's
JTAG interface

TP12

TP13
PPC_PWR D+1V8 DGND 2 1 TDI
DGND 4 3 TDO TDI
R594 R22

JTAG for DSP and

D5 DGND 6 5 TCK
R596 220R TCK

Interconnect test
0R0 C3 C2 NC 8 7 NC D2
TEST_RESET 100n IC6 TPS72518DCQ 10 9 9 IC3
LL4148 680R

TP14
2 NOT_USED 4 220u 220u NC 12 11 D+3V3;14 8
D30 D1LL4148
IC40 3 C550 C1 1 VI VO 5 NC 14 13 NC D+3V3 RESET_1V8* RESET* 10 DGND;7 DSPRESET*
VCC EN RESET* DGND DGND
LL4148 LL4148D6 74LV08

TP72
2 DGND 10u GND1 GND2 E52800601 RESET1*
RESET*

J1
RESET* 3 6 RESET_1V8*
TP71 LL4148 10k

2
GND DGND
1 MAX809TEUR-T D+5V DGND DGND R21
NOT_USED

TP446
D+3V3
DGND DGND 6V2 100n 100n 100n C102 TMS
R44 D23 IC7 TMS
TP11 C73 C54 C64 1000u 2
1k0 A1
3
1u0 B1

13 VCCQP
DGND DGND DGND DGND 5 4

6 VCCA

7 VCCP
TP444 TP442 TP440 6 A2 Y1 7 TMS_PPC
TP445 TP443 TP441 TP439 B2 Y2

TP448

TP449
C100 11 9 TCK_PPC
2 TP528 FDD6680 TDO_PPC 10 A3 Y3 12
NC ENABLE PPC_PWR TDO_DSP 14 B3 Y4 TDI_PPC
NC 3 12 Q3 TP450 TP41 TDO_FPGA 13 A4
PWRGD HIDRV B4 D+3V3
20 9 L1 0R01 1 16
16 VREF LODRV 4U7 R181 15 A*/B VCC 8 C551
1 CNTRL Q4 G GND
1k0 CEXT 4 D+3V3 74LVC157APWR 100n
R28 8 IFB FDD6680 D+3V3 DGND
17 VID4 5 R592 1 2
J2 DGND
TP530 R110 18 VID3 VFB DGND 1k0 10k 10k 10k D+3V3
LD3 1k0

GNDP1

GNDP2
0R0 19 VID2 10k 10k 1k0 R593R582R581R584 NOT_USED
GNDA

GNDD
J9
PY1112H-TR R111 VID1 R583R589R595 10k

JTAG for PPC

2 1 TDO_PPC Connect Jumper for debug
100n 0R0 4 3 TDI_DBG R590
R174
15

14

10

11
6 5
C55 0R0 100n D26 C101 8 7 TCK_DBG DGND
C77 R112 MBRS140T3 NC 10 9 TMS_DBG
0R0 C65 1000u NC 12 11 SRESET*
NOT_USED

100p NC 14 13 DHRST SRESET*

16 15 RESET* 12 IC3 DHRST
RC5066M DGND D+3V3;14 11 TRST_PPC
NOT_USED 13 DGND;7 TRST_PPC
set to 1.85V supply
DGND 74LV08

D+3V3 D+3V3
FDS4435A

TP28 TP30 D+5VTP34 TP78 D+3V3 FPGA

J3
L4
Q2
L14
I2C interface LD15 LD16
BR1112H-TR PY1112H-TR
Q1

1
TP430 TP429 TP428
S

D
2 BDS3/3/4.6-4S2 Q5 4u7 D+3V3
1k0 R370 R371 TP21
G

1 220p
100n R621 NOT_USED
R54 C141 FDC658P D4 R35 220p C25 100n 1 4 680R 680R
MMBZ15
R620 BC857 10k IC5 7 MBRS140T3 6k34 2 A0 P0 5 FPGA_PROGRAM*
D3 NOT_USED 5
2 C13 FDS4435A 10k Q6 R32 PGATE 1 C140 100u C137 3 A1 P1 6
D34 10k 8 ADJ IS 4 DGND TP76 A2 P2 7 NC FPGA_DONE
6V2 VIN FB R89 DGND DGND 1k0 P3 9 RESET1*
DGND
CGND DGND DGND TP630 C30 GND1 GND2 9k09 R85 13 P4 10 NC TP73 TP74TP75
TP629 DGND 2 6 LM3485 NC INT P5 11
220u TP79 DGND P6 12 NC RYBY
Front panel connection TP32 DGND DGND R90
9k09TP77
TP16 TP17 P7
TP20
J12 DGND 14 16
1 1k0 SCL 15 SCL VCC 8 D+3V3
D+5V R30 BR1 BR2 SDA SDA GND DGND
2 DGND
3 D+3V3 SCL PCF8574T
4 SDA D+3V3 TP18 TP3
H8 TP100 TP101 TP102 TP103
1
2
3
4

1
2
3
4

5 8 1
DGND NOT_USED NOT_USED 100n 7 VCC RST* 2 ATMEL_RESET*
6
7 DGND 6 PB2 XTAL1 3 NC D+3V3 D+3V3 ATMELCLK
8 D+3V3 D+5V 100n 100n DGND DGND DGND DGND C138 5 PB1 XTAL2 4 10k
9 DGND PB0 GND R39
10 D+5V 220p 220p 220p 220p 220p C31 C14 ATTINY45 R598 R599
D+3V3 DGND DGND DGND 2k2 2k2
C125 C134 C143 C144 C146 DGND DGND
8 PINHEADER IN 10 PIN FOOTPRINT MOSI
DGND DGND DGND DGND DGND MISO/SDA
SCK

D+3V3
D+3V3 D+3V3 D+3V3 D+3V3 D+3V3 D+3V3 D+3V3
TP451 Power-up protection
RS232 C81 C90 C91 C95 C79 C84 100n C85
R1
1k0
H10 H5 H4 H7 H2 H3 H6
D+5V 10u 10u 10u 10u 10u 10u C67 10u D+3V3 PPC_PWR
TP22
D29 D28
C518 DGND DGND DGND DGND DGND DGND DGND 100n 100n
LD1 NOT_USED NOT_USED
TP27 TP29 TP31 TP33 TP36 TP39 TP40 PY1112H-TR PRLL4001 PRLL4001
100n C12 C17 D27
DGND DGND DGND DGND
CGND
CGND
CGND
CGND
CGND PRLL4001
J13 DGND DGND DGND DGND DGND DGND DGND
1 R622
NOT_USED

2 RS232_TX
680R
3 DGND DGND DGND DGND DGND DGND BDS3/3/4.6-4S2
R623 L3
4 D+3V3
RS232_RX C149 C150 C151 C152 C153 TP8 TP19 TP7 Designer
680R
DGND 220p 220p 220p 220p
R101
220p 33R
TC Electronic A/S MAR
R624 1k0 TP628 Title Module title
TP24

TP25

CGND CGND CGND CGND CGND CGND DGND PGND DGND

DGND
DGND POCO FW INTERFACE
DGND Number Revision Previous page
P17100 GAE 1
Date Filename Page / of
8-28-2006_21:02 2 / 10