Power Factor

Correction (PFC)
(功率因數矯正器)

Ch4-81

Foreword
 Power supplies often have an ac line source input
 The front stage is diode-bridge ac-dc rectifier
 The diodes conduct for only a small duration in each
cycle, this causes the line current (is) highly non-
sinusoidal and has large THD  low PF

Ch4-82

1
Power Factor Correction (PFC)
 A way to improve the PF (and reduce the THD) is
with a PFC circuit (boost-based converter)
 The line voltage after rectifying is sampled as the
reference value of iL. Through switching control, the
iL follows the 120Hz sinewave to correct the distorted
line current waveform
iL

is

kvs
Ch4-83

CCM PFC
 This current is mainly at the same frequency and
phase angle as the voltage
 Making the PF quite high and the THD quite low
 This type of switching scheme is called CCM PFC

Ch4-84

2
 DCM PFC
 The iL varies between zero and a peak that
follows a sinusoidal shape
 This type of switching scheme is called DCM PFC
 DCM is used with low-power circuits, while CCM
is more suitable for high-power applications

Ch4-85

PFC
 In both the CCM and DCM PFC, their output is a
high dc voltage (usually on the order of 400 V)
 The PFC output will connect a dc-dc converter (e.g.,
a forward converter can be used to step down 400-V
to 5 V)
 Other converter topologies in addition to the boost
converter can be used for PFC (e.g., SEPIC and C’uk
converters are well suited for this purpose)

Ch4-86

3
 Power Supply Control

Ch4-87

Control Mechanism
 In SMPS, Vo = f(Vi , D, ILoad)
 Vo is regulated by modulating D to compensate
variations in Vi & load
 Feedback control system compares Vo with a
Vo,ref and converts error into a duty ratio

Ch4-88

4
 Feedback Control System

Voltage-mode/direct duty cycle control

Ch4-89

Linearized Feedback System

Can be linearized
H(s)

H(s)
Ch4-90

5
 Buck with Feedback

Include:
Power stage + output filter
CEA: compensated error amplifier
PWM modulator + gate driver Ch4-91

Buck with Feedback

H(s)

Ch4-92

6
 Buck with Feedback

Ch4-93

Closed-loop Block Diagram

H(s)
Ch4-94

7
 Stability Criterion
 Nyquist stability criterion-Special case: phase
margin test
 Power circuit modeling: State-space averaging
(SSA, 狀態空間平均) technique [Middlebrook,
C’uk etc.]
 Average model of PWM [V. Vorp’erian]

Ch4-95

Control Loop Stability

Performance and stability of control loop for regulating
Vo of a converter can be determined from the open-loop
TF characteristics:
 Low-frequency gain should be large  steady-state
error small
 Converter switching-frequency gain should be small
or filtered out
 Open-loop phase shift at cross-over freq. must lag by
less than 180o
 At least 45o phase margin (PM) is a commonly used
criterion for stability
Ch4-96

8
Phase & Gain Margin Definition

cross-over freq.

At cross-over freq., phase shift of less than 180o

Ch4-97

Small Signal Equivalent Circuit Derivation

 Control loop analysis based on the dynamic

behavior of voltages, currents, and switching
 Dynamic behavior can be described in terms of
small signal variations around a steady-state
operating point
 State-space averaging (SSA) is used to derive
the small-signal equivalent circuit model of
power circuit + output filter

Ch4-98

9
 Switch Network TF
 For control purposes, the average values of v and i are of
greater interest than the instantaneous values that occur during
the switching period
 The relationship between I/P and O/P for the switch network
for a time-varying duty ratio (d) is represented by an ideal
transformation of 1 : d
 d consisting of a dc (constant) component D plus a small-signal
component d

Q L

D C R

switch network in a buck Ideal Tr mode for switch network

Ch4-99

Switch Network Small-Signal Model

small ac perturbations
vx  Vx  v x , d  D  d , iL  I L  iL , vs  Vs  v s , is  I s  is

  
vx  vsd  Vx  v x   Vs  v s  D  d  DVs  Dv s  Vsd  v sd
   
dc term 2 nd ac term
1 st ac terms

dc term : Vx  DVs
Linearization: neglecting
first  orde ac term : v x  Dv s  Vsd the 2nd ac terms
Ch4-100

10
 Switch Network Small-Signal Model

similarly
is  Vx  v x , d  D  d , iL  I L  iL , vs  Vs  v s , is  Is  is

   
is  iLd  I s  is  I L  iL D  d  DI L  DiL  ILd  iLd 
dc term : I s  DIL Linearization: neglecting
first  orde ac term : is  DiL  I Ld the 2nd ac terms
Ch4-101

Filter TF
 The input to the buck converter filter is the Q L

switch network output, which is vx = dvs D C R

Filter TF with the load resistor and no capacitor ESR

vo ( s) vo ( s) 1
 
vx ( s) Vsd(s) LC  s  s(1 / RC)  1 / LC
2

vo ( s) Vs

d(s) LC  s  s(1 / RC)  1 / LC 
2

Filter TF with the load resistor and capacitor ESR

vo ( s) Vs 1  srC R

d(s) LC s (1  (rC / R))  s((1 / RC)  (rC / L))  1 / LC
2

vo ( s) Vs 1  srC R
R  rC  
d(s) LC s  s((1 / RC)  (rC / L))  1 / LC
2

capacitor ESR produces a zero in TF, which may be important in determining system stability
Ch4-102

11
PWM Modulator TF Q L

D C R

 Pulse-width modulator (PWM)

converts the vo from the
compensated error amplifier (CEA)
to a duty ratio
 Error amplifier output voltage vc is
compared to a sawtooth waveform
with amplitude Vp
1, if vc  vp
d (t )  
 0, if vc  v p
v
d c
Vp
d ( s) 1
The TF of PWM: 
v c ( s) V p Ch4-103

State-Space Averaging (SSA)

Step 1) each circuit state described by state variable
CCM converter has two operating states
 iL 
 State variable : iL , vC
x 
vC 
 State equation (including parasitic elements)
x = Ax + Bv
vo = CT x
switch on (dT ) switch off ((1  d )T )
x = A1x + B1 v x = A2 x + B2 v
vo = C1T x vo = CT2 x
Ch4-104

12
State-Space Averaging (SSA)

Step 2) average state equation using duty ratio d

x  [ A1d  A2 (1  d)]x  [B1d  B2 (1  d)]v (1)
v0  [C1d  C2 (1  d )]x (2)
 A  A1d  A2 (1  d )

where  B  B1d  B2 (1  d )
C  C d  C (1  d )
 1 2

Ch4-105

State-Space Averaging (SSA)

Step 3) Introducing small ac perturbations, and separation ac & dc terms
x  X  xˆ , d  D  dˆ , v  V  vˆ , d  1  d  D  dˆ , xˆ , dˆ , vˆ  X, D, V

x  X   xˆ = 0  xˆ  xˆ

0 + xˆ  [ A1 ( D  dˆ )  A2 ( D ' dˆ )]( X  xˆ )  [B1 ( D  dˆ )  B2 ( D ' dˆ )](V  vˆ )

 ( A D  A D ') X  ( A  A ) Xdˆ  ( A D  A D ') xˆ  ( A  A )xd
1 2 1 2 1 2 1 2
ˆˆ
( B1 D  B2 D ')V  (B1  B2 )Vdˆ  ( B1 D  B2 D ')vˆ  (B1  B2 )vd
ˆˆ
if v = V  vˆ  V (vˆ  0), and neglect all xd
s s s
ˆ ˆ terms, then small ac perturbations
vo  Vo  vˆ o , d  D  dˆ
First  order ac terms
iL  I L  iˆL , vs  Vs  vˆ s
xˆ  ( A1 D  A2 D ') xˆ  [( A1  A2 )X  (B1  B2 )Vs ]dˆ vC  VC  vˆ C
大寫: 直流(穩態)項
DC terms
ˆ :交流(小信號擾動)項
0  AX  BVs  X   A-1BVs 小寫: 表穩態  小信號
Ch4-106

13
State-Space Averaging (SSA)
Step 3) Introducing small ac perturbations, and separation ac & dc terms
x  X  xˆ , d  D  dˆ , v  V  vˆ , d  1  d  D  dˆ , xˆ , dˆ , vˆ  X, D, V
Similarly
vo  Vo  vˆ o   C1d  C2d ' x  C1 (D  dˆ )  C2 (D' dˆ )  X  xˆ 
 
  C D  C D' X   C  C  Xd   C D  C D' xˆ   C  C  xd
1 2 1 2
ˆ
1 2 1 2
ˆˆ
First  order ac terms :
vˆ o   C1D  C2 D' xˆ   C1  C2  Xdˆ
DC term : Vo   C1D  C2 D' X, X  A-1BVs
Vo
 Vo   C1D  C2 D'   A-1BVs     C1D  C2 D'   A-1B  CA-1B
Vs
Ch4-107

State-Space Averaging (SSA)

Step 4) transfer ac term to s-domain to obtain transfer function
xˆ  Axˆ  [( A  A )X  (B  B )V ]dˆ
1 2 1 2 s

sxˆ ( s)  xˆ (0)  Axˆ ( s)  [( A1  A2 )X  ( B1  B2 )Vs ]dˆ ( s)

 xˆ ( s)  ( sI  A)1[( A1  A2 )X  ( B1  B2 )Vs ]dˆ ( s)
Similary
vˆ o  Cxˆ   C1  C2  Xdˆ , C  C1 D  C2 D '
vˆ o ( s)  Cxˆ ( s)   C1  C2  Xdˆ ( s)
TF of power stage and output filter (control to o/p TF Gvd )
vˆ ( s)
TP ( s)  o  C( sI  A)1 ( A1  A2 )X  ( B1  B2 )Vs   C1  C2  X 
ˆd( s)
Ch4-108

14
 Example: CCM Forward TF

vˆ o ( s)
N1 : N 2  1 :1, find TP ( s) 
dˆ ( s)
Ch4-109

Example: Forward TF
Switch on state equation:
T T
state variable: x = iL vC    x1 x2 
 VS  Lx 1  rL x1  R( x1  Cx 2 )  0

  x2  rcCx 2  R( x1  Cx 2 )  0
x  A1 x  B1V
 RrC  RrL  rC rL R 

L( R  rC )   x1   
 1
 x 1   L( R  rC )

         L  VS
x
 2 R  1  x2  0
   

C ( R  r )

C C ( R  rC ) B1
A1
Ch4-110

15
 Example: Forward TF
Switch off state equation:

0  Lx 1  rL x1  R( x1  Cx 2 )  0

 x2  rcCx 2  R( x1  Cx 2 )  0
x  A2 x  B2V
 RrC  RrL  rC rL R 
 
 x 1   L( R  rC ) L( R  rC )   x1  0
          VS
 x2  R 1   x2  
0
 
C( R  rC )
 C( R  rC )  B2

A2

A2  A1 , B2  0 Ch4-111

Example: Forward TF
Output voltage:

v0  C T x
RrC R
v0  R( x1  Cx 2 )  x1  x2
R  rC R  rC
 RrC R   x1 
   
R  rC
 R  rC   x2 
 
C

 RrC R 
C1T  C2T   
 R  rC R  rC 
Ch4-112

16
Example: CCM Forward TF
In practical circuit : R  (rC  rL )
 (rC  rL ) 1 
 L L
A  A1  A2    C1T  C2T  rC 1 , B不變
 1 1 
 C CR 
1
B  B1D  B2 (1  D)   L  D
 
 0
A  A1 D  A2 (1  D)  A1 (1  D  D)  A1
CT  C1T D  C2T (1  D)  C1T
Ch4-113

Example: CCM Forward TF

V0
dc voltage TF in SS:  C T A1 B
VS
 1 1 
LC  CR L  D
  [rC 1]12    L
  1  (rC  rL ) / R  1 ( rC  rL )   
0  21
CT
 C L  22 
 B
A 1

R  rC
D D
R  (rC  rL )
Voltage Conversion ratio of forward in CCM
V0 N 2 N 
M( D )   D  D  2  1
VS N1  N1 
Ch4-114

17
Example: CCM Forward TF
ac small signal TF:
vˆ ( s)
TP ( s)  o  C( sI  A)1 ( A1  A2 )X  (B1  B2 )Vs   C1  C2  X 
ˆd( s)
1
  ( rC  rL ) 1  
 s 0     VS 
L L L
 [rC 1]12   
 0 s   1 1    
    0  21
 C CR   22
V 1  srcC
 S

LC s  s[ 1
2
 (r  r ) L ]  1
CR C L LC 
Ch4-115

Example: CCM Forward TF

ac small signal TF:
vˆ ( s) VS 1  srcC
TP ( s)  o 

dˆ ( s) LC s2  s[ 1
CR
 (rC  rL ) L ]  1
LC 
Denominator of TP ( s) has the form : s  20 s  
2 2
0

1 1 / CR  ( rC  rL ) / L
0  ,  A zero due to ESR of filter C :
LC 20
1 02 rC
1 z  and 
rc C( s  ) rcC z L
v 0 ( s) rcC
TP ( s)   VS
d (S)   1 ( rC  rL )  1 
LC  s2  s    
  CR L  LC 
02  s  z  rc s  z
 VS  2 2 

z  s  20 s  0  L s  20 s  02
2

Ch4-116

18
 Example: CCM Forward TF
ac small signal TF:
vˆ ( s) VS 1  srcC
TP ( s)  o 

dˆ ( s) LC s2  s[ 1
CR
 (rC  rL ) L ]  1 
LC
Denominator of TP ( s) has the form : s2  20 s  02
1 1 / CR  ( rC  rL ) / L
0  ,  A zero due to ESR of filter C :
LC 20
1 02 rC
1 z  and 
rc C( s  ) rcC z L
v 0 ( s) rcC
TP ( s)   VS
d (S)   1 ( rC  rL )  1 
LC  s2  s    
  CR L  LC 
02  s  z  rc s  z
 VS  2 2 

z  s  20 s  0  L s  20 s  02
2

Ch4-117

Compensated Error Amplifier (CEA)

Desired characteristics of open-loop power stage TF
1. Low-freq. gain should be high to minimize o/p SS error
2. Crossover freq. should be high but an order of magnitude below
switching freq. to allow quick response for transients

Type 1 CEA
3. Phase margin (PM): PM = OL + 1800
OL = phase angle of TOL at crossover freq. (negative)
Desired phase margin range  450 Ch4-118

19
 CEA
 EA compares converter vo with a reference voltage
(vo,ref) to produce an error signal (ve) that is used to
adjust switch duty ratio
 Compensation associated with the amplifier
determines control loop performance and provides
for a stable control system
 CEA TF should give a total loop characteristic
consistent with the stability criteria
 Namely, CEA should have a high gain at low freq., a
low gain at high freq., and an appropriate phase
shift at crossover freq. Ch4-119

Control Black Diagram

H(s)

v o ( s)
TOL ( s)  T1 ( s)Tc ( s), T1 ( s) 
v c ( s)
Tc ( s)  TF of CEA, H ( s)  sampling gain
Ch4-120

20
 Type 2 CEA
v c ( s) Z f A( s  z )
TC (s) 
A(s  z )
TC ( s)    s(s  p )
v o ( s) Zi s( s   p )
1 1 A  0, z  p
( R2  )
 1  1 v ( s) SC1 SC2
Zi  R1 , Z f   R2   //  c 
 sC1  sC v ( s ) 1 1
2 o R1 ( R2   )
SC1 SC2
If C2  C，
1 then
1 1
S S
v c ( s) R2C1 R2C1
 
v o ( s) C1  C2 1
R1C2 S(S  ) R1C2 S(S  )
R2C1C2 R2C2
C1  C2 1
Poles： 0 ，  p  
R2C1C2 R2C2
1
Zero： z 
R2C1
Ch4-121

Type 2 CEA
Middle- Frequency response Bode plot
frequency
gain
R2
Gc 
R1 
f
Due to zero
A( s  z )
TC ( s) 
s( s   p )
Pole at origin

 Values of R1, R2, C1 and C2 are chosen to make the overall control system have
the desired attributes
 Filter capacitor ESR puts a zero at 1/rCC

 A simulation program (e.g. Pspice) is useful to determine the freq. response.

Otherwise, the TF may be evaluated with s = j Ch4-122

21
 Type 2 CEA Control loop TF Gain
Frequency Response

R2 1
Gc  Gc ( jc ) 
R1 Tu ( j c )
z p

cross
1
20 log
Vp

20 log Gvd

 Middle-freq. gain and pole & zero location of CEA must

be designed to compensate for the gain decay of power
stage and PWM and provide the proper phase margin
required for stability Ch4-123

Type 2 CEA Design Procedure

1. Choose desired crossover freq. (fc) of total open-
loop TF, usually around an order of magnitude less
than converter switching freq.
2. Except for CEA, determine all units TF & freq.
response that in control circuit
3. Determine mid-frequency gain of CEA required to
achieve overall desired crossover freq., this obtain
R2/R1 ratio (equal the gain decay of uncompensated
loop gain @ fc)
4. Choose desired phase margin needed to assure
stability, typically > 450. From middle-freq. gain
obtain R1, R2; C1, C2 are determined by pole & zero
Ch4-124

22
 Type 2 CEA Design
1
S
v c ( j )
A( s  z ) R2C1
j  z TC ( s)  
s  j   s(s  p ) C  C2
R1C2S(S  1 )
v o ( j ) R1C2 j ( j   p ) R2C1C2

１
For middle Freq. (  z ,    p ) p 
R2C2
v c ( j ) j 1 R2
Gain :   
v o ( j ) R1C2 jp 1 R1
R1C2 ( )
R2C2
   
Phase : CEA  1800  tan1    900  tan1  
 z   p 
 
   
=  2700  tan 1    tan1  
 z   p 
 
Ch4-125

K-Factor Method
   
Phase : CEA  1800  tan 1    900  tan 1  
 z   p 
 
Phase angle of CEA at crossover freq. is
 cross  
1  cross

CEA cross  2700  tan 1    tan  
 z  
 p 
cross p
Let K 
z  cross
1
 CEA cross  2700  tan 1 K  tan 1 ( )
K

Pole & zero freq. selection—K-factor method (D. Venable, “The K factor: A New Mathematical
Tool for Stability Analysis and Synthesis,” Proceedings Powercon, 1983) Ch4-126

23
 K-Factor Method
Using trigonometric identity
1 1
tan1 ( x)  tan1    90o  tan1    90o  tan1 ( K )
x
  K
1
 CEA cross  2700  tan1 K  tan1    2tan1 ( K )  360o  2tan1 ( K ) (1)
K
 
 K  tan  CEA cross  (2)
 2 
from (1), for 0  K    0o  CEA cross  180o @ fc
CEAcross   PM   converter (3) PM  CEA cross  converter 

The K value can be calculated from (2) if the CEA-cross is

determined from (3). Where PM is the desired phase margin
Ch4-127

K-Factor Method
 Accordingto desired phase margin (PM ) and control
loop phase shift (converter ), the needed CEA-cross can
be obtained from (3), then K is determined by (2)
 If cross & K are known, then z & p can be obtained,
C1, C2 are then found
 p 
K  cross   z  cross ,  p  Kcross
z cross K
1  K S
1

z   cross  C1  T ( s) 
A( s   )

RC
z
C C
2 1

cross R2
C
s( s   )
R2C1 K R C S(S 
p
1
RCC
)2
1

2 1
2

1 1
p   Kcross  C2 
R2C2 cross R2 K
Ch4-128

24
 Design Example: Type 2 CEA
Buck converter: Vs = 10V, Vo = 5V, fs = 100 kHz, L = 100 H
with SR = 0.1, C = 100F with ESR = 0.5  , R = 5  , Vp =
3V in PWM circuit. Design a type 2 CEA that results in a
stable control system (PM  45o)
Solution

1. Let fco= 10 kHz < fs

2. Pspice simulation shows that (@ fco 10 kHz): power

stage & filter gain: –2.24 dB, phase angle: -101o ,
PWM gain=1/Vp=1/3=-9.54 dB. The combined
gain= –2.24 dB+(-9.54 dB)= -11.78 dB (= G1)
Ch4-129

Design Example: Type 2 CEA

3. CEA should have a Mid-freq. gain +11.78
dB (@ 10 kHz) to make loop gain 0 dB, then

v c v c
 11.78 
 
11.78 dB  20log   10 20   3.88
v o v o
R2
  3.88  Let R1  1 k, then R2  3.88 k
R1

Ch4-130

25
 Design Example: Type 2 CEA
4. PM = 45o, converter= -101o , then
CEA-cross= PM - converter = 450 - (-1010) = 1460
1  K
z   cross  C1 
R2C1 K crossR2
1 1
p   Kcross  C2 
 CEAcross   1460  RC crossR2K
K  tan   
2 2

 tan   3.27
 2   2 
K 3.27
 C1    13.4nF
2 fco R2 2 (10k)(3.88k)
1 1
 C2    1.25nF
2 fco R2 K 2 (10k)(3.88k)3.27
Ch4-131

Implemented Type 2 CEA circuit

Verify: A Pspice simulation of the implemented

control loop gives a crossover frequency of 9.41 kHz
and a phase margin of 46o
Ch4-132

26
Pspice Simulation
Type 2
compensator

Vs=6V, Vo=3.3V, fs=100 kHz, L=100

H rL =0.1, C=100F rC= 0.5  ,
R = 2  or 2//2 , Vp = 1.5V

Ch4-133

Type 3 CEA Design

 Type 2 CEA (0 < PM < 180o) is sometimes
not capable of providing sufficient phase
margin (PM) greater than 45o for stability
criterion
 Type 3 CEA (-90o < PM < 270o) provides an
additional phase angle boost compared to
type 2 CEA
 It is used when an adequate PM is not
achievable by using type 2 CEA
Ch4-134

27
 TF of Type 3 CEA

 1   1   1  1 
 R2   //   s  s  
v ( s) Zf sC 1   sC2  R  R3  R C
2 1  ( R  R )C
GCEA ( s)  c     1 1 3 3 
(1)
v o ( s) V Z  1  R1 R3C2  C  C2   1 
ref  0
i
R1 //  R3   s s  1  s  
 sC 3   R2C1C2   R3C3 

2 zeros and 3 poles Ch4-135

 Vref is dc and has no effect on small-signal TF.

Assuming C1 >> C2 & R1 >> R3, then
 1  1   1  1 
s  s   s  s  
R  R3  R2C1   ( R1  R3 )C3  1  R2C1   R1C3 
GCEA ( s)   1  (2)
R1R3C2  C1  C2   1  R3C2  1  1 
s s   s   s s   s  
 R C C
2 1 2  R C
3 3  R2C2   R3C3 

 There are 2 zeros and 3 poles

+20dB/dec.
-20dB/dec. -20dB/dec.

p1( 0)  z1  z2  p2  p3 Ch4-136

28
  1  1   1  1 
s  s   s  s  
R1  R3  R2C1   (R1  R3 )C3  1  R2C1   R1C3 
GCEA (s)    (2)
R1R3C2  C1  C2   1  R3C2  1  1 
s s   s   s s   s  
 R C C
2 1 2  R C
3 3  R2C2   R3C3 

Ch4-137

2 zeros 3 poles  1  1 
s  s  
1  R2C1  R1C3 
For C1  C2 & R1  R3  GCEA ( s)  
R3C2  1  1 
s s   s  
 R2C2  R3C3 

GCEA ( s  j)  
1  j  z1  j  z2  (3)
 
R3C2 jp1 j  p 2 j  p3 
 1  1 
1 1 1 s  s  
z1  , z 2   G CEA ( s)  
R1  R3  R2C1  ( R1  R3 )C3 
R2C1 ( R1  R3 )C3 R1C3 R1 R3C2 
s s 
C1  C2  
 s 
1 

 R2C1C2  R3C3 
C  C2 1 1
p1  0, p 2  1  , p 3 
R2C1C2 R2C2 R3C3
from (3), phase angle of CEA
   1   
     
CEA  180o  tan1    tan 
1
  90  tan 
o 1
  tan  
 z1   z 2   p 2   p 3 
   1   
     
 270o  tan1    tan 
1
  tan 
1
  tan   (4)
 z1   z2   p 2   p 3  Ch4-138

29
 Type 3 CEA Design
 The k-factor method can be used for type 3
in a similar way as it was used in type 2
 The zeros are placed at the same frequency
to form a double zero
 The 2nd & 3rd poles are placed at the same
frequency to form a double pole
 i.e. z = z1 = z2 , p = p2 = p3 , p1 = 0

Ch4-139

Type 3 CEA Design

 The double zeros & poles are placed at frequencies
co GCEA ( s  j)  
1  j  z1  j  z2  (3)
z  , p  co K (5)  
R3C2 jp1 j  p2 j  p 3 
K Yype 2

 j  z 
2 1 
1 z   cross
From (3), GCEA ( j)   R2C1 K

 
2
R3C2 j j   p 
1
R2C2
 Kcross
p

 jco  z 
2
1
At crossover freq. GCEA ( jco )  
 
2
R3C2 j j  
co co p

CEA phase at crossover freq.

   
CEAco  270o  2tan1  co   2tan1  co  (6)
 z   p 
  Ch4-140

30
 Type 3 CEA Design
co
    z  , p  co K (5)
CEA co  270  2tan  co   2tan1  co 
0 1 K
 z   p 
 
 co   co 
From (5), CEA-co  270o  2tan1  1
  2tan  
 co / K   co K 
 1 
 270o  2 tan1 K  tan1
 K 
1 1
tan1 x  tan1  90o  tan1  90o  tan1 K
x K
1
 CEA-co  90  4tan K ( for 0  K    CEA-co  90o ~ 270o )
o

2
   90o  
 K  tan  CEA-co  (7)
  4 
Ch4-141

Type 3 CEA Design z 

co
K
, p  co K (5)

 Maximum angle that can be compensated for the

type3 CEA is 2700, but for the type2 is 1800
1 1 1
z1  ,  
R2C1 z2 ( R1  R3 )C3 R1C3
CEA-co  PM  converter (8) C  C2 1 1
p1  0, p 2  1  , 
R2C1C2 R2C2 p3 R3C3
@ Crossover freq. (middle freq.: co  z , co  p )
 jco  z  1  jco  1  jco 
2 2
1
GCEA ( jco )     (9)
     
2 2
R3C2 j j   R3C2 j  R3C2  2
co co p co p p

K 1 1 1
From (5), co  Kz  , p    2p 
RC
1 3 R2C2 R3C3 R2C2 R3C3
K
j
1  jco  1 RC R
 GCEA ( jco )    1 3
 ( j K ) 2 (10)
  1
2
R3C2  R3C2 R1
p
R2C2 R3C3 Ch4-142

31
 Type 3 CEA Design
2
   90o  
K  tan  CEA-co  (7)
  4 

1  jco  j KR2 R2 GCEA ( jco )

GCEA ( jco )      (11)
 
2
R3C2  R1 R1 K
p

 First choose R1 and then compute R2 from (11)

 Other component values can be found by
co 1 1 1 1
z    , p  co K  
K R2C1 R1C3 R2C2 R3C3
GCEA ( jco ) R1 K K 1
R2  , C1   , C2  
K co R2 2fco R2 co R2 K
1 K K 1 1
, C3   , R3  
2fco R2 K co R1 2fco R1 coC3 K 2fcoC3 K
Ch4-143

Design Example: type 3 CEA

A Buck converter: Vs=10V, Vo=5V, fs=100 kHz, L=100
H with SR=0.1, C=100F with ESR = 0.1  , R = 5
 , Vp = 3V in PWM circuit. Design a type 3 CEA that
results in a stable control system (PM  45o)

Solution
1. Select fco = 10 kHz < fs
2. Pspice simulation shows that (@fc 10 kHz): power
stage & filter gain: –10.5 dB, phase angle: -144o ,
PWM gain=1/Vp =1/3 = -9.5 dB. Combined gain = –
10.5dB + (-9.5 dB) = -20 dB (= G1)
Ch4-144

32
 Design Example: type 3 CEA

3. PM = 45o, converter = -144o , then

CEA-cross= PM - converter =45o + 144o = 189o

2
  CEAcross  90o  
 
2
K  tan   
   tan 69.75   7.35
o

  4 

Ch4-145

Design Example: type 3 CEA

4. CEA should have a Mid-freq. gain +20 dB
(@ 10 kHz) to make loop gain 0 dB, then
20
( )
20 dB  20 log GCEA ( jco )  GCEA ( jco )  10 20
 10
1  jco  j K R2 R G ( jco )
GCEA ( jco )     2  CEA
 
2
R3C2  R1 R1 K
p

R2 GCEA ( jco ) 10
    3.6885
R1 K 7.35
R2
  3.7  Let R1  1 k,  R2  3.7 k
R1
Ch4-146

33
 Design Example: type 3 CEA
5. Calculating the other component values

K K 7.35
C1     11.6 nF
co R2 2fco R2 2(10k )(3.7k )
1 1 1
C2     1.58 nF
co R2 K 2fco R2 K 2(10k )(3.7k) 7.35
K K 7.35
C3     43.1 nF
co R1 2fco R1 2(10k )(1k )
1 1 1
R3     136 
coC3 K 2fcoC3 K 2(10k )(43.1n) 7.35
Ch4-147

Design Example: type 3 CEA

6. Implemented type 3 CEA
C2 = 1.58nF

R3 = 136 C3 = 43.1nF R2 = 3.7k

C1 = 11.6nF

R1 = 1k

Ch4-148

34
 Design Example: type 3 CEA
A Pspice simulation of the implemented
control loop gives a crossover frequency of 10
kHz with a phase margin of 49o
 Note that attempting to use type 2 CEA for this
converter is unsuccessful because the required
phase angle (189o) is greater than 180o
 Comparing this converter with previous type 2
example, the ESR of the capacitor is smaller.
Low capacitor ERS often necessitate use of type
3 rather than type 2 CEA
Ch4-149

Manual Placement of Poles &

Zeros in Type 3 CEA
 Inaddition to the K-factor method, the poles
& zeros assignment at specified frequencies
can be used to design the type 3 CEA
A frequency of particular interest is the
resonant frequency of the LC filter in the
converter (neglect any resistance in the L & C)
1 1
LC  fLC 
LC 2 LC
Ch4-150

35
 Zero or Pole Expression Placement
First zero z1 = 1/R2C1 50% to 100% of LC
Second zero z2 = 1/(R1+R3)C3 1/R1C3 At LC
First pole p1 = 0 --
Second pole p2 = (C1+C2)/R2C1C2 At the ESR zero = 1/rCC
1/R2C2
Third pole p3 = 1/R3C3 At one-half the switching
frequency, 2(fsw/2)

 The 1st zero is commonly placed at (50~100%) of fLC

 The 2nd zero placed at fLC
 The 2nd pole placed at ESR zero of the filter C, 1/rCC
 The 3rd pole placed at (1/2) fsw

Ch4-151

For more about other compensators (type I,

II, III, …), please refer to

 Abraham I. Pressman, Keith Billings,

Taylor Morey , “Switching Power Supply
Design/ Ch12,” Third Edition, 2009.

Ch4-152

36
Feed-Forward PWM Control
 Input voltage change, Vo regulated via
feedback control, but has a slow dynamic
performance when regulating Vo in response
to Vs change
 If D adjusted to accommodate the Vs change,
then Vo would remain unchanged
 Feeding Vs level to PWM IC

Ch4-153

Feed-Forward PWM Control

 Switching Strategy: Vs , Vˆr  D Vo
unchanged

Ch4-154

37
 Voltage-Mode Control
 Direct duty cycle control

Ch4-155

Voltage-Mode Control

Ch4-156

38
 Current-Mode Control

Inner loop

Outer loop

 vc directly control iL and thus Vo

 Ideally, vc should act to directly control average
of iL for fastest response
Ch4-157

Current-Mode Control
Sensing iL

Sensing ids

ids

Ch4-158

39
 Current-Mode Control

+
+
- Vs
-
Ti

Tv

Q
Ch4-159

Type of Current-Mode Control

 Peak current control

 Average current control
 Hysteresis control
 Critical conduction mode
 Valley current-mode control
 Emulated current-mode control

Ch4-160

40
Type of Current-Mode Control
 Tolerance band control: only suit for CCM,
vc indicate IL , band: (IL+ IL/2), (IL- IL/2)

Ch4-161

Type of Current-Mode Control

 Constant-off-time control: vc indicate IˆL ,
once iL reach IˆL , switch turn off a fixed off
time, switching freq. not fixed

Ch4-162

41
Type of Current-Mode Control
 Constant-freq. Control with a turn-on at
clock time: vc indicateIˆL , constant switching
freq.

Ch4-163

I-Mode Control Advantages Over V-

Mode Control
 Limit peak switch current
 Remove one pole (corresponding to output
filter inductor)
 Allow power supplies modular design
 Symmetrical flux excursion in push-pull
converter
 Provide input voltage feed-forward
Ch4-164

42
 Digital PWM Control
Digital approach has main advantages over
analog counterparts
 Lower sensitivity to environmental change
 Lower parts count
 Improving reliability

Ch4-165

Feedback Loop Isolation

Secondary-side Control

Ch4-166

43
 Feedback Loop Isolation

Primary-side Control

 Simplify the interface with the gate driver

 Input voltage feed-forward control is possible
Ch4-167

Designing to Meet
Specification
Requirements

Ch4-168

44
PWM Control IC
 Example: National
Semiconductor
LM2743, an analog
PWM IC for dc
power supply control
 The IC contains
error amplifier op-
amp, PWM circuit,
and driver circuits
for MOSFETs in a
dc-dc converter with
SR
Ch4-169

AC Line (Input) Filter

 The v and i from ac line system are often polluted by high-

frequency electrical noise (electromagnetic interference,
EMI)
 An ac line filter suppresses conductive EMI from entering
or leaving the power supply
 Single-stage low-pass L-C filter
 Improve PF and reduce conduction EMI
 This filter should have as little power loss as possible Ch4-170

45
 AC Line (Input) Filter

 A resistance across input filter capacitor, if no

adequate damping, an oscillation will exist
 A useful design criterion requires that (o)input filter
(resonant freq.) < 10 (o)output filter to avoid
interaction
Ch4-171

AC Line (Input) Filter

 Common-mode noise consists of currents in the line

and neutral conductors that are in phase and return
back to the ground (line to ground)
 Differential-mode noise consists of high-frequency
currents that are 180o out of phase in line and neutral
conductors, which means that current enters from the
line and returns in the neutral (line to line) Ch4-172

46
 AC Line (Input) Filter

 Common-mode EMI filter: consisting of a Tr with

adjacent polarity markings and a capacitor connected
from each line to ground
 Capacitors in this stage are referred to as Y capacitors

Ch4-173

AC Line (Input) Filter

 Differential-mode EMI filter: consisting of a Tr with

opposite polarity markings and a single capacitor
connected across the ac lines, removes differential-
mode noise from the ac signal
 The capacitor in this stage is referred to as the X
capacitor
Ch4-174

47
 Input Rectifier

1 2W
W  CV 2  C  2
2 V
Po( rated )  tholdup
Cd  2  2 , Vd ,min  (60% ~ 75%)Vd ,nominal
(Vd ,nomianl  Vd2,min )  
ac line variation: 230 2 V  30%
Ch4-175

Inrush Current Limit

Selenium (硒) diode Z1:

突波電壓保護

NTC 電阻: R2, R3

Ch4-176

48
 ESR of Output Filter C

vo,ESR  iC  rC  iL  rC

Ch4-177

Synchronous Rectifier (SR)

Ch4-178

49
 MO Cross Regulation

Output filter inductors are coupled (wound on a common

core), which can improve dynamic cross-regulation
Ch4-179

EMI Considerations

 EN 50006: European Standard

 IEC Norm 555-3: International Electrical
Commission
 VDE: German Standard
 ANSI/IEEE Std. 519-1992: IEEE Guide for
Harmonic Control and Reactive Compensation
of Static Power Converters
Ch4-180

50
 Ac Line Current Harmonic Standards

 US MIL-STD-461B: US military 3% limit

 International Electrotechnical Commission
(IEC) Standard 1000
 IEEE/ANSI Standard 519 (1993)

Ch4-181

Low Power Harmonic Limits

 In a city environment (e.g. a large building), a large
fraction of the total power system load can be nonlinear
 Example: a major portion of electrical load in a building
is comprised of fluorescent lights, which present a very
nonlinear characteristic to the utility system
 A modern office may contain many PCs, printers,
copiers, etc., each of which may employ peak detection
rectifiers
 Although each individual load is a negligible fraction of
the total local load, these loads can collectively become
significant
Ch4-182

51
International Electrotechnical Commission (IEC)
Standard 1000 (For low power 61000-x-x)

 A first draft of the IEC 555 standard in 1982

 IEC 1000-3-2 (Aug., 2009) standard covers a number
of different types of low power equipment, with
differing harmonic limits (Iin < 16A)
 European norm EN 61000-3-2 (2006) defines similar
limits
 It limits harmonics for equipment having an input
current of up to 16 A, connected to 50 or 60 Hz, 220 V
to 240 V single-phase circuits (two or three wire), as
well as 380 V to 415 V three-phase (three or four
wire) circuits
Ch4-183

IEC 61000-3-2 (2009 年 8 月更正)

 International IEC 61000-3-2 (Electromagnetic
compatibility, EMC) - Part 3-2: Limits for harmonic
current emissions (Iin < 16A per phase) Edition 3.0
and A1 of the Edition 3.0
 IEC 61000-3-4 - Limitation of emission of harmonic
currents in low-voltage power supply systems for
equipment with rated current Iin > 16A per phase
 European EN61000-3-2 (2006): 1995-09-16 實施，自
2009 年 2 月起僅適用 EN 61000-3-2: 2006
 JIS C61000-3-2 (2005) JIS: Japanese Industrial
Standard
Ch4-184

52
 IEC 61000-3-2
 Equipment to be connected to 220/380 V,
230/400 V and 240/415 V systems operating at
50 Hz or 60 Hz
 No limits for systems with nominal voltage
less than 220 V (line-to-neutral)
 Four categories of equipment: class A, B, C, D

Ch4-185

IEC 61000-3-2
 Class A: balanced 3-phase equipment (rms line
currents differing less than 20 %) and all other
equipment, except those in the following classes
 Class B: portable tools
 Class C: lighting equipment including dimming
devices with active input power above 25 W
 Class D: equipment having an input current with a
"special wave shape" and a fundamental active input
power between 75 and 600 W (Whatever the wave
shape of their input current, Class B, Class C, and
temporarily motor-driven equipment are not
considered as Class D equipment) Ch4-186

53
Classification of Equipment

Ch4-187

Harmonic limits

 1.5

 1.5

Ch4-188

54
Harmonic limits
In
 100%
I1

(%)

Ch4-189

Harmonic limits

Ch4-190

55
Harmonic limits

Ch4-191

56