A 10-bit 50-MS/s SAR ADC for Dual-Voltage
Domain Portable Systems
Wei-Hao Tsai1, Che-Hsun Kuo1, Soon-Jyh Chang1, Li-Tse Lo2, Ying-Cheng Wu2, Chun-Jen Chen2
1Department
of Electrical Engineering, National Cheng Kung University, Tainan, 70101, Taiwan
2Information and Communications Research Laboratories, Industrial Technology Research Institute, Hsinchu, 31040, Taiwan
Abstract — The analog-to-digital converter (ADC) is an essential
component providing the interface between the sensed analog
signal and the corresponding digital representation for a portable
ultrasonic systems. In order to extend the battery life for the
portable system, a low-voltage ADC is crucial for saving the power.
However, the sensed analog signal is usually larger than the
tolerable range of a low-voltage ADC. A level shifter, which
possibly consumes more power than ADC, is therefore adopted to
solve this problem. This paper presents a 10-bit 50-MS/s
successive approximation register (SAR) ADC by manipulating
simple but effective circuit design techniques to operate at dual-
voltage domain without the need of an additional level shifter for
shrinking the input signals. Particularly, we propose a technique
to implement the ADC with 3.3-V I/O devices and 1.2V MOS
transistors. The proof-of-concept design was fabricated in TSMC
130-nm 1P8M CMOS technology. It consumes 1.6 mW at a 50
MS/s sampling frequency and about 2 MHz sinusoidal input signal
with 1.65V input common-mode voltage and 2Vp-p differential
input amplitude. The measurement result shows an ENOB of 9.15
bits, and both the DNL and INL are within 1 LSB. The active area
is 0.226 mm2.
Index Terms－Analog-to-digital converter (ADC), successive
approximation register (SAR), dual-voltage domain, portable
system, ultrasonic system.
I. INTRODUCTION
With advances in CMOS technology, the supply voltage
and the intrinsic impedance of transistors have been reduced for
maintaining circuit reliability and enhancing device speed. This
trend imposes stringent challenges on CMOS operational
amplifier (opamp) designs. Successive approximation register
(SAR) analog-to-digital converters (ADCs) have the advantage
of low power consumption because it does not need to amplify
the signal, i.e. its operation does not rely on opamp, during the
conversion process. In addition to less power consumption,
SAR ADC can be operated at higher speed with the
advancement of technology.
The ultrasonic sensor is the key component of an ultrasonic
system which generates high frequency sound waves and
evaluates the echo received back by the sensor. To realize the
receiver of an ultrasound sensor, a high noise-immunity
amplifier is generally required for amplifying the received
echoes for achieving a better signal-to-noise ratio. The frontend
high noise-immunity amplifier of this work was implemented
with 0.35-µm Silicon-Germanium (SiGe) process with a
nominal supply voltage of 3.3 V. In order to reduce the power
consumption, the SAR ADC and the backend digital circuits
978-1-4799-8391-9/15/$31.00 ©2015 IEEE
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were implemented by 0.13-µm CMOS process with 1.2-V
supply voltage. As the bridge between mixed signal domain,
ADC is connected to high-voltage analog signal from pre-stage
and generate low-voltage digital code for post-stage digital
circuit. In this work, the input common-mode voltage of pre-
stage is 1.65 V and differential input signal swing is 2 Vp-p,
which means that the maximum voltage would reach 2.15 V.
The nominal 1.2-V MOS devices cannot withstand such a high
voltage due to reliability problem.
An intuitive way, shown in Fig. 1-(a), to implement this
SAR ADC is use 0.13µm 3.3-V I/O devices for total transistors
and supply voltage is 3.3V. Due to the fact that power
consumption is proportional to the square of supply voltage, it
will dissipate much more power than the constraint (<5mW) of
this work. Decreasing the supply voltage from 3.3V to 1.2V is
an effective method to reduce the power consumption.
However, the threshold voltage and channel length of 3.3-V I/O
devices are much larger than those of 1.2V MOS transistors. It
is hard to build a 10-bit SAR ADC with 3.3-V I/O devices and
lower supply voltage to achieve the target speed.
An alternative method in Fig. 1-(b) is using a level shifter
to reduce the input common-mode voltage. A level shifter
which combines the source follower and bootstrapped switch
was proposed [1]. However, the source follower is required to
drive the SAR ADC’s capacitor array with about 2pF
capacitance, which is much larger than the 0.4pF capacitive
loading of source follower in [1], resulting in unacceptable
power consumption. Besides, to maintain 2 Vp-p input signal
swing while reducing the common-mode voltage from 1.65 V
to 0.6 V, the over-drive voltage of source follower is too small
to guarantee the linearity of sampled signal for a SAR ADC
under this condition.
In this work, we proposed a and power efficient method for
designing the high speed dual-voltage domain SAR ADC
which consumes 1.6mW when ADC is operated at 50MS/s, 2
MHz input frequency, 1.65V input common-mode voltage,
2Vp-p differential signal range and 1.2V/3.3V supply voltage.
The rest of this paper is organized as follows: Section II
describes the architecture and design concept of the proposed
dual-voltage domain SAR ADC. Section III discusses the
asynchronous control of the dual-voltage domain SAR ADC.
The measurement results are shown in Section IV. Finally,
the conclusion is made in Section V.
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 Sensed slow the speed of switching capacitor and require more settling
Analog Signal
A/D
Digital Output
time because of the high threshold voltage of 3.3-V I/O devices.
In contrast to the bottom-plate sampling method, by top
Sensed
(a)
sampling method, the input signal only passes through the top
Analog Signal Level-
shifter
A/D
Digital Output
plate of the CDAC which are metal lines instead of transistors
by the top-plate sampling method. Hence, the buffer of CDAC
(b)
can be implemented with 1.2V MOS transistor devices to reduce
Fig. 1 Two conventional methods to implement the ADC for dual-voltage the settling time of the switching capacitor.
domain system
Monotonic capacitor switching procedure [2] reduces 81%
Vrefp switching energy and only switches one capacitor once time.
Vrefn BITp,i
C10 C9 C8 C7 C6 C5 C4C C4 C3B C2B C1B However, the common-mode voltage will decrease from Vcm to
VIP Vrefn during the bit cycling. The voltage between gate and
Direct Switching Latch C3A C2A C1A source of the comparator input pair will decrease gradually
Phase1 ~ 10
which induces dynamic offset and affects the accuracy of the
Decoder

D1~D10 BITp,i comparator. Splitting-monotonic switching procedure [3] splits

SAR Control Logic
Phase1 ~ 10
Direct Switching Latch
VIN
C10 C9 C8 C7 C6 C5 C4C C4
Vrefn
Vrefp
Fig. 2 Architecture of the proposed dual-voltage domain
10 bits 50-MS/s SAR ADC
A_ OUTN
A_ OUTN A_ OUTP
VDACP VDACN
OUTP
Clkc
VDC Stage Dynamic Latch Stage
Fig. 3 Hybrid comparator with dynamic voltage-to-delay converter
II. ARCHITECTURE AND DESIGN CONCEPT OF THE PROPOSED
DUAL-VOLTAGE DOMAIN SAR ADC
A. Sample-and-Hold Circuit and Switching Procedure
In Fig. 2, the red lines mean that the voltages at those nodes
are possibly larger than 1.2V, and the voltages on the other
nodes are smaller than or equal to 1.2V. Only the voltages of
sample-and-hold circuit, top plate of capacitive digital-to- -
analog converter (CDAC) and comparator are larger than 1.2V.
Sample-and-hold circuit and comparator use 3.3-V I/O devices
to withstand high voltage. All components in sample- -and-hold
circuit were implemented with 3.3-V I/O devices, and supply
voltage as well as the sampling clock (Clks) is 3.3V in this
design. The architecture of sample-and-hold circuit is similar
with [2]. Bootstrapped switch is used to enhance the linearity of
sampled signal.
The input signal is sampled onto the top plate of the CDAC
via bootstrapped switch. Comparing with sampling the input
onto the bottom plate of CDAC, top-plate sampling method does
not require an extra phase to charge the input signal to top plate.
If the bottom-plate sampling method is employed, the high
voltage input signal will go through the bottom plate of the
CDAC which is connected with the reference voltage buffer. As
a result, the reference voltage buffer should be implemented
with 3.3-V I/O devices and Vrefp/Verfn is about 0V/1.2V. It will
Clks
one capacitor into two. The bottom plate of these capacitors are
connected to Vrefp and Vrefn respectively during the reset phase.
C3A C2A C1A After the comparator generates the comparison result, it will
switch one capacitor of a CDAC and switch a capacitor of
C3B C2B C1B another CDAC at once. Such an arrangement maintains the
BITn,i
common-mode voltage constant during the bit cycling to
improve the accuracy of comparator. However, it complicates
the control logic and the layout routing. In this work, we
combined monotonic and splitting-monotonic capacitor
A_ OUTP
switching procedure. The first three capacitors use splitting-
monotonic capacitor switching procedure. The others use
monotonic capacitor switching procedure. This is, 𝐶𝑖 = 2 ×
OUTN
𝐶𝑖+1 for3 < i < 10,𝐶𝑖𝐴 = 𝐶𝑖𝐵 = 2 × 𝐶(𝑖+1)𝐴 = 2 × 𝐶(𝑖+1)𝐵 for
1 ≤ 𝑖 < 3 and 𝐶4 = 𝐶3𝐴 . The redundant capacitor, 𝐶4𝐶 = 𝐶4 ,
Clkc
is inserted to correct incomplete settling [5]. The number of
splitting capacitors is determined by the dynamic offset of the
comparator.
B. Hybrid Comparator
Another block requiring 3.3-V I/O devices is comparator.
The comparator employed in this design is composed of
dynamic voltage-to-delay converter (VDC) and regenerative
latch as shown in Fig. 3 [4]. This two-tail dynamic comparator
is chosen to minimize the power consumption and to avoid DC
bias. The sampled high-voltage signal will connect to the VDC.
An intuitive implementation is construct all components of
VDC with 3.3-V I/O devices as well as 3.3-V supply voltage and
0V/3.3V Clkc. In a 10-bit 50-MS/s SAR ADC, comparator will
compare the sampled voltage more than 10 times. It means that
Clkc must operate at higher than 500MHz. However, it is very
difficult to implement a level converter (1.2V -> 3.3V) operated
on such a high speed with low power consumption.
In this work, the supply voltage of hybrid comparator is 1.2V
and only the input transistors of VDC, the red elements in Fig.
3, are built with 3.3-V I/O devices. The devices connected to
Clkc use 1.2-V MOS transistors. The proposed dual-voltage
domain SAR ADC does not require level converter to start up
the hybrid comparator. The dynamic latch stage of hybrid
comparator need not use 3.3-V I/O devices and 3.3V supply
voltage.

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 Top Plate
Metal 6
Metal 5
Metal 4
Metal 3
Bottom Plate
Fig.4 Unit 3-D capacitor
Clks
~ ~ ~ ~ ~
Pulse 1
Pulse 2
Pulse 3
...
Clkc
Fig. 5 Time diagram of SAR control logic
C. 3-D Capacitor
For a high resolution SAR ADC, high linearity capacitor
array is necessary to guarantee that the switching voltage is
binary weighting. Traditional MIM capacitor array needs large
area to promote the linearity. As the area of capacitor array
increases, the capacitance will become larger. It will increase the
input capacitive loading, switching power and capacitor
switching time. Otherwise, the capacitor array calibration is
required to achieve the resolution for the specification.
[6] proposes a 3-D mesh capacitor of which capacitance is
determined by the distance between central metals and
surrounding metals instead of the area of metals. Sourrounding
metals are top plate of CDAC. The central metals are bottom
plate. The area of CDAC is small and just contributes 7.7% of
the total area in [6]. However, the parastic capacitance of top
plate to ground is large. It brings about gain error and requires
to increase Vref to slove this problem.
In this work, central metals are top plate and surrounding
metals are bottom plate so as to reduce the parastic capacitor to
ground. We also just used metal4 to metal5 and metal3 to metal6
to implement the top plate and bottom plate of CDAC
respectively to achieve this objective. The perspective view of
unit 3-D capacitor is shown in Fig. 4. To realize a small
capacitance, the distance of central metals and surrounding
metals is larger than the limit of designer’s law. It may increase
the area of CDAC. Whereas it is still smaller than the area of
MIM capacitor. Unit capacitance is about 4.32fF. There does not
exist capacitor array calibration in this work.
III. THE ASYNCHRONOUS CONTROL OF SAR ADC
SAR ADC requires a high-frequency clock, Clkc, to control
the comparator operated several times. Traditional SAR ADC
needs off-chip clock generator or extra phase-lock loop (PLL)
to produce it. Due to the fact that it may dissipate more energy
than ADC core, many designers used internal digital circuit to
generate Clkc in recently years.
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Q
D Q
Clk D
Clk
(a) (b)
Fig. 6 (a) Conventional TSPC (b) Proposed TSPC
An asynchronous control procedure is shown in [2]. The
outputs of comparator generate Valid signal to trigger the D-
type flip-flop. Then, switch the capacitor and reset the
comparator. After resetting the comparator, comparator will
begin next comparison. However, before switching capacitor,
it requires long delay time of digital circuits which will increase
the settling time of switching capacitor. It limits the speed of
high resolution SAR ADC. To resolve this problem, a direct
switching technique, which replaces the clock generator by a
pulse generator, is shown in [6]. The pulse turns on the latch
before the comparator produces the comparing result. The
delay time between the result of comparator and capacitor
switching is much smaller than [2]. However, the pulse
generator in [6] is more complex than the clock generator in [2].
In this work, the architecture of proposed pulse generator
only includes a sequence of D-type flip-flops and an OR gate.
The outputs of comparator are reseted to 1.2V during the
sampling cycle. It will not switch CDAC even if it turn on the
latch. Hence, Pulse 1, which control whether or not switch the
MSB’s capacitor, is turned on when Clks is high. Same with [2],
after comparator generate the result, Valid is high and the latch
reads the value and then switch the capacitors. After the delay
of digital logic gates, Clkc signal will be high and trigger next
D-type flip-flop which will make Pulse 2 high. Afterwards,
Pulse 2 resets Pulse 1. When OUTP and OUTN are reset to high,
Valid and Clkc will be discharged to 0 and comparator begin
the second comparion. Remaining cycles are similar. The
widths of the pulse are determined by the comparing speed of
the comparator to achieve an asynchrous control logic. Time
diagram of sampling clock, Clks, and SAR control logic is
shown in Fig. 5. Only the first D-type flip-flop needs the
function of reset.
The conventional TSPC D-type flip-flop is shown in Fig. 6-
(a). D is high only once time per sampling cycle in SAR control
logic. D is low at most of time. The output of second stage of
the conventional TSPC, the blue line in Fig. 6-(a), will be
charged to VDD or discharged to GND when Clk is changed. It
wastes extra energy even if the D-type flip-flop do not change
the output value, Q. We added extra PMOS, the blue element
in Fig. 6-(b), to prevent excess power dissipation. When D is
low, the extra PMOS is operated in the cut-off region and the
second stage will not be charged to VDD.
 V. CONCLUSION
In this paper, a power efficient dual-voltage design
technique for SAR ADC was proposed by minimizing the use
of 3.3V high supply voltage and 3.3-V I/O devices. The SAR
ADC with the proposed technique can directly connect different
voltage-domain for portable systems without using level shifter.
Besides, power consumption in digital circuits is reduced by
proposed pulse generator and proposed TSPC. The prototype
achieves 50-MS/s operation speed with 1.6mW power
Fig. 7 Die mircophotograph of the SAR ADC consumption, has a FoM of 56.3 fJ/conversion-step and
occupies an active area of 0.226 mm2.
65
50MHz
35MHz
ACKNOWLEDGMENT
60
The authors would like to express their gratitude to
SNDR (dB)

Industrial Technology Research Institute, Taiwan, for the chip

55 implementation.
TABLE I
50
0 5 10 15 20 25
COMPARISON TO STATE-OF-THE-ART WORKS
Frequency (MHz)
Specification [2] [7] [8] This Work
Fig. 8 Measured SFDR and SNDR
Architecture SAR Pipeline SAR SAR
1 Technology (nm) 130 130 90 130
Supply Voltage (V) 1.2 3 1 3.3 / 1.2
DNL

0
Vcm (V) 0.6 1.5 0.5 1.65
-1
0 200 400 600 800 1000
code Sampling Rate(MS/s) 50 50 30 35 50
1
Resolution (bits) 10 12 10 10 10
ENOB (bits) 9.18 11.05 9.16 9.37 9.15
INL

-1 Power (mW) 0.826 51 0.98 0.96 1.6

0 200 400 600 800 1000
code
FoM (fJ/step) 29 480 57 41.2 56.3
Fig. 9 Measured DNL and INL
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0
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Magnitude (dB)

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-100
-150
-200
0 5 10
Frequency (MHz)
Fig. 10 Measured FFT spectrum
IV. MEASUREMENT RESULTS
The proposed SAR ADC is fabricated in a 130nm 1P8M
CMOS technology. Fig. 7 shows the die mircophotograph of
chip. The area of ADC core is 463×488 μm2, and the area of one
capacitor array is 274×136 μm2 which contributes 16.5% of the
total area. Fig. 8 is about the figure of SNDR corresponding to
different input frequency. The measurement DNL and INL are
+0.2926 / -0.6431 LSB and +0.9383 / -0.7082 LSB respectively
in Fig. 9. The measurement ENOB and power consumption are
9.15 bits and 1.6 mW respectively at 50 MS/s with around 2
MHz input frequency. The peak SNDR shown in Fig. 10 is
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SAR ADC and the comparison with other state-of-the-art works.
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