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ICPSET-2022 IOP Publishing
Journal of Physics: Conference Series 2242 (2022) 012035 doi:10.1088/1742-6596/2242/1/012035

Analytical and Measurement-Based Method for Diagnosing

the Fault of Channels in TSV-Based 3D ICs

Chenbing Qu*, Linting Zheng, Liwei Wang and Chen Sun

Science and Technology on Reliability Physics and Application of Electronic,
Component Laboratory, China Electronic Product Reliability and Environmental
Testing Research Institute, Guangzhou, 511370, China
Email: quchenbing@126.com

Abstract. Three-dimensional integrated circuits (3D ICs) based on through silicon via (TSV)
technology can effectively solve many bottlenecks in the development of ICs. It has rapidly
developed into a key cutting-edge technology representing the medium and long-term
sustainable development of microelectronics industry. Process fluctuation causes TSV process
defects, resulting in the change of structural parameters of RDL and TSV interconnection
structure. Finally, it leads to the degradation of performance parameters and functional failure
of 3D interconnection and devices. Aiming at the high-resistance and open-circuited faults of
3D ICs, this paper develops an analysis method based on micro nano machining and detection
technology. The electrical characteristics and images of typical chain TSV interconnections are
analyzed by scanning electron microscope high-resolution imaging. The mechanism of fault
diagnosis is based on potential difference and electron transfer.
Keywords: Through-silicon vias (TSVs), Fault diagnostics, Measurement, Chain TSV
Interconnections

1. Introduction
With the continuous reduction of integrated circuit technology nodes below 10nm, interconnection
delay, reliability and bandwidth have become the main bottlenecks for the improvement of system
performance and energy efficiency [1]. Three-dimensional integrated circuits (3D ICs) based on
through-silicon via (TSV) technology is the integration mode of the next generation of integrated
circuits. 3D integration technology can integrate different devices and different IP cores on the same
chip to form a more complete system on chip (SOC) [2]. RF front-end is an important component of
mobile communication equipment, including transmitting path and receiving path. The development
history of mobile communication has gradually crossed the digital era and mobile Internet era. 3D IC
technology provides technical support for the realization of 5G ICs with ultra-low power consumption,
ultra-high density, ultra-high reliability, high security and ultra-low delay.
With the development of 3D IC industrialization in SOC and RF ICs, the demand for reliability
research of interconnection and packaging is becoming increasingly prominent. In the manufacturing
process of TSV of 3D ICs, factors such as uneven filling and incomplete chemical mechanical
polishing will lead to short circuit and open circuit defects. In particular, the 3D interconnection in
glass cavity in silicon substrate is also known as trough-glass via (TGV), and its manufacturing
process is not mature. The novel and complex three-dimensional integrated design method and
manufacturing process also introduce some new reliability and safety problems, such as thermal stress,
mechanical stress and signal coupling, resulting in TSV interconnection defects. Under micro nano

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ICPSET-2022 IOP Publishing
Journal of Physics: Conference Series 2242 (2022) 012035 doi:10.1088/1742-6596/2242/1/012035

size, TSV process defects are caused by process level and process fluctuation [3]. Before wafer
binding, defects such as insulation wall damage, metal cavity and incomplete filling are easy to occur
in the process of etching through holes, oxide deposition and copper plating, resulting in TSV leakage
or open circuit fault; In the process of wafer bonding, the thermal stress caused by different thermal
expansion coefficients of materials leads to TSV bulging and fracture defects; In the process of wafer
bonding, the size of micro bumps is larger than the diameter of TSV, the solder density is large, and
short circuit faults are easy to occur, and inaccurate alignment may lead to three-dimensional
interconnection failure. Figure 1 shows SEM photos of several common defects of TSV [4-5]. During
the use of 3D integrated circuits, internal and external stresses caused by temperature cycle, copper
creep and other factors produce interconnection damage, and TSV copper bulge, crack, cavity and
solder joint cavity defects appear. In addition, the manufacturing process of some new TSV structures
like shaft TSV is more complex, and the failure mode has not been studied enough.

Figure 1. SEM images of common defects of TSV [4-5].

In 3D ICs and microsystems, there are multilayer stacked chips. At present, a common detection
method is to observe surface integrity through high-resolution electron microscope imaging can only
screen the visible process defect products to a certain extent. However, it is difficult to effectively
identify the internal defects of 3D stacked chips. The traditional imaging positioning method can not
guarantee the functional performance of stacked on-chip components. At the same time, with the
increase of the scale of integrated circuit design, the traditional screening methods are difficult to
realize automatic detection, and can not fundamentally meet the reliability detection requirements of
large-scale automatic production.
In case of metal short circuit, it is necessary to find the fault point through failure analysis and infer
the root cause of short- or open-circuit metal. Failure analysis is divided into electrical analysis and
physical analysis. For metal short circuit, we will take electrical analysis as the starting point, use
professional electrical failure positioning equipment to locate the failure point, then use physical
analysis to determine the physical performance of metal short circuit, and finally deduce the root cause
of failure, in which the positioning of failure point is a very key step. D. H. Jung et al. [4] studied the
equivalent circuit model of multilayer ground signal ground TSV chain structure. In the literature,
fault detection is carried out based on the changes of S parameters and time-domain voltage
parameters. This method requires very high microwave measurement accuracy. The destructive
physical analysis (DPA) of sections is used in references [5] and [6]. However, in multilayer stacked
3D ICs, internal defects of 3D components may exist in the substrate. It is difficult to determine where
the DPA needs to be. Moreover, the DPA technology will also have a certain impact on different
substrate materials of heterogeneous integrated chips, thus affecting the diagnosis of defect location.
In order to further provide the quality of integrated circuits, this paper studies the defect detection
method based on the joint location of nano probe and EBIC, mainly including high-resolution imaging,
high resistance fault and open circuit fault location between metals. Two powerful yet simple analysis
techniques for detecting failures in semiconductors are Electron Beam Induced Current (EBIC) [7] and
Electron Beam Induced Resistance Change (EBIRCh) [8]. Both methods use the electron beam to
generate a current on a sample- the current is then amplified for imaging purposes. A high-ohmic short
between two metal lines is examined using the Prober Shuttle.

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ICPSET-2022 IOP Publishing
Journal of Physics: Conference Series 2242 (2022) 012035 doi:10.1088/1742-6596/2242/1/012035

This study can provide a critical path failure analysis method for 3D IC. Combined with the
destructive physical analysis and the electrical characteristics of the device, the internal failure is
detected in the metal layer. It makes the diagnosis of interconnect failure and device failure more
efficient and accurate. The internal interconnection defects of 3D integrated devices can be diagnosed
after chip polishing. This technology is suitable for the failure analysis of finished chips. Considering
that the electrical characteristic parameters and physical size parameters of the component are not
clear, inspectors can preliminarily judge whether there are defects in the substrate of the integrated
device through this method. It will improve the efficiency and accuracy of internal defect detection of
3D IC and microsystem.

2. Measurement System
In the process of semiconductor manufacturing, short-circuit or open-circuit failure often occurs in the
rear metal interconnection line, which mainly comes from design problems and process problems. In
order to evaluate the design structure and monitor the process stability on the line, extract the complex
product structure separately or use this structure as a unit to reform a repeated, large-area and easy to
test structure. A large number of corresponding electrical parameters are obtained through the
electrical test of these test structures. These electrical parameters are analyzed to find and solve
problems in advance. So, this structure covers almost all levels of the manufacturing process, has a
variety of structures, and is easy to test and easy to failure analysis.
The working principle of EBIRCh is to scan the device surface by electron beam under constant
voltage, induce the change of resistance by electron beam, and detect the change of current value at the
induction point to locate the defect position. Generally used for short circuit. EBIRCh technology is a
high-order function of the new generation Nano Probe measurement device. It is equipped with
electron microscope, with high magnification (up to tens of thousands of times), high positioning
accuracy and can locate short circuits.
EBIC images are created from electrons that penetrate through the semiconductor’s oxide and
metal layers to the p-n junctions generating electron hole pairs. These are separated by the diffusion
voltage and measured as a current that flows through the probe. The signal is fed back to the SEM to
obtain a current map of the sample.
The defect measurement of TSV interconnect metals of existing 3D IC is mainly for the failure
analysis of TSV daisy chain structure. By testing whether there is current passing between the
serpentine metal wire and the comb metal wire, researchers can judge whether there is a metal short
circuit.

SEM
SE-
DEC Electron
beam
Nano
probe

Nano manipulator
controller

Figure 2. EBIRCh and EBIC measurement system.

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ICPSET-2022 IOP Publishing
Journal of Physics: Conference Series 2242 (2022) 012035 doi:10.1088/1742-6596/2242/1/012035

The software and hardware system tested is shown in figure 2. The measurement system mainly
includes SEM, nano manipulator, nano probe, control module, ohmic test source meter and image
display. Firstly, build the device system. The main body of the equipment is scanning electron
microscope. The SEM includes backscatter and secondary electron gun, movable sample table, CCD
camera, etc; Several nano probes are assembled inside. The external nano manipulator controller
controls the probe through the data line, and the controller has an interface to connect the resistance
capacitance test instrument. The server and display are connected externally, and the server host is
equipped with the control software system of the scanning electron microscope. Operations include
equipment startup, installation of nano probes, connection of external control instruments, etc. Sample
preparation refers to the process of entering the sample bin of scanning electron microscope. Choose
whether to carry out surface grinding and gold spraying treatment according to the condition of the
sample, and then fix the sample on the sample table with conductive adhesive. Sample warehousing,
including placing the sample into the warehouse, vacuumizing the electron microscope, adjusting the
sample table to a suitable position. Aftering positing the point to be measured, put the probe in place
on the screen and take the original image. Then, connect the ohmic test source meter and control the
nano probe to be placed on the test structure. Finally, the resistance between the two test points is
obtained by ohmic test source meter.
In this study, the defects of 3D silicon-based integrated inductors are shown. The spiral inductor is
a daisy-chain-like interconnection structure of multiple TSV/TGVs and RDLs, as shown in figure 3.
The component surface is scanned by electron beam under constant voltage, the change of resistance is
induced by electron beam, and the change of current value at the induction point is detected to locate
the defect position. However, for the short-circuit failure of large area interconnection test structures,
ebirch can not effectively locate the short-circuit point. In this metal layer, there are two independent
metals. If connectting together through a layer of the lower layer, the two independent metals show the
same charging effect. The ohmic connection between the metal wires of the inductor is low. Ones use
the built test system to judge whether there are open-circuit or high-resistance defects in the inductor.

Nano probe

DPA area
Layer1

E1
Layer2

C1
Q1 Q2 Q2
MT1 Layer3
Q3 Q3

Q5 Q2

ki1 Q3 Q3

Substrate

Figure 3. 3D substrate integrated RF component based on TSV technology.

The probe can be placed on any two metal wires to detect the impedance between them. Thus, the
interconnection defects of TGV and RDL in a coil can be located. The metal resistance between two
probes can be calculated by the analytical impedance of multiple metal wires.
Rprobes = RRDL1 + RTGV 1 + RTGV 2 + RRDL 2 + (1)

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ICPSET-2022 IOP Publishing
Journal of Physics: Conference Series 2242 (2022) 012035 doi:10.1088/1742-6596/2242/1/012035

Figure 3 shows the metals and components in two IC layers. Through the Probes, EBIC and
EBIRCh help researchers to diagnosis failure of underlying metals and components.

3. EBIC imaging of TGV and RDL metals

In this paper, the open circuit and short circuit diagnosis method of 3D interconnection based on
charge induced imaging is studied. Inductors are the most critical passive components in RF integrated
circuits. It is widely used in RF amplifiers, mixers, voltage-controlled oscillators and impedance
matching circuits. It greatly affects the size and cost of microwave integrated circuits. The City
University of New York [9] and the Georgia Institute of technology 3D Packaging Research Center
[10] proposed a three-dimensional inductor structure based on grounded TSV shielding and an ultra-
thin glass substrate embedded inductor for several GHz frequency domain. It comprehensively
optimizes the inductance density, Q value, size and self resonance frequency. As shown in figure 4,
ones can see the TGV-based inductor structure of front and back RDL through optical microscope. 3D
inductors can be formed by glass through-hole (TGV) technology or TSV technology instead of the
original 2D inductors. As we all know, under the same area and inductance, the 3D solenoid
inductance has higher quality value than the two-dimensional spiral inductance. In other words, the 2D
spiral inductor can achieve the same quality factor and inductance as the 3D solenoid inductor, but the
graphics size will be larger. For these reasons, we have studied and published 3-D nested spiral
inductors. When the component is in the SEM sample bin, the electron beam shows image effects of
different brightness on metal and semiconductor materials. The 3-D inductor in this study adopts
surface gold material and glass substrate, and adopts copper TGV process.

Figure 4. Structrue of TGV-based 3D inductor.

TGV Gold

before after

Figure 5. SEM Pictures of TGV-based 3D inductor. (a) Before probe contact; (b) After probe
contact.

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ICPSET-2022 IOP Publishing
Journal of Physics: Conference Series 2242 (2022) 012035 doi:10.1088/1742-6596/2242/1/012035

Figure 5 shows the image changes after the nano probe contacts the metal surface. Use a single
nano probe to contact the metal wire and check the change of metal imaging to observe whether the
on-off condition of the metal wire is complete. The principle of image brightness change is as follows:
• When the surface potential of semiconductor and metal materials is higher than that of nano
probe, the sample begins to show a dark state. After the probe contacts the metal, the positive
charge is transferred from the sample metal to the probe. The potential of the sample
decreased. At this time, the image contrast of the metal in the sample turns white.
• When the surface potential of semiconductor and metal materials is lower than that of nano
probe, the sample begins to show a white state. After the probe contacts the metal, the positive
charge is transferred from the probe to the sample metal. The potential of the contact surface is
higher than that of other surrounding materials. At this time, the image contrast of the metal in
the sample becomes dark.
These three metals on the surface of the 3-D inductor shownare not connected in this metal layer,
but they are short-circuited with the metal at the bottom through TGVs. The potential of the three
metals in the metal layer is basically the same. Before the gold material comes into contact with the
probe, a white image is presented. Through experiments, we found that after the probe contacts the
metal, three metals without connection in this layer are imaged and darkened at the same time.
Therefore, it can be judged that the three metals are short circuited inside the substrate. There is no
open circuit fault in TGV inside the substrate.

4. Conclusion
For analyzing the failure analysis of TSV or TGV in 3-D ICs, this work explored the defect detection
method based on the joint location of nano probe and EBIC. Nano manipulator, nano probe, EBIC and
SEM were to analyze the interconnection of a 3-D component. Through the 3-D spiral inductor
imaging study, the general jugement principles and measurement methods of open circuit and short
circuit faults could be obtained. This work is to carry out defect location and failure analysis of
multilayer stacked nanoscale integrated circuits in the future.

Acknowledgments
Project supported by the Project supported by Science and Technology Program of Guangzhou (Grant
No. 202102020520), Guangdong Basic and Applied Basic Research Foundation (Grant No.
2021A1515011996), and the Key Laboratory Foundation (Grant No. 6142806200104).

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ICPSET-2022 IOP Publishing
Journal of Physics: Conference Series 2242 (2022) 012035 doi:10.1088/1742-6596/2242/1/012035

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