Chapter 4

Sequential Logic Circuits

4–1 The defining characteristic of a combinational circuit is that its output depends only on the current
inputs applied to the circuit. The output of a sequential circuit, on the other hand, depends both
on the current input values as well as the past inputs. This dependence on past inputs gives the
property of “memory” for sequential circuits.

4–2 The sequence of past inputs is encoded into a set of state variables. The feedback circuit stores
this state information and feeds it to the input.

4–3 When the propagation delay is zero, theoretically, signals at the input and output of the inverter
change at the same time. This means the output of the AND gate is always zero.

4–4 When S and R are 1, both outputs are forced to take 0. To see why this combination is undesirable,
consider what happens when S and R inputs are changed from S = R = 1 to S = R = 0. It is only
in theory that we can assume that both inputs change simultaneously. In practice, there is always
some finite time difference between the two signal changes. If the S input goes low earlier than the
R signal, the sequence of input changes is SR = 11 ! 01 ! 00. Because of the intermediate state
SR = 01, the output will be Q = 0 and Q = 1. If, on the other hand, the R signal goes low before
the S signal does, the sequence of input changes is SR = 11 ! 10 ! 00. Because the transition
goes through the SR = 10 intermediate state, the output will be Q = 1 and Q = 0. Thus, when the
input changes from 11 to 00, the output is indeterminate. This is the reason for avoiding this state.

4–5 The truth table is shown below:

S R Q n+1
0 0 1
0 1 0
1 0 1
1 1 Qn

1
2 Chapter 4

It can se seen from this truth table that is not exactly the same as that given for the NOR gate
version. However, it is closely related in the sense it is the dual of the other truth table.

4–6 The D-latch avoids the SR = 11 input combination by using a single inverter to provide only
complementary inputs at S and R inputs of the clocked SR latch as shown below:

S Q

CP

R Q

Clock

4–7 Flip-flops are edge-triggered devices whereas latches are level sensitive.

4–8 The circuit is shown below:

Q0 Q1 Q2 Q3

High
S S S S
J Q J Q J Q J Q

Clock CP CP CP CP

K C Q FF0 K C Q FF1 K C Q FF2 K C Q FF3

Reset
High

4–9 The circuit is shown below:

Q0 Q1 Q2 Q3 Q4

J Q High J Q High J Q High J Q High J Q

Clock CP CP CP CP CP

K Q K Q K Q K Q K Q
High

4–10 The circuit is shown below:

Chapter 4 3

D C B A

J Q J Q J Q J Q

Clock CK CK CK CK

K Q K Q K Q K Q

High

4–11 We need four JK flip-flops to implement this four-bit counter. The design table is shown below:

Present state Next state JK flip-flop inputs

A B C D A B C D JA KA JB KB JC KC JD KD

0 0 0 0 0 0 1 0 0 d 0 d 1 d 0 d
0 0 0 1 d d d d d d d d
0 0 1 0 0 1 0 0 0 d 1 d d 1 0 d
0 0 1 1 d d d d d d d d
0 1 0 0 0 1 1 0 0 d d 0 1 d 0 d
0 1 0 1 d d d d d d d d
0 1 1 0 1 0 0 0 1 d d 1 d 1 0 d
0 1 1 1 d d d d d d d d
1 0 0 0 1 0 1 0 d 0 0 d 1 d 0 d
1 0 0 1 d d d d d d d d
1 0 1 0 1 1 0 0 d 0 1 d d 1 0 d
1 0 1 1 d d d d d d d d
1 1 0 0 1 1 1 0 d 0 d 0 1 d 0 d
1 1 0 1 d d d d d d d d
1 1 1 0 0 0 0 0 d 1 d 1 d 1 0 d
1 1 1 1 d d d d d d d d
4 Chapter 4

Using the Karnaugh map method, we can get the simplified logical expressions for the J and K
inputs as follows:
JA = B C; KA = BC
JB = C, KB = C
JC = 1; KC =1

JD = 0; KD = d
Notice that the D flip-flop is not necessary as its output is always 0. The circuit is shown below:

D C B A

J Q J Q J Q

CK CK CK

K Q K Q K Q

High

Clock

4–12 We need three JK flip-flops to implement this four-bit counter. The design table is shown below:

Present state Next state JK flip-flop inputs

A B C A B C JA KA JB KB JC KC

0 0 0 0 0 1 0 d 0 d 1 d
0 0 1 0 1 1 0 d 1 d d 0
0 1 0 1 1 0 1 d d 0 0 d
0 1 1 0 1 0 0 d d 0 d 1
1 0 0 0 0 0 d 1 0 d 0 d
1 0 1 1 0 0 d 0 0 d d 1
1 1 0 1 1 1 d 0 d 0 1 d
1 1 1 1 0 1 d 0 d 1 d 0

Using the Karnaugh map method, we can get the simplified logical expressions for the J and K
inputs as follows:
Chapter 4 5

JA = BC; KA =BC

JB =A C; KB = AC
JC =AB + A B; KC =A B + AB
The circuit is shown below:

C B A

J Q J Q J Q

CK CK CK

K Q K Q K Q

Clock

4–13 The state table is shown below:

Next state Output

Present state X=0 X=1 X=0 X=1

S0 S0 S1 0 1
S1 S1 S0 1 0

Simple state assignment: S0 = 0 and S1 = 1.

Present Present Next Present

JK flip-flop inputs
state state state state
A X A Y JA KA

0 0 0 0 0 d
0 1 1 1 1 d
1 0 1 1 d 0
1 1 0 0 d 1
6 Chapter 4

Using the Karnaugh map method, we can get the simplified logical expressions for the J and K
inputs and the output Y as follows:
JA = X; K A = X
Y=AX + A X
The circuit is shown below:

Y
J Q

Clock CK

X K Q

4–14 The Karnaugh map for the state assignment is shown below:

BC
A 00 01 11 10

0 S0 S3 S5

1 S1 S6 S4 S2

Final state assignment is shown below:

State A B C

S0 = 0 0 0
S1 = 1 0 0
S2 = 1 1 0
S3 = 0 0 1
S4 = 1 1 1
S5 = 0 1 0
S6 = 1 0 1

The design table is shown below:

Chapter 4 7

Present Present Next Present

JK flip-flop inputs
state state state state
A B C X A B C Y JA KA JB KB JC KC

0 0 0 0 1 1 0 0 1 d 1 d 0 d
0 0 0 1 1 0 0 0 1 d 0 d 0 d
0 0 1 0 1 1 1 0 1 d 1 d d 0
0 0 1 1 0 0 1 0 0 d 0 d d 0
0 1 0 0 1 1 1 1 1 d d 0 1 d
0 1 0 1 0 0 1 0 0 d d 1 1 d
1 0 0 0 1 1 1 0 d 0 1 d 1 d
1 0 0 1 0 0 1 0 d 1 0 d 1 d
1 0 1 0 1 0 1 0 d 0 0 d d 0
1 0 1 1 0 1 0 1 d 1 1 d d 1
1 1 0 0 1 0 1 0 d 0 d 1 1 d
1 1 0 1 0 1 0 0 d 1 d 0 0 d
1 1 1 0 1 0 1 1 d 0 d 1 d 0
1 1 1 1 0 1 0 0 d 1 d 0 d 1

Using the Karnaugh map method, we can get the simplified logical expressions for the J and K
inputs as follows:
JA = X + B C; KA = X
JB =CX + AX + A C X; KB =A X + AX
JC = AB + A B + A X; KC = AX
The Y output logical expression is:
Y=ABCX + BCX + ABX
It is straightforward to complete the solution using these expressions (similar to what is shown in
Figures 4.27 and 4.28).

4–15 We can use the same circuit; all we have to do is invert the input.

4–16 The state diagram is shown below:

8 Chapter 4

You can see from this state diagram that the design remains the same as that for the pattern recog-
nition example on page 134 (see Example 2). However, we need to modify the output Y. In the Y
column in Table 4.8, the last two 1s should be zero. This gives us the following expression for the
only 1 in that column:
Y = A B C X.
The implementation is as shown in Figure 4.28 (substitute the following circuit for the Y logic
circuit given in Figure 4.8b):

B
Y
C

4–17 The state diagram is shown below:

Chapter 4 9

Next state Output

Present state X=0 X=1 X=0 X=1

S0 S1 S0 0 0
S1 S1 S2 0 0
S2 S0 S0 1 0

Heuristic 1 groupings: (S0, S1) (S0, S2)

Heuristic 2 groupings: (S0, S1) (S0, S2)

These groupings suggest the following state assignment:

B
A 0 1

0 S0 S1

1 S2

Final state assignment is shown below:

State A B

S0 = 0 0
S1 = 0 1
S2 = 1 0

The design table is shown below:

10 Chapter 4

Present Present Next Present

JK flip-flop inputs
state state state state
A B X A B Y JA KA JB KB

0 0 0 0 1 0 0 d 1 d
0 0 1 0 0 0 0 d 0 d
0 1 0 0 1 0 0 d d 0
0 1 1 1 0 0 1 d d 1
1 0 0 0 0 1 d 1 0 d
1 0 1 0 0 0 d 1 0 d

Using the Karnaugh map method, we can get the simplified logical expressions for the J and K
inputs as follows:

JA = B X; KA =1

JB = A X; KB = X

The Y output logical expression is:

Y=AX

The implementation is shown below:

B A
J Q J Q
Y
CK CK

X K Q K Q

High

Clock

4–18 The state diagram is shown below:

Chapter 4 11

01/0

01/0 01/0 01/0 01/0 01/1

00/0 S0 S1 S2 S3 S4 S5

00/0 00/0 00/0 00/0 00/0

10/1

10/0 10/0 10/0 10/1

10/0

The state table is shown below:

Next state Output Z

Present state XY = 00 XY = 01 XY = 10 XY = 00 XY = 01 XY = 10

S0 S0 S1 S2 0 0 0
S1 S1 S2 S3 0 0 0
S2 S2 S3 S4 0 0 0
S3 S3 S4 S5 0 0 0
S4 S4 S5 S5 0 1 1
S5 S5 S1 S2 0 0 0

Heuristic 1 groupings: (S0, S5) 2 (S3, S4)

Heuristic 2 groupings: (S1, S2) 3 (S2, S3)2 (S4, S5)2 (S3, S4)2
Heuristic 3 groupings: None
These groupings suggest the following state assignment:
12 Chapter 4

BC
A 00 01 11 10

0 S0 S3 S2

1 S5 S4 S1

Final state assignment is shown below:

State A B C

S0 = 0 0 0
S1 = 1 1 1
S2 = 0 1 1
S3 = 0 0 1
S4 = 1 0 1
S5 = 1 0 0

The design table is shown below:

Chapter 4 13

Present Present Next Present

JK flip-flop inputs
state state state state
A B C XY A B C Z JA KA JB KB JC KC

0 0 0 00 0 0 0 0 0 d 0 d 0 d
0 0 0 01 1 1 1 0 1 d 1 d 1 d
0 0 0 10 0 1 1 0 0 d 1 d 1 d
0 0 1 00 0 0 1 0 0 d 0 d d 0
0 0 1 01 1 0 1 0 1 d 0 d d 0
0 0 1 10 1 0 0 0 1 d 0 d d 1
0 1 1 00 0 1 1 0 0 d d 0 d 0
0 1 1 01 0 0 1 0 0 d d 1 d 0
0 1 1 10 1 0 1 0 1 d d 1 d 0
1 0 0 00 1 0 0 0 d 0 0 d 0 d
1 0 0 01 1 1 1 0 d 0 1 d 1 d
1 0 0 10 0 1 1 0 d 1 1 d 1 d
1 0 1 00 1 0 1 0 d 0 0 d d 0
1 0 1 01 1 0 0 1 d 0 0 d d 1
1 0 1 10 1 0 0 1 d 0 0 d d 1
1 1 1 00 1 1 1 0 d 0 d 0 d 0
1 1 1 01 0 1 1 0 d 1 d 0 d 0
1 1 1 10 0 0 1 0 d 1 d 1 d 0

Using the Karnaugh map method, we can get the simplified logical expressions for the J and K
inputs as follows:
JA =B Y + C X; KA = BX + BY + C X
JB =C X + C Y; K B = X + A Y
JC = X + Y; K C =B CXY + ABCXY
The Z output logical expression is:
Z = A B C (X Y + X Y)
It is straightforward to complete the solution using these expressions (similar to what is shown in
14 Chapter 4

Figures 4.27 and 4.28).

4–19 The state diagram is shown below:

01/00 01/00

01/00 01/00 01/00 01/00 01/01

00/00 S0 S1 S2 S3 S4 S5 S6

00/00 00/00 00/00 00/00 00/00 00/00

10/00 10/00 10/00 10/10 10/11

10/00
10/00

Note that the output is represented by two bits: CZ. The C bit indicates change due and the Z bit
indicates activation of the selection circuit (as in the last exercise).
The state table is shown below:

Next state Output CZ

Present state XY = 00 XY = 01 XY = 10 XY = 00 XY = 01 XY = 10

S0 S0 S1 S2 00 00 00
S1 S1 S2 S3 00 00 00
S2 S2 S3 S4 00 00 00
S3 S3 S4 S5 00 00 00
S4 S4 S5 S5 00 01 11
S5 S5 S1 S2 00 00 00
S6 S6 S1 S2 00 00 00

Heuristic 1 groupings: (S0, S5, S6) 2 (S3, S4)

Heuristic 2 groupings: (S1, S2) 4 (S2, S3)2 (S4, S5)2 (S3, S4)2
Chapter 4 15

Heuristic 3 groupings: None

These groupings suggest the following state assignment:

BC
A 00 01 11 10

0 S0 S3 S2

1 S5 S4 S1 S6

Final state assignment is shown below:

State A B C

S0 = 0 0 0
S1 = 1 1 1
S2 = 0 1 1
S3 = 0 0 1
S4 = 1 0 1
S5 = 1 0 0
S6 = 1 1 0

The design table is shown below:

16 Chapter 4

Present Present Next Present

JK flip-flop inputs
state state state state
A B C XY A B C CZ JA KA JB KB JC KC

0 0 0 00 0 0 0 00 0 d 0 d 0 d
0 0 0 01 1 1 1 00 1 d 1 d 1 d
0 0 0 10 0 1 1 00 0 d 1 d 1 d
0 0 1 00 0 0 1 00 0 d 0 d d 0
0 0 1 01 1 0 1 00 1 d 0 d d 0
0 0 1 10 1 0 0 00 1 d 0 d d 1
0 1 1 00 0 1 1 00 0 d d 0 d 0
0 1 1 01 0 0 1 00 0 d d 1 d 0
0 1 1 10 1 0 1 00 1 d d 1 d 0
1 0 0 00 1 0 0 00 d 0 0 d 0 d
1 0 0 01 1 1 1 00 d 0 1 d 1 d
1 0 0 10 0 1 1 00 d 1 1 d 1 d
1 0 1 00 1 0 1 00 d 0 0 d d 0
1 0 1 01 1 0 0 01 d 0 0 d d 1
1 0 1 10 1 0 0 11 d 0 0 d d 1
1 1 0 00 1 1 0 00 d 0 d 0 0 d
1 1 0 01 1 1 1 00 d 0 d 0 1 d
1 1 0 10 0 1 1 00 d 1 d 0 1 d
1 1 1 00 1 1 1 00 d 0 d 0 d 0
1 1 1 01 0 1 1 00 d 1 d 0 d 0
1 1 1 10 0 0 1 00 d 1 d 1 d 0

Using the Karnaugh map method, we can get the simplified logical expressions for the J and K
inputs as follows:
JA =B Y + C X; KA = BX + BCY + C X
JB =C X + C Y; K B = X + A Y
Chapter 4 17

JC = X + Y; K C =B CXY + ABCXY
The C and Z output logical expressions are:
C=ABCXY
Z = A B C (X Y + X Y)
It is straightforward to complete the solution using these expressions (similar to what is shown in
Figures 4.27 and 4.28).