28F512 512K (64K x 8) CMOS FLASH MEMORY i Flash Electrical Chip-Erase m Command Register Architecture for —1 Second Typical Chip-Erase Microprocessor/Microcontroller 1 Quick-Pulse Programming Algorithm Compatible Write Interfa —10 1s Typical Byte-Program © Nolse Immunity Features —1 Second Chip-Program — +10% Vc Tolerance ® 100,000 Erase/Program Cycles —Maximum Latch-Up Immunity through EPI Processing m= ETOX I! Nonvolatile Flash Technology m 120V +5% Vp @ High-Performance Read —EPROM-Compatible Process Base — 120 ns Maximum Access Time —High-Volume Manufacturing m CMOS Low Power Consumption Experience —10 mA Typical Active Current m JEDEC-Standard Pinouts —50 1A Typical Standby Current —32-Pin Plastic Dip — OW Data Retention Power —32-Lead PLCC @ Integrated Program/Erase Stop Timers feetaeeinret eee m Extended Temperature Options Intel's 28512 CMOS flash memory offers the most costetfective and reliable alternative for read/write random access nonvolatile memory. The 28F512 adds electrical chip-erasure and reprogramming to far EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; on- board during subassembly test; in-system during final test; and in-system after-sale. The 28F512 increases memory flexibility, while contributing to time: and cost-savings. The 28F512 is a 512-kilobit nonvolatile memory organized as 65,536 bytes of 8 bits. Intel's 28F512 is offered in 32-pin plastic dip or 32-Ioad PLCC packages. Pin assignments conform to JEDEC standards for byte-wide EPROMs, Extonded erase and program cycling capabilty is designed into intal's ETOX Il (EPROM Tunnel Oxide) pro cess technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field com- bine to extond raiable cycling beyond thet of traditional EEPROM. With the 120V Vep supply, the 28F512 Berforms 100,000 erase and program cycles wel within the time limts of the Quick-Pulse Programming and Ouick-Erase algorithms Intel's 28512 employs advanced CMOS circuitry for systems raquiring high-performance access speeds, low ower consumption, and immunity to noise. Its 120 nanosecond access time provides no-WAIT-state perform ance for a wide range of microprocessors and microcontrollers. Maximum standby current of 100 A trans- lates into power savings when the device is deselected. Finally, the highest degree of latch-up protection is achieved through Intel's unique EP! processing. Prevention of latch-up is provided for stresses up to 100 mA ‘on address and data pins, from -1V to Vog + 1V. With Intel's ETOX II process base, the 28F512 levers years of EPROM experience to yield the highest levels of auality, reliability, and cost-offectiveness. November 1994 6-60 (Order Number: 290204-00828F512 004-00, Yo Ys —> 0 a8e4y Source stare come wer conwane intecnare stor ew voLiace twee ‘smTen cee ove foots TooRess Lavon 524,280 ot rut waraix Figure 1, 28F512 Block Diagram —| 66128F512 intel ° raarsiz Pe oan 64 Grape Nott Sone 0004-2 "Figure 2. 28F512 Pin Configurations. Table 1. Pin Description Symbol Type Name and Function Ao-Ais | INPUT ‘ADDRESS INPUTS for memory addresses. Addresses are internally latched during a write cycle 0Q9-0Q, | INPUT/OUTPUT | DATA INPUT/OUTPUT: Inputs data during memory write cycles; ‘outputs data during memory read cycles. The data pins are actve high and loat to t-state OFF when the chip is deselected or the outputs are disablod, Data is internally latched during a write cyclo, cee INPUT CHIP ENABLE: Activates the device's contol logic, input butters, decoders and sense amplifiers. CE is active low; CE high doselects the memory device and reduces power consumption to standby levels OE* INPUT ‘OUTPUT ENABLE: Gatos the devices output through the data butfors during a read cycle, OF # is active low. wee INPUT WRITE ENABLE: Controls wites to the control register and the array. Write enable is active low. Addresses are latched on the falling edge and datas latched on the rising edge of the WE # pulse. Note: With Vpp < 6.5V, memory contents cannot be altered. Ver ERASE/PROGRAM POWER SUPPLY for writing the command register, erasing the entire array, or programming bytes in the arcay. Voc DEVICE POWER SUPPLY (5V + 10%) Vss GROUND NC NO INTERNAL CONNECTION to device. Pin may be driven or let floating 6-62intel. APPLICATIONS The 28F512 flash memory provides nonvolatilty along with the capability to perform over 100,000 electrical chip-erasure/reprogram cycles. These tures make the 28F512 an innovative alternative to disk, EEPROM, and battery-backed static RAM. Where periodic updates of code and data-tables are required, the 28F512's reprogrammabilty and non- volatility make it the obvious and ideal replacement for EPROM. Primary applications and operating systems stored in flash eliminate the slow disk-to-ORAM download process. This results in dramatic enhancement of performance and substantial reduction of power consumption — a consideration particularly impor- tant in portable equipment. Flash memory increases flexibility with electrical chip erasure and in-system update capability of operating systems and applica- tion code, With updatable BIOS, system manufactur- ers can easily accommodate last-minute changes as, revisions are made. In diskless workstations and terminals, network trat- fic reduces to a minimum and systoms are instant. ‘on, Reliability exceeds that of electromechanical media. Often in these environments, power intorrup- tions force extended re-boot periods for all net- ‘worked terminals. This mishap is no longer an issue if boot code, operating systems, communication pro- tocols and primary applications are flash-resident in each terminal For embedded systems that rely on dynamic RAM/ disk for main system memory or nonvolatile backup storage, the 28F512 flash memory offers a solid state alternative in a minimal form factor. The 28F512 provides higher pertormance, lower power nsumption, instant-on capability, and allows an sxecute in place” memory hierarchy for code and data table reading. Additionally, the flash memory is more rugged and reliable in harsh environments where extreme temperatures and shock can cause disk-based systems to fail ‘The nead for code updates pervades all phases of a system's life — from prototyping to system manufac: ture to after-sale service. The electrical chip-erasure and reprogramming ability of the 28F512 allows in- 26F512 circuit alterabilty: this eliminates unnecessary han- dling and less-reliable socketed connections, while adding greater test, manufacture, and update flex bility Material and labor costs associated with code changes increases at higher levels of system inte- gration — the most costly being code updates after sale. Code “bugs”, or the desire to augment system functionality, prompt after-sale code updates. Field revisions to EPROM-based code requires the re- ‘moval of EPROM components or entire boards. With the 28F512, code updates are implemented locally via an edge-connector, or remotely over a commun: cation link. For systems currently using a high-density static RAM/battery configuration for data accumulation, flash mamory's inherent nonvolaillty eliminates tho need for battery backup. The concern for battery failure no longer exists, an important consideration for portable equipment and medical instruments, both requiring continuous performance. In addition, flash memory offers a considerable cost advantage over static RAM. Flash memory’s electrical chip erasure, byte pro- ‘grammability and complete nonvolatilty ft well with dala accumulation and recording needs. Electrical chip-orasure gives the designer a "blank slate” in which to fog or record data. Data can be periodically off-loaded for analysis and the flash memory erased producing a new "blank slate’ ‘A high degree of on-chip feature integration simpli- fies memory-to-processor interfacing. Figure 3 de- picts two 28F512s tied to the B0C186 system bus. ‘The 28F512's architecture minimizes interface cir- cuitry needed for complete in-circuit updates of memory contents. With costetfective in-system reprogramming, ex tended cycling capability, and true nonvolatilty, the 28F512 offers advantages to the alternati EPROMs, EEPROMs, battery backed static RAM. ‘or disk. EPROM-compatible read specifications, straight-forward interfacing, and in-circuit alterabilty offers designers unlimited flexibility to meet the high standards of today's designs. 6-6320F512 soctas syste us 004-0015, 09-00, new 004-00, aarsia rersi2 290204-5 Figure 3. 28F512 in a 80C186 System PRINCIPLES OF OPERATION Flash-memory augments EPROM functionality with in-circuit electrical erasure and reprogramming. The 28F512 introduces a command register to manage this new functionality. The command register allows tor: 100% TTL-level control inputs: fixed power sup- plies during erasure and programming: and maxi- rum EPROM compatibility In the absence of high voltage on the Vpp pin, the 28F512 is a read-only memory. Manipulation of the external memory-control pins. yields. the standard EPROM read, standby, output disable, and Intel ‘gent identifier operations, The same EPROM read, standby, and output disable operations are available when high voltage is ap- plied to the Vpp pin. In addition, high voltage on Vp enables erasure and programming of the device. All functions associated with altering memory con- tents—Inteliigent Identifier, erase, erase verity, pr ‘gram, and program verity—are accessed via the ‘command register. Commands are written to the register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for programming or erase operations. With the appropriate command written to the register, 6-64 standard microprocessor read timings output array data, access the Inteligent Identifier codes, or out- put data for erase and program verification Integrated Stop Timer Successive command write cycles define the dure- tion of program and erase operations; specifically, the program or erase time durations are normally terminated by associated program or erase verity ‘commands. An integrated stop timer provides simpli fied timing control over these operations; thus elimi- nating the need for maximum program/erase timing specifications. Programming and erase pulse durations are minimums only. When the stop timer terminates a program or erase operation, the device enters an inactive state and remains inactive until receving the appropriate very oF reset command, Write Protection The command register is only active when Vpp is at high voltage. Depending upon the appiication, the system designor may choose to make the Vpp pow- cr supply switchable—available only when memory updates are desired. When Vp = Vppi, the con- tents of the register default to the read command, making the 28F512 a read-only memory. In this mode, the memory contents cannot be altered.intel. 20F512 Table 2. 28F512 Bus Operations = Pine | vpptt) | Ao] Ap | CE* | OE* | we*| Dao-Da, Operation Road Vee. | Ao| Ao | Yu) Vi | Via | Data Out Output Disable Vee. | x |x | va_| Vin | Vin | Ta-State READONLY | Standby Ven |x| x | vm | x |x | Tristate Intelligent identifier (Mf)(2) Ver. | Vi | Vio | Vi_| Vu_| Var | Data ~ 89H | intelligent Identifier (Device)(2) | Vep._| Vin | Vio) | Vi | Vic_| Win _| Data = 88H Read Very | Ao| Ao | Vi | Yu | Vin | Data Outié) READ/WaiTe |OuPUtDisabie Vern | xX | x | Ve | Vin | Vii | TeState ‘Standby'S) Vepu | x x View x X_| Tri-State Write Veen | Ao] Ao | Vi | Vw | Vu | Dataine | NoTEs: 1. Roter to DC Characteristics. Whan Vep = Vapi memory contents can be read but not written or erased. 2 Manufacturer and device codes may also be accessed via a command registar wite sequence. ter to Table 3. Al other addresses low. 3. Vip is the Intoligent idantfor high voltage. Rafer to DC Chara acteristics, 44 Read operations with Vpp = Vppy may access array data or the intatigent Identifier codes. 5. With Vpp_at high voltago, the standby current equals loc 6 Refer fo Table 3 for valid Data-In during a write operation, 7. X can bo Vi, Or Vin 'e Or, the system designer may choose to "*hardwir Vee, making the high voltage supply constantly available. In this case, all Command Register func- tions are inhibited whenever Vcc is below the write lockout voltage Vi.xo. (See Power Up/Down Protec- tion). The 28F512 is designed to accommodate ei- ther design practice, and to encourage optimization of the processor-memory interlace, The two-step program/erase write sequence to the Command Rogister provides additional software write protection BUS OPERATIONS Read ‘The 28F512 has two control functions, both of which must be logically active, to obtain data at the out- Puts. Chip-Enable (CE) is the power control and should be used for device selection. Output-Enable (OE#) is the output control and should be used to gate data from the output pins, independent of device selection. Refer to AC read timing waveforms, When Vp is high (Vp), the read operation can be used to access array data, to output the Intelligent Identifier codes, and to access data for program/ erase verification. When Vpp is low (Vpp), the read ‘operation can only access the array data, 5p (standby), Output Disable With Output-Enable at a logic-high level (Vin), output from the device is disabled, Output pins are placed in a high-impedanco state. Standby With Chip-Enable at a logic-high level, the standby operation disables most of the 28F512's circuitry and substantially reduces device power consump- tion. The outputs are placed in a high-impedance slate, independent of the OutputEnable signal Ut the 28F512 is deselected during erasure, pro- ‘gramming, program/erase voriication, the device draws active current until the operation is terminated, Intelligent Identifier Operation ‘Tho Intelligent Identifier operation outputs the manu- facturer code (89H) and device code (88H). Pro- ‘gramming equipment automatically matches the de- vice with its proper erase and programming algo: rithms. 6-6526F512 With Chip-Enable and Ouiput-Enable at a logic low level, raising A9 to high voltage Vip (see DC Charac: teristics) activates the operation. Data read from lo- cations 00004 and 0001H represent the manuf turer's code and the device code, respectively ‘The manufacturer. and device-codes can also be ‘ead via the command register, for instances where the 28512 is erased and reprogrammed in the tar- got system. Following a write of 90H to the com: mand ragister, a read from address location O000H outputs the manufacturer code (89H). A read from address 0001H outputs the device code (88H). write Device erasure and programming are accomplished via the command register, when high voltage is ap- plied to the Vpp pin, The contents of the register serve as input to the internal state-machine. The state-machino outputs dictate the function of the: device. intel. The command register is written by bringing Write- Enable to a logic-low level (Vj,), while Chip-Enable is low. Addresses are latched on the falling edge of Write-Enable, while data is latched on the rising edge of the Write-Enable pulse. Standard microproc- ‘essor write timings are used. Refer to AC Write Characteristics and the Erase/ Programming Wavelorms for specific timing parameters, COMMAND DEFINITIONS When fow voltage is applied to the Vpp pin, the con- tents of the command register default to OOH, en. abling read-only operations. Placing high voltage on the Vpp pin enables read/ write operations. Device operations are selected by writing specific data patterns into the command reg- The command register itselt does not occupy an ad- ister. Table 3 defines these 28F512 ragistor dressable memory location. Tho register 's a laich commands. eva) First Bus Cycle ‘Second Bus Cycle ‘Command Cyctes| "s a _[Ree's loperation()| Address(@)[Data‘®)|Operation(*)| Address(®)[Data() ‘Read Memory 1 x__| 008 [Read Inteligent Identier Codel x__| 90H | Read o | [Set-up Erase/Eraset®) __x_| 20m | write x__| 20H lErase Very) EA | AOH | Read x__| evo [Set-up Program/Progran®) | | 40H | Write PA | PD [Program Verity®) con | Read PVD Reset?) Tox | ren] write x__| FeH Nores: 1" Bus operations are doined in Tabla 2 2.1A. Ident addres: OH Tor manutacturer code, O1H for device code Ex - ‘Adatess of memory location Yo be read dng erase very PA__Adaross of memory locaton to be programmed. ‘Addresses aro latched on the faling edgo of the Wrte-Enable pulse, 3.10 = Data read trom location IA during device identification (tr EVO = Data from location EA during erase vont PD = Data to be programmed at location PA. Data i latched on tho rising odgo of Writ-Enabl YD ~ Data ead from location PA during program venty. PA is latched on Following the Read Intaligent 1D command, two read operations accoss mantacturer Figure 5 lusirates the Quick Erase algorithm Figure 4 illustrates the Quck Pulse Programming algorithm. 6-66 ‘89H, Dovico = 86H), Programs command nd devico codes. The socond bu cycle must be followed by the desired command register wet,intel. Read Command While Vp is high, for erasure and programming, memory contents can be accessed via the road ‘command. The read operation is initiated by writing 00H ‘into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register con- tents are altered, The default contents of the register upon Vpp pow: €F-up is OOH, This defautt value ensures that no spu- ‘ious alteration of memory contents occurs during tho Vpp power transition. Where the Vpp supply is hard-wired to the 28F512, the dovice powers-up and ‘emains enabled for reads until the command-ogis- ter contents are changed. Refer to the AC Read ‘Characteristics and Waveforms for speciic timing Parameters. Intelligent Identifler Command Flash-memories are intended for use in applications where tho local CPU alters memory contents. As such, manufacturer- and devico-codes must be ac- cessible while the device resides in the target sys- tem. PROM programmers typically access signature codes by raising A9 to a high voltage. However, mul- tiplexing high voltage onto address lines is not a de- sired system-design practice. ‘The 28F512 contains an Inteltigent Identifier opera- tion to supplement traditional PROM-programming methodology. The operation is initiated by writing 90H into the command register. Following the com- mand write, a read cycle from address 0000H re- trieves the manufacturer code of 89H. A read cycle from address 0001H returns the device code of BH. To terminate the operation, it is necessary to write another valid command into the register. Set-up Erase/Er: ‘Commands Setup Erase is a command-only operation that stages the device for electrical erasure of al bytes in the array. The set-up erase operation is performed by writing 20H to the command register. To commence chip-erasure, the erase command (20H) must again be written to the register. Tho erase operation begins with the rising edge of the Write-Enabie pulse and terminates with the rising ‘0dge of the next Write-Enable pulse (i.e, Erase-Vor' ty Command) ‘This two-step sequence of set-up followed by execu- tion ensures that memory contents are not acciden- tally erased. Also, chip-erasure can only occur when high voltage is applied to the Vep pin. In the absence 20F512 of this high voltage, memory contents are protected, against erasure, Refer to AC Erase Characteristics and Waveforms for specific timing paramoters. Erase-Verlty Command The erase command erases all bytes of the array in parallel. After each erase operation, all bytes must be verified. The erase verity operation is initiated by writing AOH into the command register. The address. for the byte to be verified must be supplied as it is, latched on the falling edge of the Write-Enable pulse. The register write terminates the erase opera- tion with the rising edge of its Write-Enable pulse. The 28F512 applies an internally-generated margin voltage to the addressed byte. Reading FFH from the addressed byte indicates that all bits in the byte are erased, Tho orase-verity command must be written to the command register prior to each byte verification to latch its address. The process continues for each byte in the array until a byte does not return FFH data, or the last address is accessed. In the case where the data read is not FFH, another frase operation is performed. (Refer to Setup Erase/Erase). Veriication then resumes from the address of the last-verified byte. Once all bytes in the array have been verified, the erase step is com- plete. The device can be programmed. At this point, the verity operation is terminated by writing a valid command (e.g. Program Set-up) to the command segister. Figure 5, the Quick-Erase algorithm, illus- trates how commands and bus operations are com- bined to perform electrical erasure of the 28F512. Refer to AC Erase Characteristics and Wavetorms, for specific timing parameters. Set-up Program/Program Commands Setup program is @ command-only operation that stages the device for bye programming. Writing 4OH into. the command register performs the set-up operation. ‘Once the program set-up operation is performed, the next Write-Enable pulse causes a transition to ‘an active programming operation. Addresses are in- ternally latched on the faling edge of the Write-En- able pulse. Data is internally latched on the rising edge of the Write-Enable pulse. The rising edge of Write-Enable also begins the programming opera- tion. The programming operation terminates with the noxt rising edge of Write-Enable, used to write the program-verity command. Refer to AC Programming Characteristics and Wavetorms for specific timing parameters. 66728F512 Program-Verity Command ‘The 28F512 is programmed on a byte-by-byte basis. Byte programming may occur sequentially or at ran dom. Following each programming operation, the byte just programmed must be verified, ‘The program-verify operation is initiated by writing COH into the command register. The register write terminates the programming operation with the ris- ing edge of its Write-Enable pulse. The program-ver- ify operation stages the device for verification of the byte last programmed. No new address information is latched. ‘The 28F512 applies an intornally-generated margin voltage to the byte. A microprocessor read cycle ‘outputs the data. A successful comparison betwaen the programmed byte and true data moans that the byte is successfully programmed. Programming then proceeds to the next desired byte location. Figure 4, the 28F512 Quick-Pulse Programming algorithm, i lustrates how commands are combined with bus op- ‘rations to perform byte programming. Refer to AC Programming Characteristics and Waveforms for specitc timing parameters. Reset Command ‘A reset command is provided as a means to safely ‘abort the erase- or program-command sequences. Following either set-up command (erase or program) with two consecutive writes of FFH will sately abort the operation. Memory contents will not be altered. A valid command must then be written to place the device in the desired state. EXTENDED ERASE/PROGRAM CYCLING EEPROM cycling failures have always concemed users, The high electrical field required by thin oxide EEPROMs for tunneling can literally tear apart tho ‘oxide at defect regions. To combat this, some sup- pliers have implemented redundancy schemes, re- ducing cycling failures to insignificant levels. Howev- cr, redundancy requires that cell size be doublod— an expensive solution Intel has designed extended cycling capability into its ETOX Il flash memory technology. Resulting im- Proverents in cycling reliability come without in- creasing memory call size or complexity. First, an advanced tunnel oxide increases the charge carry- ing ability ten-fold. Second, the oxide area per coll subjected to the tunneling electric field is one-tenth that of common EEPROM, minimizing the probabil ty of oxide defects in the ragion. Finally, the peak electric field during erasure is approximately 2 MV/ em tower than EEPROM, The lower electric field 6-68 intel. ety rece nesters ad ptabiy of failure—increasing time to wearout by a factor of ‘100,000,000. The 28F512 is capable of 100,000 program/erase cycles. The device is programmed and erased using Intel's Quick-Pulse Programming and Quick-Erase algorithms. Intel's algorithmic approach uses a se- fies of operations (pulses), along with byte veriticg: tion, fo completely and reliably erase and program the device, For further information, see Reliability Report RA-60 (ETOX-II Reliability Data Summary). QUICK-PULSE PROGRAMMING ALGORITHM The Quick-Pulse Programming algorithm uses pro- gramming operations of 10 js duration, Each opera- tion is followed by a byte verification to determine when the addressed byte has been successfully pro- grammed. The algorithm allows for up to 25 pro- gramming operations per byte, although most bytes verity on the first or second operation. The entire sequence of programming and byte verification is performed with Vep at high voltage. Figure 4 illus- trates the Quick-Pulse Programming algorithm. QUICK-ERASE ALGORITHM Intel's Quick-Erase algorithm yields fast and reliable electrical erasure of memory contents. The algo- rithm employs a closed-loop flow, similar to the Quick-Pulse Programming algorithm, to simulta- ‘neously remove charge from all bits in the array. Erasure begins with a read of memory contents. The 28512 is erased when shipped from the factory. Reading FFH data from tho device would immed ately be followed by device programming. For devices being erased and reprogrammed, unk form and reliable erasure is ensured by first pro- {gramming all bits in the device to their charged state (Oe 00H). This is accomplished, using the Quick-Puiso Programming algorithm, in approx mately one second, Erase execution then continues with an initial erase operation. Erase verification (data = FFH) begins at address 0000H and continues through the array to the last address, or until data other than FFH is en- ‘countered. With each erase operation, an increasing ‘umber of bytes verify to the erased state. Erase efficiency may be improved by storing the address of the last byte verified in a register. Following the next ‘erase operation, verification starts at that stored at dress location. Erasure typically occurs in one sec- ‘ond. Figure 6 illustrates the Quick-Erase algorithm.intel ° 28F512 | ‘operation | COmand Comments ersgrommig ) = | vow sStancby Wai for ep Ramp Ven? | | iniaize Puse-Count Frgrort Gd Program + 109 Wie Progam rite | Program | Vets Adross/Data ea wate | Program | vais Adcross/ Oat | + Ties 0 Tope Standby Duration of Program + Operation (twine) Wika Prosar wirte | Program| Data = CoH: Stops Program = Verity Operation(3) t Tem 04 boa Stansby Sot. + Rent Ole ood Read Byte 1 Verty Programming standby Data Ourputto Data wite | read | Data = 00H, Resatsthe | Les | Register for Road Operations wen wel Stancoy Wait for Vep Ramp to Vorutt | 2006-6 eon 3. Reter to iples of operatic 100 DC Characteristics fr valve of Vrpy and Ve otto princes of operation Se en ae Ee er «4. CAUTION. The algorithm MUST BE FOLLOWED ‘ming, A final read/compare may be performed (option- to ensure proper and rellable operation of the de- al) after the register is written with the Rlead command. vice. Figure 4. 28F512 Quick-Pulee Programming Algorithm | 6-6926F512 NoTES: et tee 1. S96 DG Charactorstcs for value of Vp and Ver. 2. Erase Verity 1s porformed only after chip-erasure. A {inal read/compare may be performed (optional) afi ‘the registar is wntten withthe read command. ‘Standby Write write Standby Write ‘Standby Read Standby weite ‘Standby setup Erasol®) Verity Road Entra memory must = OOH. bofore erasure Use Quick Pulse Programming Algorithm (Figure 4) Wait for Vep Ramp 10 Vepy(1) Intatize Addresses and Pulge-Count Data = 20H Data = 20H Duration of Erase Operation ‘aswnia) ‘Addr = Byte 1 Verity: Data = ADH; Stops Erase Operation’) tw. Rad Byte to Verity Erasure ‘Compare Output to FFH Increment Pulse-Count Data = 00H, Resets the FRogieter for Read Operations Wait for Vep Ramp to Vpeu(t) 38. Rotor to principles of operation. 4. CAUTION: The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the de- vies. 6-70 Figure 5. 28F512 Quick-Erase AlgorithmDESIGN CONSIDERATIONS Two-Line Output Control Flash-memories are often used in larger memory ar rays. Intel provides two road-control inputs to ac- ‘commodate multiple memory connections. Two-ing control provides for: a the lowest possible memory power dissipation and, bb. complete assurance that output bus contention will not occur. To efficiently use these two control inputs, an ad- dress-decoder output should drive chip-enable, while the system's read signal controls all flash- memories and other paraitel memories. This assures that only enabled memory devices have active out: Puts, while deselected devices maintain the low power standby condition. Power Supply Decoupling Flash-memory power-switching characteristics. re- ‘quire careful device decoupling. System designers. are interested in three supply current (icc) Issues— standby, active, and transient current peaks pro- duced by falling and rising adges of chip-onablo. Tho capacitive and inductive loads on the device outputs determine the magnitudes of these peaks. Tworline control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 pF ceramic capacitor connected betwaen Vcc and Vsg, and between Vpp and Vss. Place the high-frequency, low-inherentinductance capacitors as close as possible to the devices. Also, for every eight devices, a 4.7 uF electrolytic capaci- tor should be placed at the array's power supply connection, betwoon Voc and Ves. The bulk capaci tor will overcome voltage slumps caused by printed: circuitboard trace inductance, and will supply charge to the smaller capacitors as needed. pp Trace on Printed Circuit Boards Programming flash-memories, while they reside in the target system, requires that the printed circuit board designer pay attention fo the Vpp power sup- ply trace. The Vpp pin supplies the memory cell cur rent for programming. Use similar trace widths and layout considerations given the Vic power bus. Ad- equate Vpp supply traces and decoupling will de- ‘erase Vp voltage spikes and overshoots. 29F512 Power Up/Down Protection ‘The 28F512 is designed to offer protection against accidental erasure or programming during power sitions. Upon power-up, the 28F512 is indifferent ‘as to which power supply, Vp or Vcc, powers up: first. Power supply sequencing is not required. Inter nal circuitry in the 28F512 onsures that the com- mand register is reset to the read mode on power up. A system designer must guard against active writes for Voc voltages above ViKo when Vpp is active Since both WE# and CE # must be low for a com: mand write, driving either to Vjyx will inhibit writes ‘Tha control register architecture provides an added evel of protection since alteration of memory con: tents only occurs after successful completion of the ‘two-step command sequences. 28F512 Power issipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory nonvolatilty in- ‘creases the usable battery life of your system be: cause tho 28F512 does not consume any power to retain code or data when the system is off, Table 4 illustrates the power dissipated when updating the 28F512. Table 4. 28F512 Typical Update Power Dissipation(®) Power Dissipation Operation | Notes |" (watt-Seconds) ‘Aray Program/ 1 0.085, Program Verty _ | ‘Array Erase? 0.092 Erase Vonity ‘One Complete cycle | 3 0.262 ‘ypical Program/Program Verity Power (Vp < # Bytes x Typeal # Prog Pulses (none «lope Typical + twuct ops Type) = Woo. # Bytes Typeal # Prog Pulses (yawns Ioez Tybical twa, * toca Typical, 2 Formula to calcuate typcal Eraso/Erase Voity Power = [Ver(eea Typical * terase TyBcal + leps Typical» =" Bytea)] + (Vecticcs Typical * "erase TYOr cal t Ios TyBeal ~ twice" * Bytes) Sr One Gompiote Gyele = Aray Proprogram + Amey Erase ~ Program 1 “Typials ra not glarantoad, but based on a tinted ‘numbar of samples from production los 67120F512 intel. ABSOLUTE MAXIMUM RATINGS* Yep Supply Voltage with Respect to Ground Operating Temperature During Erase/Program.....—2.0V to + 14.0V02.9) ‘During Read ©Ct0 +70 Voc Supply Voltage with During Erase/Program oto +70) VERY Te Bev eer Oe Operating Temperature Output Short Circuit Gurrent.............100 mal) ‘During Read 40°C to +85°CI2) During Erase/Program ......-40°C10 +85'C® — [noriCE: This a a production data shoot. The spect Temperature Under Bias 10°Cto + 80°C) | catons are suboct to change without notice, Temperature Under Bias 50°C to +95°C® “WARNING: Strssing the device beyond the “Absohita ore - xc Maximum Ratings” may cause permanent damage. Storage Temp 65°Cto + 125°C um atngs” may cause permanent damage, Voltage on Any Pin with “Operating Conditions” is not recommended and ex: Respect to Ground 2010 + 7.0V\2 tended exposure bayond the “Operating Conditions’ Voltage on Pin Ag with may atfoct device reliably Respect to Ground —2.0V to + 13.5V(2, 3) noes: 1. Operating temperature is for commercial product defined by this specification. 2. Operating tomperatue i for extended temperature product defined by this specification. 3, Minimum OC input voltage ‘8 -0.5V. Dunng transitions, inputs may undershoot to ~2.0V for periods less than 20 ns. Maximum DC voltage on output pins is Vc + 0.5V, which may overshoot to Voc. + 2.0V for periods less than 20 ns. 4, Maximum DG voltage on Ay oF Vep may overshoot to + 14.0V for poriods loss than 20 ns. 5. Output shorted for no more than me second. No more than one autput shorted at atime. OPERATING CONDITIONS ‘symbol Parameter Lets yet Comments | win | max Ta Operating Temperature | 0 | 70 | °C | ForRead-Only and | Read/Write Operations = for Commercial Products Ts Operating Temperature | -40 | +85 | °C | For Read-Only and Rlead/Write Operations for Extended Temperature Products Veo Voc Supply Voltage aso | 550 [ Vv DC CHARACTERISTICS—TTL/NMOS COMPATIBLE—Commercial Products Limits: symbol Parameter Notes Unit} Test Conditions ‘Min | Typ(4) | Max ta Input Leakage Current 1 $1.0 | wA | Vec = Voc Max Vin = VooorVsg ito | Output Leakage Curent | £100 | HA | Voo = Voc Max Your = Veco" Vss Tees | Yoo Standby Current 7 03 | 40 | mA | Voc = VocMax Ce = Vin ‘ect | Voc Active Read Current | 1 10 | 90 | mA | Voo = Voc Max, CE® = Vi, = 6MHz,lour = OmA [iece | Voc Programming 12 40 | 10 | mA | Programming in Progress Current z : toca |VocEtase Curent | 1.2 50 | 15 | mA | Erasure n Progress loca | Voc Program Verity 12 50 | 15 | mA | Vpp— Vpn ‘Current | Program Verify in Progress 672 |20F512 DC CHARACTERISTICS—TTL/NMOS COMPATIBLE—Commercial Products (Continued) | Symbol Parameter Unit} Test Conditions Jlccs | Voc Erase Vanity Currant 42 50 | 15 | mA| Vep~ Vern | Erase Verity in Progress [pes | Vep Leakage Current 1 [e100 [ua | Vee = Voc Flop: | Vep Read Current, Standby | 90 | 200 | wA | Vpp > Voc } Current, or Current | [#100 Ver § Veo Jere | Vep Programming Curent | 1,2 80 | 30 | mA| Vpp= Veen Programming in Progress ‘eps | Vor Erase Current 12 40 | 30 | mA|Vpp = Veru Erasure in Progress Tppa | Ver Program Verity Curent | 1,2 20 | 50 | mA| Vpp= Very Program Verity in Progress toes | Vep Erase Verify Current 12 20 | 50 | mA| Vpp = Veen Erase Vert in Progress Input Low Voltage =05 os |v Input High Voltage 20 Voc + 05 Output Low Voltage 045 |v [ig 58ma Veo = Voc Min Vou: | Output High Vortago 24 V [lon = =2.5ma Veo = Voc Min Vio__| Ae intetigent identifier Voltage 11.50 va00 |v io ___| Ap inteligent identiier Gurent | 1.2 0 | 200 | ua [Ae = Vio Vee. | Vep during Read-Only 0.00 65 | V | NOTE:Erese/Program are Operations lnnibited when Vep ~ Veet Vern | Vep during Read/Write 11.40 1260 | Vv Operations Vixo | Voc Erase/Wrte Lock Voltage 25 Vv DC CHARACTERISTICS—CMOS COMPATIBLE—Commercial Products Limits | Symbol Parameter Notes unit] TestConditions | in | Tyo | Max | hi Input Leakage Current 1 #10 | wa | Voc = Voc Max | Viv = VooorVss Lo | Output Leakage Current 1 +100] A | Voc = Voc Max | Vout = Voc or Vss ‘cos | Voc Standby Current 1 50 | 100 | HA | Voo = VooMax GE# = Voc 40.20 loc: | Voo Active Read Current 1 10 | 30 | mA | Voc = VocMax,CE# = Vi 6 MHz, lour = mA 67328F512 intel. DC CHARACTERISTICS—CMOS COMPATIBLE—Commercial Products (Continued) i mite symbol| Parameter Limite —__| unit | Test Contons Tyett) | Max | - tre] mex |} ‘cae | Voc Prograrming 10 | 10 | mA | Progamming in Progress Hees Vec Erase Current 12 5.0 15 mA | Erasure in Progress ‘Vc Program Verity 2 5.0 15 mA | Vep = VepH Citra Program Very Progress \ 2 50 15 mA | Ver = VepH Erase Verity in Progress se | VonLeakage Gurent | 1 Fi00_| wa [vee = voo toot | VepReaa Curent iD | 4 eo | 200 | wh | Yer > Voc | Guront or Standby 100 Vor «Woe ire | Vow Programming ve ao | 30 | ma | Von = Vern Caren Programing in Progress Tieee | Ven Erase Gurent | 4,2 40 | 30 | ma | Vee = Voow Eracirein Progress twee | VenProwramverty | 12 20 | 50 | ma] Vee = Vopw | Curent Program Veriyin Progress Fiees | Vow Erase Very Curent | 1,2 20 [80 | ma | Ver = Von Ve. [ Input Low Votage =05 oe |v Ve | Input igh Votage O7 Vos Vos +08 Yor | Output Low Votage ows | V [ig = Sama oo = Veo tn Vou | Output igh Vtage 085 Vo y [lon <25mA, eo = Woo Min Vows Woo 04 Tox = —100 A, eo = Veo in Vio ‘Ag Intelligent Identifier 11.50 13.00 V | Ae vonage To | Astnigentideninor | 1.2 vo [200 [HA |e Coren Voor | Vpp ing Read Ony 65 |v | NOTE Erase/Pooram ‘Operations: 9 Inhibited when it Ver = Vppt Veo | pe ding Rad Write a0 200 |v Operatons Vino | Voc Eraso/wrte Lock 28 v [lage 6-74 Iintel ° 20F512 ce GHARACTERISTICS—TTL/NMOS COMPATIBLE—Extended Temperature roducts | Limits: | symbol Parameter Notes Unit] Test Conditions Min |Typ()) Max [ir [Input Leakage Current 1 £10 | wA|Voc = Voc Max | ;—| |__| _|Win= Vocervss__| iio [Output Leakage Current 1 | #100 | ua |Voo = Voc Max |__| {|__| __Wour=Vecor¥ss_| Taos \Weo Standby Curent +] fos) 10 |ma|voo = Voc Max | ICE# = Vin icc: [Voc Active Read Current 1 [10] 30 [malVoc = Voc Mar. CE = Vi f= 6 MHz, lout = 0 mA Teco |Voo Programming Guren’ | 12] | 10 | 90 | ma Programming in Progress icca__|Voc Erase Current 12 | 50 30 | mA Erasure in Progress. Thoca Curent | 1.2 50 30 |mA|Vpp = VepH |e Program Varityin Progress Nicos [Vcc Erase Venty Curr 1.2 ma |Vpp = Ver | | | |Erase Verify in Progress [lees [Ver Leakage Current 1 £100 | uA |Vop 5 Veo lipo: [Ver Read Current, Standby 1 90 200 | #A |Vpp > Voc Current, or 1 Current I ee ee lppa [Vee Programming Current | 1,2 80 | 30 |mAlVpp = Vppn Programming in Progress lips [Ver Erase Current 1.2 | 40 | 90 |mA|Vpp = Veen Erasure in Prograss lope [Vpp Program Verify Current | 1,2 | 20 5.0 | mA]|Vpp = Vee | Program Vent in Progress pes [Ver Erase Verity Curent | 1,2 20 | 50 |mA|Vep = Vppu Erase Vert in Progress Vi [Input Low Voltage “08 oa fv Vin input High Voltage 20 Veo + 08) Vv Vo. [Output Low Voltage 045 | V fig = 58ma Nos = Voc Min Vou: |Output High Voltage 24 V |low = —2.5mA oc = Voc Min Vio __| As Inteligent identiier Voltage 14.50) 1300 | v “io _|As nteligent dentiier Voltage] __| 11-60) Lo | ig [As intoligont dentifer Curent | 1,2 90 | 500 | wAlAa = Vio Veet |Vep during Read-Only 0.00 65 | V |NOTE:Erase/Program are | Operations Infibited when Vep = Vert (Veen |Vpp during Read/Wete 11.40] 1260 |v | [Operations | VVixo [Voc Erase/Write Lock Votiage 25 v | 67526F512 intel. DC CHARACTERISTICS—CMOS COMPATIBLE—Extended Temperature Products { mite Symbol Parameter Notes unit] Test Conditions | Min | Typ) | Max [tr [lmputteakage Current |i £10 | uA | Voc = Voc Max | Viv = Voc er Vss to | Output Leakage Current | + +100 | HA | Voc = Voc Max Your = VocorVss Icos | Voc Standby Curent 1 50 | 100 | #A| Voc = Voc Max CE# = Voc #0.2v tcc: | Voc Active Read Curent | 1 10 | 80 | mA | Voc = VocMax,CE* = Vi. 6 MHz, loyr = Oma Icce | Voc Programming Curent | 1,2 10 | 10 _ | ma | Programming in Progress cca | Voc Erase Current 12 50 | 15 | mA | Erasurein Progress 'oce _| Voc Program Very 12 50 | 90 | mA | Vpe = Vern Current Program Vert in Progress tees | Voc Erase Venty Curent | 1,2 50 | 90 | mA] Ven = Veow Erase Verily in Progress lpes _| Vep Leakage Current 1 210.0 | HA | Vee & Yoo tper | Vpp lead Curent, 1D 1 90 | 200 | nA | Ven > Vor Currant, or Stand Currant ” #100 Ver < Voc ‘bee | Ver Programming Gurent | 1,2 a0 | 90 | mA| Ve = Vern ie Programming in Progress tpea | Vor Erase Curent 12 40 [90 | ma | Vor = Vern Erasure in Progross tora | Vpp Program Verity 20 | 50 Vpp = Vex Curent Program Verty in Progress ‘pes | Ver Erase Very Current | 1.2 20 | 50 | mA| Ver = Vern I Eraso Venty in Progress Vu__[ input tow Vonage | =05 oe |v Vi __| input High Voltage 07 Voo Voo +05] V Vo. | Output Low Voltage ows |v | 6-76 |intel . 28F512 DC CHARACTERISTICS—CMOS COMPATIBLE—Extended Temperature Products (Continued) [ Limite symbol Parameter Not Unit | Test Conditions min | Typ] Max Vor | Output High Vortage 085 Voc, y | fou = -25ma, Voc = Voc Mia Vou Voc - 0.4 lon = — 100 nA, Voc = Voc Min | Via__| Asinteligentidontiter Vottage 11.50 1300 |v [As = Vio lio__| Ae nteligent identiir Curent 12 90 | 500 | uA [Ao = Vio Vee | Vee during Read-Only Operations 0.00 65 | Vv | NOTE:Erase/ Program are ntibited when { | ft Vee = Vret Veen | Vep during Read/ Waite Operations: 1440 1eso[ Vv [Vico _ | Voc Erase/ Write Lock Voltage 25 v CAPACITANCE Ta = 25°C.1 ~ 1.0MH2 Limits ] | symbol Parameter unit | Conditions Min | Max | Gn ‘Addross/Contol Capacitance 3 8 pe | Vw=ov | Cour Output Capacitance 3 12 pF | Vour= ov | NoTES: 1 All curents aro in AMS unless otherwise noted. Typical values at Voc currants aro valid forall product versions {packages and speeds), 2. Not 100% tested: characterization data availabe. 3. Sampled, not 100% tested 5.0V, Vep = 120¥. 44 "Typicals” are not guaranteed, but based on a limited number of samples from production its T = +25. Theso 67728F512 ‘AC TESTING INPUT/OUTPUT WAVEFORM weur } ous: TS vers 7 } aunrur 25 > Test Poms sane id out ees ie fe teres eee once t Sea eae Rene a aes ne eau eee ae _Gireniendgconamer | AC TEST CONDITIONS Input Rise and Fal Times (10% t0 90%)... ..10ns Input Pulse Levels... +++. 0.48V and 2.4V Input Timing Reference Level .....0.8V and 20V Output Timing Reference Level ......0.8V and 2.0V AC CHARACTERISTICS—Read-Only Operations Nzereiz120 Versione) notes| Paorereie0 | Pesrers-160 | ume |_tezaest2-120 Symbol_| _haractersue _—_—| win [ max | min | Max tavav/tac_| Read Cycle Time 120 150 ns [‘etovitce [Cripenable Access time | [[va0 [| 150 [ne | tavav/tace | Address Access Time. 120 150, ns tgtov/toe_| Output Enable Access Time 50 55 ns. tevax/tiz _ | Chip Enable to Output in Low Z 2,3 0 0 ns [eHoz, Chip Disable to Output in High Z 2 55 55 ns. | tovox/toxz | Output Enable to Ouiput in Low Z 2a] 0 0 _[ ns ‘ewoz/tor | Output sable to Outputinrigh2 | 2 | | 0 | | 95 | ne tou Output Hold from Address, CE #, or 24 oO o ns Gee Change tWHGL Write Recovery Time before Read 6 6 Ss wores 1. Mode! number profxes: N 2 Sampled, not 100% tested 3, Guaranteed by design, 44 Whichever occurs first. 6-78 PLCC, P = PDIP, T ~ Extended Temperature,28F512 Figure 6. AC Waveforms for Read Operations. 290206-1028F512 intel. AC CHARACTERISTICS—Write/Erase/Program Operations(? 4) Versions notes [206592120 [20512160] Characteristic Min | Max | min | Max tavav/twe _| Write Oycle Time 120 150 ns tav/tas_| Address Set-Up Time ° ° ns [twuax/tan | Adress Hold Time 6 « ns tovwn/tos_ | Data Setup Time 50 50 ns ‘wnox/ton | Data Hold Time 10 10 ns twict __ | Wiite Recovery Time before Read 6 é Hs [tow a us texwi/tcs_| Chip Enable Set-Up Time betore Write 20 20 ns twnen/tcn | Chip Enable Hold Time ° ° ns [twcwn/twe | White Pulse Width 60 0 ns [win /tven | Write Pulse Width High 20 20 ne ‘wwii | Duration of Programming Operation | 9 | 10 10 Hs ‘wnwne | Ouration of Erase Operation 3 | 95 95 ms. ‘vee. ___| VepSetUp Time to Chip Enabietow | 2 | 1.0 10 as notes: 1. Reead timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Char: actarsties foc Read-Only Operations. 2. Guarantood by design 3. The integrated stop timer termina spocticaton 4 Erase/Program cycias on extended temperature products is 1,000 cycles. the programming/erase operations, thereby eliminating the need for @ maximum ERASE AND PROGRAMMING PERFORMANCE Lumits Parameter | Notes N/P28F512-120, 150 ‘TN/TP28F512-12019) Unit min | Typ Max min | Typ Max Chip Erase 13.4 1 10 1 10 ‘Sec Time Chip Program | 1,24 1 6.25 1 625 ‘Sec Time notes: 1. "Typicals are not guaranteed, but based on a fimited number of samples from production los, Data taken at 26°C, 12.0V pp at 0 eyclos. 2. Minimum byte programming time excluding system overhead Is 16 ys (10 ys program + 6 us write recovery), while ‘maximum is 400 us/byte (16 us % 25 loops allowed by algorithm). Max chip programming time is spectied lower than the worst case allowad by the programming algorithm since most bytes program significantly faster than the worst case byte. 5, Excludes OOH Programming Prior to Erasure. 4, Excludes Systom-Level Overhead. 5 Refer to AR-60 "ETOX Il Flash Memory Raliabilty Data Summary” for iypical cycling data and falura rate calculations 6, Extended temperature products 6-80 |intel. 29F512 200208-14 Figure 8. 28F512 Typical Programming Capability2eF512 intel . NoTE: 280204-18 (008 not include Pro-Eraso program, Figure 8, 20F512 Typical Erase Time at 12¥ co cent P(e) note: 2000-17 Does not nchue Pre-Erase program. Figure 10. 28F512 Typical Erase Capability 6-82er-woz0se 28F512 dasowes © | saeeooe Figure 11. AC Waveforms for Programming Operations 6-8320F512 ALTERNATIVE CE#-CONTROLLED WRITES In tel. 20F512-120 20F512-150 Versions as a Symbol_| Characteristic Min Max | Min | Max tavay ‘Write Cycie 120 150 ns _ Time TtavEL ‘Address Set- 0 ° ns. Up Time ‘eux ‘Address Hold 60 ns Time | toven Data Set-Up 50 ns | Time \teiox | Data Hots 10 10 ne | Time tena Waite 6 6 as | Flecovery Time | before Read ‘oHeL Read 2 0 0 As | Recovery Time before Write Y wet Write Enabio| ° ° ne Set-Up Time before Chip Enable ‘enw Write Enable 0 0 ns Hold Time teu Write Pulse 1 70 70 ns Width ‘ene Write Pulse 20 20 ns Width High | typeL Vpp Set-Up 2 10 1.0 | ps Time to Chip | Enable Low l nore: 1. Chip-Enable Controlled Wetes: Write operations are driven by the valid combination of Chip-Enable and Write-Enabio, in 6-84 lems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all eet-up, hold and. ‘Weta-Enable times should be moasured relate to tho Chip-Enable wavotorm. uarantoed by design28F512 oz-vozoee, ay ARES PERK Figure 12. AC Wavetorms for Erase Operations 68528F512 0I ntel . 28F512 Ordering Information P= 32-00 PLASTIC OF | 12000 Na S2-Leag mice 10m TeweRaTURE T= EXTENDED (-409C 10 +85°¢) avant = COMMERCIAL (OE TO 770%) l 200204-19 Valid Combinations: P28F512-120 N28F512-120 ‘TP28F512-120 P2BF512-150 N2BF512-150 ‘TN28F512-120 ADDITIONAL INFORMATION (Order Number ER-20, "ETOX II Flash Momory Technology” 294005 ER.24, “intel Flash Memory” 294008 IR.60, "ETOX Ii Flash Memory Reliability Data Summary" 299002 ‘AP-316, “Using Flash Memory for In-System Reprogrammable 292046 Nonvolatile Storage" ‘AP.325 “Guide to Flash Memory Reprogramming” 292059 REVISION HISTORY Number Description 006 Removed 200 ns speed bin Clarified AC and DC test conditions 007 Corrected AC Waveforms Added Extended Temperature device: Revised Erase Maximum Pulse Count for Figure § trom 3000 to 1000 fa P28F512-120, TN28F512-120 008 Revised symbols; i.e., CE, OE, ete. to CE¥, OE #, at. 687