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8086 Complete Module
8086 Complete Module
Vcc
16 - bit Address/Data Bus
CLK
RESET
A16 - A19 / S3 - S6
READY
4 - bit Address/Status Bus
TEST
BHE / S7
NMI
MN / MX
(MAX INTR 8086 (MAX
MODE) RD MODE)
(QS1)/INTA WR/(LOCK)
Gnd Gnd
SUPPLY:
Supply Voltage: Single +5V DC +/- 10%
Ground: System Ground (Two pins)
CLOCK:
Duty Cycle: 33%
In 8088 CPU:
• Length of internal FIFO queue is 4-bytes.
• AD8 to AD15 changes to A8 to A15 as only 8-bit data bus is there.
• Signal BHE/S7 changes to SSO, which is logically equivalent to signal S0.
The signal is always HIGH when 8088 is operating in maximum mode.
• M/IO becomes IO/M.
• Other pin functions and definitions remain same.
PIN FUNCTION
Vcc +5V +/- 10%
Gnd Ground pin connected to system ground. Two ground pins
Clock input signal with 33% duty cycle. It Determines the speed of
CLK
processor.
It causes the processor to reset itself if the RESET is high atleast for 4
clock periods.
RESET At reset processor sets CS = FFFFh and clear the PSW, IP, DS, ES, SS
and instruction queue (IPQ).
Address/Data multiplexed bus. The address comes first and can be
AD0-AD15
latched externally. Then bus can be made free to carry the data.
Address/Status bus multiplexed bus. The upper 4-bit address comes
first and then come the status signals.
A16-A19 /
• Status S6 always LOW i.e. S6=0 always.
S6 –S3
• Status S5 gives current status of IF flag i.e. S5=IF always.
• Status S4 & S3 gives the information about current segment (register)
being used as shown below. The S4 & S3 bits may also be used as A21
& A20 to address four separate 1MB-memory banks.
Status Signals
Meaning
S4 S3
0 0 Extra Segment
0 1 Stack Segment
1 0 Code or No Segment
1 1 Data Segment
Bus High Enable. A LOW on this pin enables the most significant
BHE/S7 data bus (D8-D15) during a read or write operation. After BHE
information, comes the status S7 which always remains LOW.
Read signal. A LOW on this signal instructs the selected I/O or
RD
memory device to give its data content onto the data bus.
Slow peripheral or memory devices use it. A LOW on this input tells
the processor that the device is not yet ready for data transfer and
READY thus causing processor to enter into wait states. A HIGH on this
input continues normal operation of 8086.
Interrupt Request. A level triggered interrupt. External hardware
INTR can used this pin to interrupt normal operation of processor. This
signal is recognized if and only if flag IF=1 in flag register.
Non Maskable Interrupt. A positive edge triggered interrupt.
NMI Always served by the 8086 irrespective of status of IF flag. Thus
always used for critical conditions.
Test input is sampled by WAIT instruction of 8086. If TEST=1 the
WAIT instruction waits for this signal to become 0. As soon as it
TEST becomes 0 processor works further. If it is already 0 WAIT
instruction works as NOP.
Minimum/Maximum Mode. A LOW on this signal configures the
MN/MX 8086 in maximum mode and a HIGH configures it to minimum mode
of operation.
AD0 - AD15
Vcc
16 - bit Address/Data Bus
CLK
RESET
A16 - A19 / S3 - S6
READY
4 - bit Address/Status Bus
TEST
BHE / S7
NMI
MN / MX
(MAX INTR 8086 (MAX
MODE) RD MODE)
(QS1)/INTA WR/(LOCK)
Gnd Gnd
SUPPLY:
Supply Voltage: Single +5V DC +/- 10%
Ground: System Ground (Two pins)
CLOCK:
Duty Cycle: 33%
In 8088 CPU:
• Length of internal FIFO queue is 4-bytes.
• AD8 to AD15 changes to A8 to A15 as only 8-bit data bus is there.
• Signal BHE/S7 changes to SSO, which is logically equivalent to signal S0.
The signal is always HIGH when 8088 is operating in maximum mode.
• M/IO becomes IO/M.
• Other pin functions and definitions remain same.
VCC 1G
20 1
1A1 1Y1
2 18
1A2 1Y2
4 16
1A3 1Y3
6 14
Function Table
1A4 1Y4 1A1 1Y1
8 12
1G 2G Operation
1A2 1Y2
2A1 2Y1 All O/Ps Enabled, i.e. I/Ps 1A i
11 9 1A3 1Y3 0 0 appears at O/Ps 1Yi & I/Ps 2A i
2A2 2Y2 appears at O/Ps 2Yi.
13 7 1A4 74LS244 1Y4
O/Ps 1Yi Enabled, i.e. I/Ps 1A i
2A1 OCTAL 2Y1 0 1 appears at O/Ps 1Yi & O/Ps 2Yi
2A3 2Y3
15 5 BUFFER in HIGH-Z State.
2A2 2Y2
2A4 2Y4 O/Ps 2Yi Enabled, i.e. I/Ps 2A i
17 3 2A3 2Y3 1 0 appears at O/Ps 2Yi & O/Ps 1Yi
in HIGH-Z State.
2A4 2Y4
10 19 All O/Ps in HIGH-Z State.
1 1 OR
Gnd 2G 1G 2G
I/P Isolated from O/P.
(a) Internal Logic Diagram (b) Functional Diagram (c) Function Table
VCC GND
A1 B1
20 10
A1 B1 A2 B2
2 18
A3 B3
A2 B2
3 17 A4 B4
74LS245
A5 Transceiver B5
A3 B3
4 16 A6 B6
A4 B4
5 15 A7 B7
A5 B5
6 14 A8 B8
A6 B6
7 13 DIR G
A7 B7
8 12
A8 B8 (b) Functional Diagram
9 11
Function Table
Direction
Enable Control Operation
G DIR
Data flow
0 0
from B to A.
Data flow
1 19 0 1
from A to B.
DIR G
Direction 1 X Isolation
Enable
Control
(a) Logic Diagram
(c) Function Table
74LS245 TRANCEIVERS
1
A0 A1 A2 A3 B0 B1 B2 B3
SEL (B)
Y0 Y1 Y2 Y3
Function Table
1 SELECT Vcc 16
Select
Operation
SEL (B) 2 A3 STROBE 15
RESET
A16 - A19 / S3 - S6
READY
4 - bit Address/Status Bus
TEST
BHE / S7
NMI
MN / MX
(MAX INTR 8086 (MAX
MODE) RD MODE)
(QS1)/INTA WR/(LOCK)
Gnd Gnd
SUPPLY:
Supply Voltage: Single +5V DC +/- 10%
Ground: System Ground (Two pins)
CLOCK:
Duty Cycle: 33%
In 8088 CPU:
• Length of internal FIFO queue is 4-bytes.
• AD8 to AD15 changes to A8 to A15 as only 8-bit data bus is there.
• Signal BHE/S7 changes to SSO, which is logically equivalent to signal S0.
The signal is always HIGH when 8088 is operating in maximum mode.
• M/IO becomes IO/M.
• Other pin functions and definitions remain same.
AD0 – AD7
Vcc 8 - bit Address/Data Bus
CLK A8 - A15
RESET 8 - bit Address Bus
Gnd Gnd
SUPPLY:
Supply Voltage: Single +5V DC +/- 10%
Ground: System Ground (Two pins)
CLOCK:
Duty Cycle: 33%
Status Signals
Meaning
S4 S3
0 0 Extra Segment
0 1 Stack Segment
1 0 Code or No Segment
1 1 Data Segment
Bus High Enable. A LOW on this pin enables the most significant
BHE/S7 data bus (D8-D15) during a read or write operation. After BHE
information, comes the status S7 which always remains LOW.
Read signal. A LOW on this signal instructs the selected I/O or
RD
memory device to give its data content onto the data bus.
Slow peripheral or memory devices use it. A LOW on this input tells
the processor that the device is not yet ready for data transfer and
READY thus causing processor to enter into wait states. A HIGH on this
input continues normal operation of 8086.
Interrupt Request. A level triggered interrupt. External hardware
INTR can used this pin to interrupt normal operation of processor. This
signal is recognized if and only if flag IF=1 in flag register.
Non Maskable Interrupt. A positive edge triggered interrupt.
NMI Always served by the 8086 irrespective of status of IF flag. Thus
always used for critical conditions.
Test input is sampled by WAIT instruction of 8086. If TEST=1 the
WAIT instruction waits for this signal to become 0. As soon as it
TEST becomes 0 processor works further. If it is already 0 WAIT
instruction works as NOP.
Minimum/Maximum Mode. A LOW on this signal configures the
MN/MX 8086 in maximum mode and a HIGH configures it to minimum mode
of operation.
READY Signal
• READY is sampled at the end of T2. If it is 0
then T3 is delayed by inserting a wait state
Tw.
• READY is sampled again in the middle of Tw.
If it still 0, then another wait state is
inserted. If it is 1, then T3 appears.
• During the wait state signal status are
maintained, so that selected I/O or memory
device can work properly.
• Timing requirements for READY input are
very stringent
• In T2 it must be LOW at the end during 1 to
0 transition of the clock.
• In Tw it must come back to HIGH in the
middle during 0 to 1 transition of the clock.
OR
It should be LOW in the middle of Tw during
0 to 1 transition of the clock.
RESET
A16 - A19 / S3 - S6
READY
4 - bit Address/Status Bus
TEST
BHE / S7
NMI
MN / MX
(MAX INTR 8086 (MAX
MODE) RD MODE)
(QS1)/INTA WR/(LOCK)
Gnd Gnd
SUPPLY:
Supply Voltage: Single +5V DC +/- 10%
Ground: System Ground (Two pins)
CLOCK:
Duty Cycle: 33%
In 8088 CPU:
• Length of internal FIFO queue is 4-bytes.
• AD8 to AD15 changes to A8 to A15 as only 8-bit data bus is there.
• Signal BHE/S7 changes to SSO, which is logically equivalent to signal S0.
The signal is always HIGH when 8088 is operating in maximum mode.
• M/IO becomes IO/M.
• Other pin functions and definitions remain same.
There are total 8-pins which have dual meaning and have different definitions in
minimum and maximum mode of operation. The maximum mode pin names are
indicated within the brackets in the logic diagram.
Status Bits. These bits indicate the function of current bus cycle. These
S2,S1,S0 pins are decoded externally by the 8288 bus controller. The below table
summarizes the function encoded on these bits.
STATUS BITS
MEANING
S2 S1 S0
0 0 0 Interrupt Acknowledgement
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 HALT
1 0 0 Opcode Fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Passive or Inactive
10K
RESET RESET
10
RES
uF
SYSTEM
RESET