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Async Fifo Design

This document describes an asynchronous 8-word first-in first-out (FIFO) buffer with 1-word write and 1-word read capability between two clock domains. The FIFO uses a 8-word register file and gray coding to keep track of the write and read pointers across the different clock domains without using additional synchronization logic.

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jhbandy
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21 views1 page

Async Fifo Design

This document describes an asynchronous 8-word first-in first-out (FIFO) buffer with 1-word write and 1-word read capability between two clock domains. The FIFO uses a 8-word register file and gray coding to keep track of the write and read pointers across the different clock domains without using additional synchronization logic.

Uploaded by

jhbandy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Asynchronous, 8-word, 1wr/1rd FIFO

WR_CLK DOMAIN RD_CLK DOMAIN


8-Word Regfile

wr_data rd_data
WR_DATA RD_DATA

wren rden
WREN

+1 1 wc_wr_ptr rc_rd_ptr 1 +1
WR_ADDR RD_ADDR
0 4 3 3 4 0

wc rc
wc_wr_ptr rc_rd_ptr

wc

empty empty
detect

full full
detect gray gray_wr_ptr gray rc_wr_ptr
code decode
wc rc rc

wc_rd_ptr gray gray_rd_ptr gray


decode code
wc wc rc

Signal Logic:

full <= '1' when (wc_wr_ptr[2:0] = wc_rd_ptr[2:0]) and ((wc_wr_ptr[3] xor wc_rd_ptr[3]) = '1') else '0';

empty <= '1' when (rc_wr_ptr[3:0] = rc_rd_ptr[3:0]) else '0';

overflow <= full and wren; (optional - implement externally)

gated_wren <= (not full) and wren; (optional - implement externally)

async_fifo : afifo-8w

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