Power Aware Testability

1. Introduction

Low power issues are very much concern during this era of technology. As the technology
tends to reduce its size, more and more complexities with power issues come into
existence. Large Integrated circuits require an increasing amount of data to test them which
increases testing time and tester memory. Power reduction is needed during functional
mode and test mode of the design.

As integrated circuit feature size continues to shrink and portable devices grow, power
consumption not only becomes one of the key issues to be considered during functional
operation, but also has to be considered during manufacturing tests [1]. High power
consumption during the functional operation implies:
 Higher design and manufacturing costs due to the extra effort to calibrate power grids in
order to meet the power supply requirement.
 Higher system costs due to packaging and cooling requirements.
 Shorter device life cycle and lower device reliability.
 Shorter battery life for portable devices.

In real world mobile applications, it is essential to save power in parts of the chip that are
not in use. Nowadays, chips integrate several systems on a single chip (SoC); each of these
SoCs is also called intellectual property (IP). In order to save current consumption, each IP
can move between power modes (power-off/power-on/sleep). Each IP is divided into power
domains, and those power domains can be turned on and off as well, according to the
power-mode. Memory and register values can be restored after being shut down (also called
retention). There are isolation cells which keep the turned off IP outputs in a previously
defined value, and this is how the shut-down IP does not corrupt other active IP
functionality [2]. Our power-management test methodology test the functionality of all the
power-management elements described above.

Why We need

Typically, to achieve testability in a SoC device, various DFT structures are inserted in
the design, such as memory BIST, boundary scan, and internal scan. Most of these
DFT structures are inserted in the synthesized structural (gate-level) netlist.
If the design has multiple power domains, a new set of DFT challenges will need to be
addressed. For example, how to control and stabilize various power domains during
test, how to create controllability and observability for the lowpower structures (isolation
cells, power shut-off gates, state retention registers, etc.), and how to minimize the
power during the test application.

For low-power test, there are two key issues. First, the design must be testable. On-
tester power consumption can dwarf operational power consumption, even at tester
clock speeds, because efficient test patterns cause a very high percentage of the logic
to be switching at a given time. Some chips would melt on the tester unless different
blocks are shut down at different times, as they are in various functional modes of
operation. So, for Power Shut-Off (PSO) test, scan chains must be constructed to
minimize power domain crossing and to bypass switchable domains when they are shut
down.

Once the design partitioning is understood, the second issue can be addressed. Power-
aware manufacturing tests can be created. These tests now have two goals: limit the
switching activity on the chip and test the advanced power logic such as level shifters,
PSO logic, and state retention gates.

EDA solutions may combine DFT capabilities, such as constructing scan chains that are
power domain aware, with advanced test pattern generation. To reduce power
consumption during manufacturing test, these power domain-aware scan chains can be
controlled during test by inserting logic that enables direct control of which power
domains are being tested. Combined with power domain-aware ATPG, this solution
tests advanced power structures and reduces power consumed during test.
Also, the vectors themselves can be constructed so that the changing values of the “filler” bits
are controlled to reduce the switching activity. This means that the power consumed during the
shifting of the scan patterns is controllable.
Power Management Circuit

The power management scheme is built by the power architect of the SoC in order to
reduce the current consumption of the chip. There are several common building blocks
which are used by the power management architect, as will be described in the next
sections.

Figure 1: Functional power management circuitry

A. Clock Gating:
It’s a powerful technique to reduce the power consumption in a power-on domain through
dynamically blocking the clock pulse to reach a set of sequential state elements. The clock
gating is often hierarchically implemented in order to improve the flexibility to control the
power consumption during functional operation.

B. Power Domains:
The design is created with multiple power domain blocks. Each block can be independently
powered up or down by controlling the power switches used to gate the power supply
connection to each power domain block.

C. Multiple supply voltages:

Depending upon operating conditions, different supply voltages are applied to different
power domain blocks, and each power domain blocks are connected using level shifters.

D. Low Power Cell:

State Retention Cell: The ability of state retention registers (SRRs) to retain their state
when the power domain is powered off needs to be validated during test. Conventional
structural tests, if applied while a given power domain is forced on, cannot validate state
retention since the domain is not powered off during the capture cycle.
Isolation Cell: The Isolation cells locate at the boundary of two power domains in order to
isolate the power off and power on domain.
 E. Power Switches:
To reduce power dissipation, especially leakage power dissipation introduced by shrinking
process technologies, power switches are commonly used in modern low power designs. To
enable the power gating functionality, different parts of the design are equipped with one or
more power switches

For a DFT product, this translates into the following considerations:

 Each step in the DFT insertion process must be made power aware;
 Additional work has to be done in order to test the power management structures
themselves;
 The tool must allow the user make the best trade-offs between DFT architecture options and
their impact on power management structure needs.

On the other hand, an ATPG tool:

 Must be guided by a power budget, usually in term of toggling activity;

 It needs to support the power management structures themselves;
 Finally, it also has to help the user make trade-off decisions in the area of pattern count,
test application time and power consumption.
As shown in Figure 3, DFT synthesis involves a multi-step process. The test protocol
creation helps the user define test protocols. Usually the user provides an initialization
sequence, and the tool completes the protocol based on user specification of test control
signals, clocks, and reset signals. The test design rules checking phase analyzes the design,
and based on the test protocol, it checks for critical issues that will negatively impact the
testability of the design [6].
Figure 3: Key components of DFT synthesis

Typical issues include clock and reset controllability. The user needs to fix any critical issues
before moving to the DFT architectural phase. This phase does not change the design.
Therefore, it allows the user to explore many DFT architectures based on variations of
constraint specifications.

The DFT implementation is the final step of the process. It realizes the DFT architecture in
the form it was previewed in the exploration phase. This results in DFT insertion and design
optimizations that take care of any design constraint violations introduced by DFT on global
control signals.

To improve the testability for the power management circuitry, DFT structure, such as the
Power Test Access Mechanism (PTAM) [7], can be inserted in the design by using the DFT
insertion tool as shown in Figure 4.
Figure 4: DFT architecture with test control mechanism

During test, this structure generates signals that override the control signals from the
functional power controller. This improves the flexibility to schedule the testing order for
power domains, ensures the power domains hold their power state in the middle of test,
and ensures the isolation between power domains with different power state, etc.

Conclusion

Testing complexity increases as low-power devices is making designs much more complex
and very strictly optimized for power. Design for low power is changing the way designs are
built and its testing rapidly became very intrusive at the point where all of the EDA tools
need to be made power aware and must have unified support for users’ power intent for
both designing and testing.

The goal of this paper is to study and implement low power designs and create environment
around design suitable for testing the logic. DFT is implemented with different methods for
testing both, core logic and power management circuits.