-- Company: -- Engineer: --- Create Date: -- Design Name: -- Module Name: counters - Behavioral -- Project Name: -- Target Devices:

-- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity counters is Port ( CLK : in STD_LOGIC; mode : in STD_LOGIC; rst : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (03 downto 00)); end counters; architecture Behavioral of counters is signal q_temp: std_logic_vector(3 downto 0); begin PROCESS(rst,mode,CLK) begin if(rst='0') then q_temp<="0000"; elsif(CLK' event and CLK='1') then if(mode='0') then q_temp<=q_temp+"0001"; else q_temp<=q_temp-"0001"; end if; end if; end PROCESS; Q<=q_temp;

end Behavioral;