Design A PLL For A Specific Loop Bandwidth - EDN

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Design a PLL for a specific loop bandwidth
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A-PLL-FOR-A-SPECIFIC-LOOP- /DESIGN-A-PLL-FOR-
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Today's PLL ICs make designing a high-quality, versatile frequency synthesizer

easier than ever. These devices have many built-in functions, such as serial
interfaces, phase detectors, and swallow counters. Typically, the only external
parts are the reference oscillator, VCO, loop filter, and dc decoupling
components. Some ICs, such as the MB15E03SL from Fujitsu
(www.fujitsumicro.com < http://www.fujitsumicro.com> ), also have built-
in circuitry for a crystal or an LC reference oscillator. Most of the synthesizer
applications are for wireless designs, for which the system specifications require
the synthesizer to operate over a bandwidth of 10% or less.
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Most of the written design information about calculating the loop filter for these
PLL synthesizers is based on how long it takes to “hop” from one frequency to
another. This design information is sufficient if you plan to use the synthesizer
only as a local oscillator, to convert one frequency to another, or as a continuous-
wave source at various frequencies. However, many applications use a
synthesizer to modulate a transmitter. In this case, the loop bandwidth may be
the controlling factor for the loop-filter design.
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If you plan to phase- or frequency-modulate the PLL, the desired loop bandwidth
will influence the choice of the loop-filter component values. Therefore, you must
2 of 12 1/15/24, 12:17
base the initial design on the desired loop bandwidth. Unfortunately, trade-offs
are necessary. A direct relationship exists between loop bandwidth and hop time:
The narrower the bandwidth, the longer it takes the synthesizer to step from one
frequency to another. If hop time is also important, you have to work out a
balance between loop bandwidth and hop time.
Define the basic requirements
To design a loop filter based on bandwidth, instead of the frequency hop or

switching time, consider the following example. You first define the basic
synthesizer requirements:
– Frequency range: 770.01 to 800.01 MHz;

– Channel spacing: 30 kHz;
– Maximum frequency hop: 30 MHz; and
– Loop bandwidth: 1000 Hz.
Then, you identify the active component specifications:
– VCO sensitivity: 22 MHz/V and

– PLL IC charge-pump current: 6 mA.
Now, you perform the PLL calculations for the typical loop-filter configuration in
Figure 1a. Table 1 lists the definitions of terms. The basic steps and
calculations for a given loop bandwidth are as follows:
1. Calculate FSTEP :
2. Calculate N:
3. Calculate FN :
3 of 12 1/15/24, 12:17
4. Calculate C2 :
5. Calculate R1 :
6. Calculate C1 :
7. Choose values of R2 and C3 :
R2 and C3 reduce any spurs that the reference frequency introduces.

The product of R2 and C3 should be at least one-tenth times the product of C 2
and R1 .
8. Calculate T :
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Step-by-step example
(1)
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(2)
(3)
(4)
(5)
(6)
(7) Let R2 =539?. Then, C3 =1.39 µF/10=0.139 µF.
(8)
Figure 1b shows the completed design using the closest standard component
5 of 12 1/15/24, 12:17
values. The measured results of this design working with an MB15E03SL-based

synthesizer show a close relationship between the design goals and the actual
performance. Figure 2 displays the phase noise between 100 Hz and 100 kHz.
The phase noise at 100 Hz (marker 0) is –72.0 dBc/Hz, and the phase noise at
1000 Hz (marker 1) is –75.5 dBc/Hz. Figure 2 also shows that the loop
bandwidth is very close to the desired 1000 Hz.
Figure 3 shows that the spurs are greater than –96.7 dBc at 30 kHz from the
carrier. Figure 4 shows that the hop time from 770.01 to 800.01 MHz is 7.65
msec. The loop bandwidth mainly determines this hop time. Table 2 shows the
approximate hop times that result when you use other loop bandwidths in the
design example.
Author info
Ken Holladay is applications manager for the wireless group at Fujitsu

Microelectronics. He has been with FMI for five years and has more than 20 years
of industry experience.
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Design a PLL for a speciﬁc loop bandwidth - EDN https://www.edn.com/design-a-pll-for-a-speciﬁc-loop-ban...

DESIGN < HTTPS://WWW.EDN.COM/CATEGORY/DESIGN/>

DESIGN HOW-TO < HTTPS://WWW.EDN.COM/CATEGORY/DESIGN

Design a PLL for a speciﬁc loop bandwidth

OCTOBER 12, 2000 <  COMMENTS 0 <

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Today's PLL ICs make designing a high-quality, versatile frequency synthesizer

Himax: Compo Redeﬁning

Deﬁne the basic requirements

To design a loop ﬁlter based on bandwidth, instead of the frequency hop or

– Frequency range: 770.01 to 800.01 MHz;

Then, you identify the active component speciﬁcations:

– VCO sensitivity: 22 MHz/V and

7. Choose values of R2 and C3 :

R2 and C3 reduce any spurs that the reference frequency introduces.

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values. The measured results of this design working with an MB15E03SL-based

Ken Holladay is applications manager for the wireless group at Fujitsu

0 COMMENTS ON “DESIGN A PLL FOR A SPECIFIC LOOP

Himax: Enabling AI Everywhere

Compo Electronics Receives 2023 Outstanding

Redeﬁning LiDAR and Perception Solutions: An

Cookie Settings Accept All

Renesas’ Transphorm acquisition points to GaN writing on the wall <

Cookie Settings Accept All

In this podcast, we get deep

VIEW ALL EPISODES

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David Bell on Simple log-scale audio meter < https://www.edn.com/simple-log-

WStephenWoodward on Simple log-scale audio meter < https://www.edn.com

WStephenWoodward on Simple log-scale audio meter < https://www.edn.com

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