Simple Processor Design and its VHDL

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 In Addition to the 4 n-bit shift register connected using
tri-state buffers, the system also includes Adder and a
Subtractor
◦ One of the inputs A is supplied by an n-bit register
◦ The other input B is connected to the bus
 The control signal ADD/SUB control the ADD(0) and
SUB(1) operation
◦ Subtraction is done using two’s complement

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Function: indicates specific operation to be performed
W: Initiates the operation
Done: is asserted when the operation is completed. 3
 We will design a control circuit that can perform the
four listed operations
 The left column is the name of the operation
◦ It lists the name of the operation and its operand
 RX and Ry can be any R0 to R3
◦ Load and move require 1 clk cycle
◦ Add/sub require 3 steps (clock cycles)
1- Transfer the content of Rx to A
2- Places the content of Ry onto the Bus
 Perform the required operation
 Store the result in register G
3- Transfer the content of G into Rx

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 The control unit will be designed using
counters
◦ This circuit has to generate the required
control signals for each step of the operation
◦ Since the longest operation is the ADD/SUB
which needs three steps
 A 2-bit counter is used and connected to 2-4
decoder
 The decoder is always enabled

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 Each of the decoder outputs represents a step in the operation
◦ When no operation the counter value is 00
 Hence T0 output is asserted
◦ In the first step of an operation the counter is 01
 => T1 =1
 During ADD/SUB
 T2 is asserted in step 2
 T3 is asserted in step 3
◦ In each of steps, T0->T3, various control signals have to be generated
depending on the operation being performed
 The operation is specified in 6 bits: F=[f1 f0 Rx1 Rx2 Ry1 Ry2]
 F=f1f0 is a two bit identifier which specifies the operation: 00, 01, 10, 11 for Load,
Move, Add and Sub respectively.
 Rx1 Rx0 and Ry1 Ry0 specify the operand address
 The function is stored in a six-bit Function register when FRin is set

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 Using the input w and the signals T0, …, T3, I0, …, I3, X0 …X3
and Y0 …Y3, the control circuit has to generate the outputs:
◦ R0in … R3in
◦ R0out … R3out
◦ Extern, Done
◦ Ain, Gin, Gout, AddSub, Clear, FRin

◦ Clear signal:
 Makes the counter 00 as long as w =0 and no operation is
executed
 Also it is used to clear the counter at the end of the
operation

◦ FRin Signal is used to load the values of the Function inputs register
when w changes to 1

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 The rest of the outputs is specified by the table below

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 The Extern is asserted only in the first step of
the load operation

 The Done is asserted in the Load and move

as well as in the third step of add and sub

 Ain, Gin and Gout are asserted in the add

and sub operation
◦ Ain is asserted in T1
◦ Gin is asserted in T2
◦ Gout is asserted in T3
◦ ADD/SUB =0 when add and 1 when SUB

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 The values R0in…R3in are determined either by X0…X3 or
Y0…Y3
◦ IF Rin = X or Rin = Y➔ R0in =X0 R1in = X1 and so on
 Similarly, Rout =X or Rout = Y
 We will develop R0in and R0out from table 7.3
◦ R0in is set to X0 in the first step of both Load a move and in the Third
step of ADDSUB

◦ Similarly, R0out is set to Y0 in the first step of Move, first and second
steps of Add/Sub to X0 and Y0 respectively
 It is set to Y0 in the second step of these operations

 R1in and R1out are the same as R0in and R0out except X1
and Y1 is placed instead of X0 and Y0

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Generate is
Also used to
To repeat a logic
Expression (but
not sequential
like LOOP)

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