Alexandria Engineering Journal (2020) 59, 3715–3729

H O S T E D BY
Alexandria University

Alexandria Engineering Journal

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Performance comparison of 6T SRAM bit-cells

based on side-contacted FED and CMOS
Tara Ghafouri, Negin Manavizadeh *

Faculty of Electrical Engineering, K. N. Toosi University of Technology, Tehran 1631714191, Iran

Received 6 May 2020; revised 26 May 2020; accepted 5 June 2020

Available online 26 June 2020

KEYWORDS
6T static random-access
memory (SRAM) bit-cell;
Side-contacted field effect
diode (S-FED);
Static noise margin;
Power dissipation;
Sensitivity analyses
Abstract Designing a Static Random-Access Memory (SRAM) cell configuration that copes with
conventional complementary metal-oxide-semiconductor (CMOS) constraints on the cell area is
desired to satisfy high packing density in integrated digital circuits. This paper analyzes and compares
performance parameters of 6T SRAM bit-cells based on the side-contacted field-effect diode (S-FED)
and conventional CMOS at 180 nm technology node. Steady-state responses demonstrate that in the
worst-case, by applying weak logic 0/1 to the bit-lines, strong logic data is stored in the S-FED-based
cell with superior write margin and lower power consumption by about one order of magnitude in
comparison with the CMOS-based one. Comparing static noise margin reveals that S-FED-based
cells enjoy prominent stability, especially in the read and hold operations with ~3X and 29% improve-
ments, respectively, to the CMOS-based versions. In addition, enhancement of read-stability is
attained utilizing S-FED-based cell, as well as decrement of subthreshold current and static power dis-
sipation, compared with the CMOS-based one. Sensitivity analyses extracted from Monte Carlo sim-
ulations and butterfly curves indicate that S-FED-based cell successfully tolerates process and supply
voltage variations in all operation modes, superior to the CMOS-based counterpart.
Ó 2020 The Authors. Published by Elsevier B.V. on behalf of Faculty of Engineering, Alexandria
University. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/
licenses/by-nc-nd/4.0/).

1. Introduction Operation modes of an SRAM cell include write, read and

hold 0/1 operations.
SRAM arrays are arranged in several rows and columns of Applying variations in structural parameters of SRAM bit-
storage bit-cells called bit-lines (BL and BL’) and word-lines cells throws considerable impacts on cell characteristics in
(WL) to control data access and storage. The bit-cells are bi- CMOS technology. In this regard, researchers attempt to sat-
stable flip-flops which can consist of 4 to 11 transistors with isfy the device- and circuit-level considerations in different
pull-up (PU), pull-down (PD), and pass-gate (PG) networks. configurations of SRAM cells.
In the device level, currently, an 7T SRAM cell has been
designed based on dual pocket double-gate tunnel field-effect
transistor (DP-DGTFFT) for ultralow-power applications
* Corresponding author.
[1]. High ION/IOFF in TFET is attributed to its band-to-band
E-mail address: manavizadeh@kntu.ac.ir (N. Manavizadeh).
tunneling mechanism that copes with the limit of subthreshold
Peer review under responsibility of Faculty of Engineering, Alexandria
swing in metal-oxide-semiconductor field-effect transistor
University.
https://doi.org/10.1016/j.aej.2020.06.026
1110-0168 Ó 2020 The Authors. Published by Elsevier B.V. on behalf of Faculty of Engineering, Alexandria University.
This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).
3716
(MOSFET) (60 mV/decade at room temperature) [2]. More-
over, employing multi-gate devices such as regular and nega-
tive capacitance fin field-effect transistors (FinFETs) in
SRAM cells has contributed to reducing leakage power [3].
A stable SRAM cell architecture has also been designed utiliz-
ing independent gate FinFET in [4], in which, a few control
signals are configured to adjust drive strengths of the con-
stituent devices. In [5], a CMOS-technology compatible tran-
sistor is introduced to suppress the charge sharing effect,
employing a new class of field-effect transistors with multiple
independent gates (MIGFETs). Charge sharing can degrade
the output voltage level in dynamic logic gates by redistribu-
tion of the charge loaded during the precharge phase through
the internal junction capacitances of the network [6]. In addi-
tion to Si-based SRAM cells, the novel structures have been
utilized in bit-cells and arrays such as carbon nanotube field-
effect transistor (CNTFET) [7], graphene nanoribbon field-
effect transistor (GNRFET) [8], single electron transistor
(SET) [9], and quantum-dot cellular automata (QCA) [10].
Although these nanostructure-based SRAM cells provide
highly scalable architectures, these confront complexities in
the fabrication and integration processes.
Optimization techniques in the circuit level are frequently
dedicated to improving the cell write-ability, read-stability
and power consumption compared with the conventional
CMOS-based SRAM cell. In this domain, single-ended SRAM
topologies have been presented for power-constrained applica-
tions [11]; however, these structures undergo increased read-/
write-access time and degraded write noise-immunity at low
supply voltages. To rectify write failures, some techniques
are adopted such as transient negative bit-line voltage
approach [12], strengthening PG network stemming from
WL boosting [13], supply downscaling [14], asymmetrical
write-assist approach, [15], applying cross-point data-aware
write word-line structure [16], and cutting off the feedback
loop of the inverter pair [17]. Reducing the bit-cell supply volt-
age decreases also both static and dynamic power [18]; how-
ever, it degrades read stability and data hold operation by
weakening PU network. On the other hand, reducing the bit-
lines precharging voltage improves read stability [13]. More-
over, the higher order cell topologies suggest better data stabil-
ity besides sustaining the power as low as possible [19];
however, the bit-cells occupy more area. These compromises
are inevitable in a CMOS-based SRAM cell, as downscaling
confines utilizing MOSFET in very large-scale integration
(VLSI) circuits. A Schmitt-trigger-based single-ended 11T
SRAM cell has been designed to improve read/write static
noise margin and consume low power at the cost of occupied
area [20]. Moreover, an 8T SRAM cell with charge recycling
read and write assist (CRRWA) technique [21] has also been
designed, which lowers switching power consumption by
reducing the voltage swing. This approach, nonetheless, leads
to the occupation of a large area. A robust 12T SRAM cell
with enlarged write margin has been presented by eliminating
a feedback of back-to-back inverters by means of data-
dependent supply cutoff during write operation [22]. Further-
more, a pseudo differential 12T (PD12T) SRAM cell has been
introduced in [23] offering high static noise margin in read and
hold operation modes while causing an area overhead. For-
ward body-biasing and reverse body-biasing are conventional
techniques that adjust the threshold voltage of driver transis-
tors; therefore, power dissipation in standby mode and switch-
T. Ghafouri, N. Manavizadeh
ing frequency in read and write operations are controlled
depending on the intended application [24–26]. In another
work, multi threshold and fingering techniques have been com-
bined to suggest MTCMOS SRAM cell with low leakage cur-
rent and improved read-stability; however, it also involves
additional transistors [27].
Regarding the above-mentioned techniques, packing den-
sity is an important issue in designing an SRAM bit-cell, in
addition to satisfying performance parameters. Devising an
alternative SRAM cell configuration which can overcome to
a large extent to demerits of conventional SRAM bit-cells
based on Si-technology is desired. Alternative structures have
revealed breakthroughs in the optimization of SRAM cell
characteristics within the realm of the CMOS technology
[12,18,28–33].
Field-effect diodes (FEDs) have been proposed to suppress
serious concerns derived from CMOS downscaling in the deep
submicron and nanoscale regime, such as hot electron and
short channel effects [34,35]. This nanoscale device enjoys
high-speed and low-power with considerably high ION/IOFF
ratio, making FED applicable in digital integrated circuits
[36]. Assembling FED-based fundamental logic gates [37,38]
and memory cells [39–43] as well as electrostatic discharge pro-
tection [44] realize high performance, packing density, and reli-
ability in the modern system-on-chips (SoCs). Modified
versions of FED, such as side-contacted FED (S-FED)
upgrade this capability by contributing to turning the device
properly OFF at the sub-100 nm channel length [35]. Remark-
ably, all FEDs located on a single chip are fabricated simulta-
neously through CMOS-compatible processes [38].
The proposed FED-based RAM cells in [39–42] consist of a
regular FED coupled with a silicon-on-insulator (SOI) MOS-
FET in series. Although the array comprising these bit-cells
enjoys high packing density, the aforementioned challenges
which confine employing conventional CMOS in VLSI circuits
recur. In this paper, a novel SRAM cell architecture involving
six S-FEDs is designed, analyzed and compared with the
CMOS-based counterpart at 180 nm SOI technology node in
terms of SRAM fingerprints, including stability of the bit-cell
in each operation mode, data retention capability, switching
frequency, read access time, different components of power
consumption, and finally process/voltage/temperature (PVT)
variability in accordance with Monte-Carlo analysis in the
SRAM cell.
The rest of this paper is organized as follows. Section 2 rep-
resents the proposed bit-cell in a coordinated device-circuit co-
design framework and describes simulation strategy. Section 3
evaluates the capability of S-FEDs to perform write/read oper-
ations. Section 4 analyzes the proposed bit-cell characteristics
and compares the results with the corresponding CMOS in all
operation modes. Section 5 studies sensitivity analyses extracted
from Monte Carlo simulations and butterfly curves under PVT
variations for the CMOS- and S-FED-based bit-cells in all oper-
ation modes. Finally, Section 6 concludes the paper.
2. 6T S-FED-based SRAM bit-cell design
2.1. S-FED structure and simulation strategy
Structurally, two main differences distinguish S-FED from the
conventional MOSFET, resulting in the outperformance of the
Performance comparison of 6T SRAM bit-cells
S-FED-based circuits over the CMOS-based ones. Firstly, two
separate gates (Gate-source or GS and Gate-drain or GD)
enhance the gate controllability over the channel. In addition,
oppositely doped source and drain regions contribute to the
formation of desired operation modes. Devising two other
oppositely doped layers underneath the source and drain areas,
called reservoirs, assist the FEDs to be turned OFF properly in
the nanoscale regime, thereby, the highest ION/IOFF ratio is
achieved and power dissipation is expected to be reduced.
Schematic of the S-FED structure is represented in Fig. 1.
Both device- and circuit-level simulations are performed
using TCAD tools as a semiconductor drift-diffusion solver,
to scrutinize the characteristics of S-FEDs and their derivative
3T and 6T SRAM bit-cells as well as the CMOS-based coun-
terparts. Physical models involve the concentration- and
temperature-dependent mobility, parallel electric field-
dependent mobility, Klaassen model, Fermi statistic depen-
dence, Shockley-Read-Hall and Auger recombination, band-
gap narrowing, band-to-band tunneling, and Lombardi CVT
model for expansion components attributed to mobility. Cali-
brator is set up by the simulation of nanoscale FED [37,38]
using TCAD tools. Geometrical parameters of S-FEDs are
adopted according to the high-performance (HP) logic
180 nm SOI CMOS technology node [45]. Reference power
supply (VDD) and back-gate voltages (VBG) are considered
1.2 V and 0.6 V, respectively and simulations are performed
at operating temperature 27 °C.
A typical strategy to reduce power consumption in the S-
FED-based digital VLSI designs is applying half of the supply
voltage to the back-gate terminal. In this way, no symmetric
gate voltages are required, therefore, logic ‘‘0” and logic ‘‘1”
are equivalent to 0 and VDD (for VBG = VDD/2), instead of

VDD and VDD (for VBG = 0), respectively. As a result, the
only a single power supply is required to design a digital circuit
and thereby the power consumption of the circuit is reduced.
In addition, by adjusting the reservoir thickness and engineer-
ing the gate work function of the S-FED, threshold voltage
and subsequently, leakage and switching power consumption
can be optimized as well as noise-immunity [37].
Taking 6T CMOS-based SRAM cells into account, transis-
tor widths must be carefully selected to guarantee cell stability
during the write, read and hold operations [46]. Therefore, the
appropriate widths for nMOS in PG network, nMOS in PD
network, and pMOS in PU network are conceived to be
Fig. 1 Schematic view of the S-FED structure.
3717
1 lm, 2 lm, and 0.5 lm, respectively. As can be seen further,
although a stronger PD network than PG one contributes to
read stability, this ratio is confined to guarantee write-ability;
since, a good write margin is achieved by strengthening PG
network rather than PU one. These selections are unlimited
for S-FED. Prominently, the possibility of utilizing identical
S-FEDs with the same geometrical parameters in each of the
PG, PD and PU networks contributes to reducing cell size,
owing to the same width-to-length ratio in all S-FEDs. In this
regard, the occupied areas by 6T S-FED- and CMOS-based
SRAM bit-cells are 1.86 lm2 and 4.34 lm2, respectively, typi-
cally in 180 nm technology node. In parallel, the constraints on
the using pMOS in PU network and nMOS in PD and PG net-
works are removed in the S-FED based circuits.
2.2. S-FEDs behavioral modeling in 6T SRAM bit-cell
The equivalent circuit of conventional bit-cell composed of six
MOSFETs is illustrated in Fig. 2(a). In a similar fashion, Fig. 2
(b) indicates that of the S-FED-based counterpart. In both
configurations, two cross-coupled inverters (Q1 to Q4) are
employed to store logic ‘‘0” and logic ‘‘1” and PG network
(Q5 and Q6) provides access to the stored data for read and
write operations. PG network is activated whenever a WL is
asserted, connecting the cell to the complementary BL and
BL’ columns. Certainly, PG network is controlled through
WL, while logic data is introduced into the cell through BL
and BL’ external sources.
Regarding 6T S-FED-based cell, Q2 and Q4 should behave
like an pMOS in PU network, and Q1, Q3, and Q5, Q6 should
act as an nMOS in PD and PG networks, respectively. To
achieve PD and PG n-SFEDs (VDS > 0), GD should be con-
nected to the fixed VDD and GS is free terminal. Also, S-FEDs
with the ground-connected GD and free GS terminal act as PU
p-SFED (VDS < 0). Accordingly, Q5 and Q6 which operate as
control switches should operate in saturation mode. Also, in
the coupling of two inverters connected back-to-back, p-
SFED of one inverter and n-SFED of the other inverter [Q2
and Q3 in Fig. 2(b)] are in cutoff mode; while two other S-
FEDs (Q1 and Q4) operate in linear mode. These considera-
tions come true by applying appropriate voltages to terminals
of each of the six S-FEDs, according to Table 1.
To find the optimum thickness of the reservoirs or source/
drain, the S-FEDs which are in OFF state, i.e., Q2 and Q3 are
regarded. To turn Q2 OFF, VGS and VGD are set in high and
low levels; therefore, by decreasing drain thickness or increasing
reservoir thickness, the accumulated hole concentration under-
neath GS surpasses the electron concentration in the channel
and thereby assists Q2 to raise IOFF and decline ION/IOFF, as
illustrated in Fig. 3(a). On the other hand, by applying 0 and
VDD to VGS and VGD, Q3 is turned OFF. By extending reservoir
regions of Q3, the accumulated electron (hole) concentration
underneath GD (GS) is intensified and thus, IOFF is declined
and ION/IOFF ratio rises, as shown in Fig. 3(a). In this compro-
mise, the optimal values for the source/drain and reservoir thick-
nesses are considered 25 nm and 15 nm, respectively.
2.3. Implementation of SRAM cell operation modes
In an SRAM cell, read and write operations commence with
activating WL and subsequently PG network. In read mode,
3718 T. Ghafouri, N. Manavizadeh

Fig. 2 The equivalent circuits of 6T SRAM bit-cell based on (a) CMOS and (b) S-FED.

Table 1 Operation modes and states of S-FEDs in 6T SRAM bit-cell topology.

Element VDS VGS VGD Structure State
+ +
Q1 ‘‘1” ‘‘1” ‘‘1” p nnn ON
Q2 ‘‘0” ‘‘1” ‘‘0” n+pnp+ OFF
Q3 ‘‘1” ‘‘0” ‘‘1” p+npn+ OFF
Q4 ‘‘0” ‘‘0” ‘‘0” n+ppp+ ON
Q5 ‘‘1” ‘‘1” ‘‘1” p+nnn+ ON
Q6 ‘‘1” ‘‘1” ‘‘1” p+nnn+ ON

the voltage at both bit-lines is precharged to high. By asserting
WL and assuming that logic ‘‘1” is prestored on node Q, neg-
ligible current flows through Q6 and BL voltage level remains
almost unchanged. Therefore, the output CBL is charged
through the fixed BL voltage. Nonetheless, Q1 and Q5 conduct
a non-zero current and thus, CBL’ is discharged slightly
through Q1 and Q5 (CBL and CBL’ are addressed with CO (R)
in Fig. 2). The voltage difference between two bit-lines will
be detected by the sense amplifier and accordingly logic ‘‘1”
is read from the cell. In the condition that logic ‘‘0” is pre-
stored on node Q, logic ‘‘0” is transferred to BL and read from
the cell in the same way. Data read operation is vulnerable and
threshold voltage plays a significant role in the stored data
destruction during the read operation. Since, the internal node
Q’ voltage during the current flow through Q5 may exceed the
threshold voltage of Q3, inflicting an undesired change of the
stored data by turning Q3 ON and Q4 OFF. As a result,
VQ’Vth (Q3) should be satisfied to properly read ‘‘1”. Accord-
Performance comparison of 6T SRAM bit-cells
Fig. 3 (a) ION/IOFF ratio of the OFF-state S-FEDs as a function of the reservoir thickness. (b) Transfer characteristics of S-FED and
CMOS at VDS = ±1.2 V.
ingly, VQ  Vth (Q1) provides the proper read ‘‘0” operation
and subsequently ensures read stability. Fig. 3(b) represents
transfer characteristics of S-FED and CMOS at 180 nm tech-
nology. |Vth| values for n-SFED and p-SFED are obtained
0.32 V and 0.65 V, respectively; whereas, both nMOS and
pMOS have almost the same |Vth|, equal to 0.36 V, implying
that S-FED-based SRAM cell enjoys higher read stability than
CMOS-based as well as lower leakage power dissipation owing
to lower subthreshold current rather than conventional
CMOS. As previously mentioned, S-FED has two more
degrees of freedom than CMOS to adjust threshold voltage,
i.e., altering the reservoir thickness and engineering the gates
work function, in addition to body-biasing technique [18].
In write mode, logic ‘‘1” and logic ‘‘0” are applied to BL and
BL’, respectively. By this approach, the output CQ’ is dis-
charged to drop Q’ voltage level down to 0 V. In the same
way, the output CQ is initiated to be charged and the comple-
mentary storage node Q rise up to VDD (CQ and CQ’ are
addressed with CO (W) in Fig. 2); thereby, logic ‘‘1” is overwrit-
ten in the cell. By presetting BL and BL’ voltages in low and high
levels, logic ‘‘0” is overwritten in the cell in a similar fashion.
In hold mode, WL is not asserted and thereby, PG network
is deactivated. In this condition, the SRAM cell sustains the
stored data while the supply voltage is powered ON [47].
3. Steady-state responses
Prior to characterize the S-FED- and CMOS-based SRAM
cell, the capability of S-FEDs to perform write/read operations
is evaluated and compared with the corresponding CMOS uti-
lizing DC mixed-mode simulations. The symmetry of 6T
SRAM bit-cell configuration facilitates the analysis of write/
read ‘‘0” by the contribution of Q1, Q2, and Q5, and simulta-
neously, write/read ‘‘1” by the contribution of Q3, Q4, and
Q6. Accordingly, VBL’ and VBL are swept from 0 to VDD to
first scrutinize steady-state responses ascribed to write ‘‘0”
and ‘‘1” operations, as indicated in Fig. 4(a) and (b) for 3T
S-FED-based cell and Fig. 4(c) and (d) for 3T CMOS-based
one, respectively. By increasing input VBL’ from 0 to VDD/2
(weak ‘‘0”), the transferred voltage to output VQ’ is varied
from 0 to 0.262 V for the S-FED-based cell and from 0 to
0.294 V for the CMOS-based one. Certainly, n-SFED Q5
passes a little bit stronger logic ‘‘0” and hence, the S-FED-
3719
based bit-cell has better write-ability than the CMOS-based
one. Output characteristics of Q5 in the insets of Fig. 4(a)
and (c) demonstrate that steady-state in the S-FED-based cell
emerges by flowing less current through Q5 (about one order of
magnitude) and thus, lower power consumption (at a constant
VBL’) rather than the CMOS-based one. In the same way, by
increasing input VBL from VDD/2 (weak ‘‘1”) to VDD, output
VQ plateaus at VBL = 0.83 V for the S-FED-based cell and
VBL = 1.08 V for the CMOS-based one. It implies that even
by applying weak ‘‘1” to VBL, n-SFED Q6 passes strong ‘‘1”
to VQ output. Output characteristics of Q6 in the insets of
Fig. 4(b) and (d) approve that at a constant VBL, less current
and thereby less power is required to attain steady-state in
the S-FED-based cell compared with the CMOS-based one.
On the other hand, it is comprehended that enhancement of
(W/L)PG proportional to (W/L)PU assists the current flowing
through nMOS Q6 to be constructive in discharging output
capacitance CQ to write ‘‘0” whenever logic ‘‘0” is applied to
BL external source. In this way, write-ability can be increased.
However, S-FED-based cells attain to superior write-ability
with the same (W/L)PG and (W/L)PU and smaller cell size to
the CMOS-based versions. (W/L)PG/(W/L)PU ratio is inter-
preted as a write margin (WM).
Read operation is analyzed based on the currents flowing
through each branch in both 3T S-FED- and CMOS-based
bit-cells at logic ‘‘0” and logic ‘‘1”, as shown in Fig. 5. Voltage
transfer characteristics (VTCs) in Fig. 5(a) reveal that both
logic ‘‘0” and logic ‘‘1” inverters of S-FED based cell undergo
minor degradations in the waveforms and thereby enjoy higher
voltage gains compared with the CMOS-based version. By
increasing input VQ’ from 0 to VDD/2 and input VQ from
VDD/2 to VDD, the current polarities at corresponding nodes
are compatible to preserve symmetrically flowing behavior in
both 3T cells. Accordingly, Q2 and Q4 in PU network
[Fig. 5(b)], Q1 and Q3 in PD one [Fig. 5(c)], and Q5 and Q6
in PG one [Fig. 5(d)] sink/source the similar currents. How-
ever, the S-FED-based cell requires fewer currents (about
one order of magnitude) to discharge/charge output capaci-
tances and perform read 0/1 operations. Thus, S-FED-based
cells consume lower switching power in both read and write
operations, compared with CMOS-based cells. Fig. 5(d)
demonstrates that increasing IS (Q5) output current is stopped
properly in the S-FED-based cell, since VQ’ is disallowed to
3720
Fig. 4 Steady-state responses to write logic ‘‘0” and logic ‘‘1” in (a,b) 3T S-FED-based and (c,d) 3T CMOS-based bit-cells.
surpass Vth (Q3). Regarding the contribution of Q1 and Q5 in
read ‘‘0” operation, to satisfy this consideration, (W/L)PD is
considered stronger than (W/L)PG in the CMOS-based bit-
cell and by this approach, read stability can be guaranteed.
(W/L)PD/(W/L)PG ratio is interpreted as a read margin
(RM). Although we consider RM the same for both S-FED-
and CMOS-based cells, read operation is expected to be more
stable for the S-FED-based cell with due attention to its shar-
per VTCs.
4. 6T SRAM bit-cell characteristics
In this section, transient and AC mixed-mode simulations are
added to DC ones to analyze and compare SRAM fingerprints
derived from 6T bit-cells based on S-FED and CMOS in hold,
write, and read operations.
Stability is one of the most important criteria in the design
of an SRAM bit-cell. Of the most reliable measures to evaluate
and quantify noise-immunity in an SRAM cell is static noise
margin (SNM), defined as the minimum level of DC noise volt-
age that might flip the cell data to an undesired state. Graph-
ically, the SNM is obtained from the confluence of the VTC of
one internal inverter and inverse VTC of the second inverter
for each operation mode. Hold static noise margin (HSNM)
and read static noise margin (RSNM) are attributed to the
length of the largest square that can be embedded between
T. Ghafouri, N. Manavizadeh
the two VTCs derived from the hold and read 0/1 operations,
respectively; whereas, write static noise margin (WSNM)
implies to the length of the smallest square for the write 0/1
operations [48,49]. Figs. 6 and 7 illustrate the SNMs for S-
FED- and CMOS-based SRAM cells in each operation mode,
respectively. To properly hold the stored data, a balance
between the current carrying capabilities of PD and PU net-
works is required. In CMOS-based circuits, this fact realizes
by enhancing (W/L)PU due to higher electron mobility than
hole mobility. By this approach, HSNM can be enhanced, as
indicated in Fig. 7(a). However, the surplus increase in pMOS
strength disturbs symmetrical behavior of VTCs besides write
margin. Considering WPD = 2 lm and WPU = 0.5 lm,
HSNM value is obtained 312 mV (26% VDD). Regarding the
write-ability and read stability mentioned in the previous sec-
tion, the bit-cell must be adequately stable to preserve the
stored data despite the voltage drop inflicted by the bit-lines
voltage; however, the bit-cell must also be weak enough to
ensure the write operation. Consequently, RM and WM
benchmarks must be set as a trade-off. As expected and illus-
trated in Fig. 7(b) and (c), increase in (W/L)PG leads to
WSNM enhancement and RSNM decrement in CMOS-
based bit-cells. Considering WPG = 1 lm, WSNM and RSNM
quantities are obtained 356 mV (30% VDD) and 55 mV (5%
VDD), respectively. By replacing nMOS and pMOS by
S-FEDs in 6T SRAM cell topology, HSNM, WSNM, and
Performance comparison of 6T SRAM bit-cells 3721

Fig. 5 (a) VTC of inverter 1 to read logic ‘‘0”. (b-d) I-V characteristics of each device used in 3T bit-cell, where solid and dashed lines
show the characteristics of S-FED- and CMOS-based 3T bit-cells, respectively. The insets represent those of corresponding devices in
inverter 2 to read logic ‘‘1”.

Fig. 6 VTC curves for (a) hold, (b) write, and (c) read operations in 6T S-FED-based SRAM bit-cell independent of the width of pull-
down, pull-up, and pass-gate networks (WPD = WPU = WPG).

RSNM quantities are obtained 403 mV (33.5% VDD), 271 mV
(22.5% VDD), and 182 mV (15.2% VDD), respectively, as
revealed in Fig. 6(a)–(c). HSNM improvement is owing to
superior balance in current driving capability between PD n-
SFEDs and PU p-SFEDs despite the same strength. The rea-
son RSNM is increased considerably in the S-FED-based cell
is that a higher threshold voltage of S-FED than that of
CMOS contributes to the read stability so that VQ’ is allowed
to rise further with respect to the consideration of VQ’Vth (Q3)
in the read operation.
In retention mode, the stored data can be preserved indef-
initely, as long as the power supply is ON. The leakage power
dissipated in this mode depends directly on the power supply
and thus, voltage scalability contributes to reducing the leak-
age power. As a result, VDD scaling must be stopped at a min-
imum voltage called data retention voltage (DRV). DC
3722 T. Ghafouri, N. Manavizadeh

Fig. 7 VTC curves for (a) hold, (b) write, and (c) read operations in 6T CMOS-based SRAM bit-cell as a function of the width of pull-
down, pull-up, and pass-gate networks (reference WPD = 2 lm).

Fig. 8 VTC curves for hold operation as a function of the supply voltage in 6T S-FED-based SRAM bit-cells (DRV = 100 mV).

Fig. 9 VTC curves for hold operation as a function of the supply voltage in 6T CMOS-based SRAM bit-cells (DRV = 51 mV).

analysis is used for DRV estimation as well as for SNM deriva-
tion. The DRV is extracted from the HSNM butterfly curve
for different supply voltages by finding the minimum voltage,
for which the area within the curve is non-zero [50]. In Figs. 8
and 9, HSNM curves are illustrated as a function of the supply
voltage for the S-FED- and CMOS-based SRAM cells, respec-
tively. Accordingly, the amounts of DRV are obtained 100 mV
for the S-FED-based cell and 51 mV for the CMOS-based ver-
sion. Regarding the higher threshold voltage of S-FED than
that of CMOS, S-FED-based cell requires distinctly higher
VDD (min) to retain the stored data without any deterioration
compared with the CMOS-based one.
To estimate the speed of read and write operations of both
bit-cells based on CMOS and S-FED, transient mixed-mode
simulations are performed by applying a square voltage with
an amplitude of 0-VDD and frequency of 12.5 MHz to the
word-line. Figs. 10 and 11 illustrate time sequence responses
ascribed to write 0/1 operations for both 6T S-FED- and
CMOS-based cells, respectively. Once being turned ON, PG
network will conduct a non-zero current and the output volt-
ages (VQ and VQ’) follow the input bit-lines voltages (VBL
and VBL’) with the rise time and fall time equal to 0.75 ns
and 0.32 ns, respectively, for the S-FED-based cell
[Fig. 10(a) and (b) (insets)] and the same rise time and fall time
equal to 0.12 ns for the CMOS-based one [Fig. 11(a) and (b)
(insets)]. The required time to flip the bit-cell data to the oppo-
site state (overwrite in the cell) is equal to the time elapsed to
charge/discharge the output capacitance, i.e., (trise + tfall)/2.
Performance comparison of 6T SRAM bit-cells
Fig. 10 Time sequence responses for (a, b) hold operation followed by the write operation. (c, d) Read operation in 6T S-FED-based
SRAM bit-cell.
The pertinent frequency is called switching frequency and
calculated as fswitching = 1/[(trise + tfall)/2]. Accordingly, the
maximum data write speeds are obtained 1.869 GHz and
8.333 GHz for S-FED- and CMOS-based SRAM cells, respec-
tively. Hence, the power consumption of the CMOS-based cell
during the write operation is expected to be higher than that of
the S-FED-based one. In addition, significant overshoots by
about 40 mV, 500 mV [Fig. 11(a)] and 120 mV [Fig. 11(b)]
in output timing diagrams of the CMOS-based cell have
been mitigated to about 10 mV in those of the S-FED-based
cell [Fig. 10(a) (inset)]. This reduction stems from less
input-to-output coupling capacitance in the S-FED-based
SRAM bit-cell, compared with the CMOS-based one.
The hold operation is controlled by the voltage applied to
the word-line, so that once falling edge occurs, the hold phase
is initiated. As shown in Fig. 10(a,b) and 11(a,b), output volt-
age degradations at the beginning of hold ‘‘0” and ‘‘1” opera-
tions are about 860 mV and 689 mV, respectively, for the
CMOS-based cell. These amounts have been reduced to about
270 mV and 50 mV, respectively, for the S-FED-based version.
Therefore, standby leakage power dissipation in the S-FED-
based cell is conceived to be less than that of the CMOS-
based cell.
Time sequence responses in Figs. 10(c,d) and 11 (c,d)
demonstrate that read operation is vulnerable, especially for
the CMOS-based SRAM bit-cells. As expected, the outperfor-
mance of the S-FED-based cell in the read operation is attrib-
3723
uted to a higher threshold voltage of S-FED than that of the
corresponding CMOS. However, the S-FED-based cell experi-
ences a little bit longer read access time compared with the
CMOS-based version. Regarding the timing diagrams for the
read operation, the rise time for both S-FED- and CMOS-
based cells is approximately 40 ns; whereas, the fall time is
approximately 23 ps for the S-FED-based cell and 13 ps for
the CMOS-based one. According to switching frequency calcu-
lation, the maximum data read speeds for S-FED- and CMOS-
based bit-cells are obtained approximately 49.971 MHz and
49.984 MHz, respectively.
The power consumption in SRAM bit-cells is mainly
divided into dynamic (switching) power consumption in the
write and read operations and static (leakage) power dissipa-
tion in the hold mode. Charging and discharging the output
capacitors (Cload) in the circuit with respect to the read or write
operations inflict dynamic power consumption (Pdynamic). The
load capacitors involved in the read operation are source-to-
bulk capacitors of Q5 and Q6; whereas, the load capacitors
involved in the write operation are drain-to-source capacitors
of Q1 to Q6 and source-to-GS capacitors of Q1 to Q4. Pdynamic
is computed by AC mixed-mode simulations, according to [13]:
Pdynamic ¼ fswitching  Cload  VDD 2 ; in units of Watt ð1Þ
or:
Pdynamic ¼ Cload  VDD 2 ; in units of Watt:Hz
1 ð2Þ
3724
Fig. 11 Time sequence responses for (a, b) hold operation followed by the write operation. (c, d) Read operation in 6T CMOS-based
SRAM bit-cell.
The second component of power dissipation in SRAM cir-
cuits is static power (Pstatic). Although both inverters are in
stable logic states in retention mode, small amounts of leakage
current (Ileak) are induced due to reverse-biased diode leakage,
gate induced drain leakage, gate oxide tunneling, and sub-
threshold leakage. Pstatic is calculated using DC mixed-mode
simulations, according to [13]:
Pstatic ¼ VDD  Ileak ¼ VDD  ðISðQ2 Þ þ ISðQ4 Þ Þ; ð3Þ
Fig. 12(a) and (b) indicate different components of power
consumption as a function of power supply scaling, for the
S-FED- and CMOS-based SRAM cells, respectively. Appar-
ently, the power consumption for the read operation is lower
than that of the write operation, at a constant VDD, in accor-
dance with the higher data write speed than read speed, for
both bit-cells. As mentioned in Section 3, the currents flowing
all S-FEDs in both read and write operations were declined by
about one order of magnitude compared with their corre-
sponding MOSFETs. On the other hand, regarding the superi-
ority of the CMOS-based cell in terms of data write speed, it
was expected that dynamic power consumption during the
write operation for the S-FED-based cell is lower than that
of the CMOS-based one. Although there is 8 times as data
write speed for the CMOS-based cell as for S-FED- based
one, the power consumption (write) for the S-FED-based cell
is degraded by about 30 times. Moreover, although data read
speed is obtained almost the same for both bit-cells, the S-
FED-based cell enjoys lower power consumption during the
read operation, in each supply voltage, compared with the
T. Ghafouri, N. Manavizadeh
CMOS-based counterpart. Regarding the higher threshold
voltage of S-FED than that of CMOS, S-FED-based SRAM
cells are immune to subthreshold current, as well as noise in
the hold operation. Accordingly, these cells sustain lower static
power dissipation in each supply voltage, by about one order
of magnitude in comparison with the CMOS-based ones. As
illustrated in Fig. 12(a) and (b), voltage scalability throws its
impact on both switching and leakage power dissipation of
the SRAM cells. One of the popular approaches to reduce
both components of power consumption is VDD scaling; how-
ever, scaling is allowed to decrease to DRV amount. In addi-
tion, by downscaling VDD extremely, sub-threshold currents
may appear, which increase the static power. Taking these
compromises into consideration contributes to design low-
power and noise-immune SRAM bit-cells.
5. Stability analysis under PVT variations
As previously mentioned, SNM is one of the figures of merits
evaluating bit-cell stability whenever a device mismatch occurs
in a part of the circuit. The impact of the process, supply volt-
age and temperature (PVT) variability is destructive, especially
on the hold and read operations. Figs. 13 and 14 represent
HSNM and RSNM butterfly curves under PVT variations
for the S-FED-based SRAM bit-cell, respectively. Likewise,
Figs. 15 and 16 illustrate those of the CMOS-based counter-
part. The probable failures related to technology scaling are
derived from the fabrication process such as W/L deviations,
random dopant fluctuations, flat-band condition, interface
Performance comparison of 6T SRAM bit-cells
Fig. 12 Dynamic (switching) and static (leakage) power dissipation components in 6T SRAM bit-cells based on (a) S-FED and (b)
CMOS under supply voltage variations.
roughness, and gate-oxide thickness. These effects inflict an
increase in process variability and subsequently large deviation
in threshold voltage, speed, stability, and power consumption
of traditional SRAM designs [51]. Figs. 13(a) and 14(a) indi-
cate that for ±15% variation in channel length (Lch), i.e.,
[153 nm, 207 nm], HSNM and RSNM are varied in the ranges
of [376 mV, 430 mV] and [168 mV, 190 mV] for the S-FED-
based cell, respectively; while, Fig. 15(a) and 16(a) render the
ranges of [294 mV, 359 mV] and [43 mV, 107 mV] for HSNM
and RSNM of the CMOS-based counterpart, respectively.
Explicitly, HSNM and RSNM variations in the S-FED-
based cell have decreased by about 5.5% and 49.8%, respec-
tively, compared with the CMOS-based cell (at a constant
VDD = 1.2 V and T = 27 °C). It implies that the S-FED-
based cell is Lch-tolerant with higher stability compared with
the CMOS-based one, especially in the vulnerable read
operation.
A low value of supply voltage (DRV) is always preferable
in retention mode to reduce the power dissipation; however, a
stable bit-cell is achieved while maintaining full VDD during
the read cycle and hold state. Since data retention highly
depends on supply voltage, the HSNM is expected to be
decreased by downscaling VDD. Moreover, reduced cell supply
voltage inflicts a weak PU network. Subsequently, WM bench-
mark rendering the WSNM enhances and RM benchmark ren-
dering the RSNM reduces. As can be seen in Figs. 13(b) and 14
(b), considering 50% variation in supply voltage, i.e., [0.6 V,
1.2 V], HSNM and RSNM are varied in the ranges of
Fig. 13 HSNM butterfly curves under (a) process and (b) supply voltage variations. (c) Representation of data retention voltage in terms
of operating temperature for the S-FED-based SRAM bit-cell.
3725
[243 mV, 403 mV] and [143 mV, 182 mV] for the S-FED-
based cell, respectively; while, these variation ranges are
[180 mV, 312 mV] and [44 mV, 55 mV] for HSNM and RSNM
of the CMOS-based counterpart, respectively [see Figs. 15(b)
and 16(b)]. Explicitly, HSNM and RSNM variations in the
S-FED-based cell have decreased by about 2.6% and 1.6%,
respectively, in comparison with the CMOS-based cell (at a
constant Lch = 180 nm and T = 27 °C). It implies that despite
the SNM values decrease as VDD decreases to DRV, the
S-FED-based bit-cell has tolerated supply voltage drop to
VDD/2, in both hold and read operations, with slightly superior
stability to the CMOS-based counterpart. This superiority is
achieved by satisfying SNM benchmarks equal to unity in all
operation modes of the S-FED-based SRAM bit-cell.
SRAM bit-cells are systematically susceptible to tempera-
ture variation. Although a rise in operational frequency of
SRAM cells emerges at high junction temperatures, fluctua-
tions probability of carriers increases as a result of excessive
increase in temperature. In this condition, PG network
becomes unable to pass the strong logical data, or PD and
PU networks fail to properly hold the data for a long time.
Consequently, the SNM butterfly curves shrink in all opera-
tion modes and DRV rises. Fig. 13(c) and 15(c) demonstrate
DRV variations extracted from HSNM butterfly curves as a
function of temperature in a wide range of operating tempera-
tures, i.e., [
45 °C, 125 °C], for the S-FED- and CMOS-based
cells, respectively. By increasing temperature during the hold
state, DRV amounts are varied in the ranges of [75.9 mV,
3726 T. Ghafouri, N. Manavizadeh

Fig. 14 RSNM butterfly curves under (a) process, (b) supply voltage, and (c) temperature variations for the S-FED-based SRAM bit-
cell.

Fig. 15 HSNM butterfly curves under (a) process and (b) supply voltage variations. (c) Representation of data retention voltage in terms
of operating temperature for the CMOS-based SRAM bit-cell.

Fig. 16 RSNM butterfly curves under (a) process, (b) supply voltage, and (c) temperature variations for the CMOS-based SRAM bit-
cell.

148.2 mV] for the S-FED-based cell and [45.6 mV, 84 mV] for
the CMOS-based counterpart. Also, Figs. 14(c) and 16(c)
show that by increasing temperature during the read mode,
RSNM values are varied in the ranges of [97 mV, 242 mV]
for the S-FED-based cell and [20 mV, 82 mV] for the
CMOS-based counterpart. Explicitly, the S-FED-based cell
has experienced an increase of 11% in DRV variations and
36% in RSNM variations compared with the CMOS-based
cell (at a constant Lch = 180 nm and VDD = 1.2 V). It is orig-
inated from that carriers in the channel of S-FED encounter
with an extra p-n junction, raising the probability of switching
type of carriers in the channel in high temperatures. This
increases S-FEDs failure probability to operate in desired
modes, according to Table 1 and thereby, SNM is reduced.
However, the S-FED-based cell has tolerated temperature
variations, in both hold and read operations, with slightly infe-
rior data retention capability to the CMOS-based counterpart.
Another representation to evaluate the reliability of the
SRAM bit-cells under process variations is Gaussian distribu-
tion with a mean value lp and a standard deviation rp
extracted from Monte Carlo (M
C) simulations. Figs. 17
and 18 show the results of M-C simulations with random
Lch mismatch in all S-FEDs and MOSFETs in 6T SRAM
bit-cells, respectively. All simulations are performed at 541
points, considering lp = 180 nm and rp = ±5% to analyze
variations in an interval of 3rp. The histograms approximated
to Gaussian probability density function (PDF) indicate the
number of occurrences per SNM. As can be seen in Fig. 17,
Performance comparison of 6T SRAM bit-cells 3727

Fig. 17 Monte Carlo simulation results with the estimated Gaussian distributions on the device channel length (rp = ±5%) for the S-
FED based SRAM bit-cell. Modeling of the (a) HSNM, (b) WSNM, and (c) RSNM distributions.

Fig. 18 Monte Carlo simulation results with the estimated Gaussian distributions on the device channel length (rp = ±5%) for the
CMOS-based SRAM bit-cell. Modeling of the (a) HSNM, (b) WSNM, and (c) RSNM distributions.

HSNM, WSNM and RSNM in the S-FED-based cells are dis-
tributed normally. Also, their corresponding Gaussian PDFs
(lSNM, rSNM) have smaller rSNM, in accordance with their
narrow-edge SNM butterfly curves [Figs. 13(a) and 14(a)],
compared with the CMOS-based counterparts [Figs. 15(a)
and 16(a)]. It implies that S-FED-based SRAM cells enjoy
superior robustness under technology scaling in all operation
modes, compared with the CMOS-based versions. Although
WSNM is larger for the CMOS-based bit-cell, process varia-
tions throw adversely more impact on the write-ability, com-
pared with the S-FED based one. As a result, employing the
S-FED in VLSI digital circuits and systems is expected to guar-
antee their mismatch-robustness as well as noise-immunity.
6. Conclusion
This paper analyzed and compared performance parameters of
6T SRAM bit-cells based on the conventional CMOS and the
previously proposed S-FED in 180 nm SOI technology, utiliz-
ing DC, AC, and transient mixed-mode simulations. Optimum
reservoir thickness was achieved so that high ION/IOFF ratio in
the S-FED can be preserved to design low-power S-FED-
based SRAM cells. Identical S-FEDs with the same geometry
can play the role of both nMOS and pMOS in 6T SRAM cell
topology with smaller cell size. Steady-state responses revealed
that in the worst-case, by applying weak logic 0/1 to the bit-
lines, strong logic data is stored in the S-FED-based cell with
superior WM benchmark and lower power consumption com-
pared with the CMOS-based one. Employing S-FED with
higher threshold voltage than that of CMOS in 6T SRAM cell
configuration contributes to the prominent enhancement of
RSNM and HSNM as well as decrement of parasitic capaci-
tance, static and dynamic power consumption in the S-FED-
based cell. As a compromise, WSNM, data write speed and
read access time obtained for the CMOS-based cell are equally
or a bit more desirable compared with the S-FED-based ver-
sions. However, the superior outcomes of the S-FED-based
SRAM bit-cell are more outstanding. Sensitivity analysis
extracted from butterfly curves and Monte Carlo simulations
demonstrated that S-FED-based cell is Lch- and VDD-
tolerant with higher stability in comparison with the CMOS-
based one, especially in the vulnerable read operation. More-
over, the S-FED-based cell enjoys desirable stability even in
high temperatures. S-FED has two more degrees of freedom
than CMOS in controllability of the characteristics, through
adjusting the reservoir thickness and engineering the gates
work function. This merit assisted with superior stability of
the S-FED-based cell under technology scaling demonstrates
that S-FEDs with CMOS-compatible fabrication process
empirically facilitate the massive utilization of these devices
as the building blocks of the VLSI digital circuits in the future.
Declaration of Competing Interest
We wish to confirm that there are no known conflicts of
interest associated with this publication.
3728
Acknowledgement
This work has been supported by the Iran National Science
Foundation (INSF) under Grant No. 94021178.
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