AVR

AVR INSTRUCTION SET

Under the Guidance of: Dr. Sujata C.
TEAM 15
SEM:05 DIVISION :C2
NAME ROLL NO USN
MEGHA I 355 01FE21BCS042
SHREYA G 338 01FE21BCS030
KIRTHI G 354 01FE21BCS025
DHANSHREE P 348 01FE21BCS310
Table of Contents
1.Introduction
2.AVR Instruction set
• 2-byte instructions
• 3-byte instructions
• 4-byte instructions
3. Description of Features with Examples
4. Comparison of AVR with SIC/XE Features
5. Conclusion
Introduction to AVR Instruction Set
AVR instruction set is collection of assembly language
instructions that are specifically designed for AVR micro-
controller Architecture.

Key Components of AVR Instruction Set

Mnemonic: The name of the instruction.
Length: The number of bytes in the instruction.
Opcode: The hexadecimal code representing the instruction.
Effect: A brief description of what the instruction does.

Instruction Lengths
AVR instructions come in 2, 3, and 4-byte lengths.
2-Byte Instructions: Basic operations.
3-Byte Instructions: More complex operations.
4-Byte Instructions: Branches, jumps, and function calls.

Importance of the AVR Instruction Set

Foundation of countless embedded systems.Efficient code
execution and resource management.Broad range of
applications, from appliances to industrial automation.
Description of features with example

This section provides a detailed description of the features of the AVR instruction

set. Examples of how to use the instructions are also provided.

AVR Instruction Set Documentation

1- Byte Instructions
Mnemonic length Opcode Effect Note
ADDI 1 bytes 0110KKKKddddKKKK Add Immediate KKKK-ImmediateValue
to Register dddd-Destination Register
CPI 1 bytes 0011KKKKddddKKKK Compare with KKKK-ImmediateValue
Immediate dddd-Destination Register
ANDI 1 bytes 0111KKKKddddKKKK AND KKKK-ImmediateValue
Immediate dddd-Destination Register
with Register
ORI 1 bytes 0110KKKKddddKKKK OR Immediate KKKK-ImmediateValue
with Register dddd-Destination Register
XORI 1 bytes 0110KKKKddddKKKK XOR KKKK-ImmediateValue
Immediate dddd-Destination Register
with Register:
SBCI 1 bytes Subtract with KKKK-ImmediateValue
0100KKKKddddKKKK Carry dddd-Destination Register
Immediate
SUBI 1 bytes 0101KKKKddddKKKK Subtract KKKK-ImmediateValue
Immediate dddd-Destination Register
from Register
LDS 1 bytes 1001000ddddd0000 Load Direct KKKK-ImmediateValue
KKKK KKKK KKKK from Data dddd-Destination Register
KKKK Space
STSR 1 bytes 1001001ddddd0000 Store Indirect KKKK-ImmediateValue
KKKK KKKK KKKK from Register dddd-Destination Register
KKKK in Data Space
BRBS 1 bytes 1111010kkkkkkkkk Branch if Bit in Kkkkkkkkk-Relative Offset
Status Register or Bit Number
is Set
BRBC 1 bytes 1111011kkkkkkkkk Branch if Bit KImmediatevalue
in Status fromregisterDD – Regis
Register is ter
Cleared

2-byte Instructions
Mnemonic length Opcode Effect Note
SLEEP 2 bytes 1001 0101 1000 1000 Sleep -
NOP 2 bytes 0000 0000 0000 0000 No operation -
SEC 2 bytes 1001 0100 0000 1000 Set carry flag -
WDR 2 bytes 1001 0101 1010 1000 Watchdog Reset -
IJMP 2 bytes 1001 0100 0000 1001 Indirect Jump -
EIJMP 2 bytes 1001 0100 0001 1001 Extended Indirect -
- Jump
LDI 2 bytes 1110 KKKK dddd KKKK Load immediate K -Immediate value
( 16 ≤ d ≤ 31, 0 ≤ K ≤ into register DDDestination regis
255) ter
CPI 2 bytes 0011 KKKK dddd KKKK Compare K - Immediate value
(16 ≤ d ≤ 31, 0 ≤ K ≤ immediate with DD -
255) register Destination register
SBCI 2 bytes 0100 KKKK dddd KKKK Subtract with K - Immediate value
(16 ≤ d ≤ 31, 0 ≤ K ≤ Immediate value DD - register
255)
SUBI 2 bytes 0101 KKKK dddd KKKK Subtract K - Immediate value
(16 ≤ d ≤ 31, 0 ≤ K ≤ immediate from from register
255) register DD - Register
ORI 2 bytes 0110 KKKK dddd KKKK Logical OR with KImmediatevalue
(16 ≤ d ≤ 31, 0 ≤ K ≤ immediate fromregisterDD -
255) Register
ANDI 2 bytes 0111 KKKK dddd KKKK Logical AND K - Immediate value
(16 ≤ d ≤ 31, 0 ≤ K ≤ with immediate with register
255) DD - Register
SBC 2 bytes 0000 10rd dddd rrrr Subtract with R-Destination
(0 ≤ d ≤ 31, 0 ≤ r ≤ 31) carry register
R-Source resister-
SUB 2 bytes 0001 10rd dddd rrrr Subtract without R-Destination
(0 ≤ d ≤ 31, 0 ≤ r ≤ 31) carry register
R-Source resister-
ADC 2 bytes 0001 11rd dddd rrrr Add with carry R-Destination
(0 ≤ d ≤ 31, 0 ≤ r ≤ 31) between registers register
R-Source resister-
EOR 2 bytes 0010 01rd dddd rrrr Exclusive OR R-Destination
(0 ≤ d ≤ 31, 0 ≤ r ≤ 3) between registers register
R-Source resister-
OR 2 bytes 0010 10rd dddd rrrr Logical OR R-Destination
(0 ≤ d ≤ 31, 0 ≤ r ≤ 31) between registers register
R-Source resister-
MOV 2 bytes 0010 11rd dddd rrrr Copy Register R-Destination
(0 ≤ d ≤ 31, 0 ≤ r ≤ 31) between registers register
R-Source resister-
CPC 2 bytes 0000 01rd dddd rrrr Compare R-Destination
(0 ≤ d ≤ 31, 0 ≤ r ≤ 31) between registers register
R-Source resister-
CBR 2 bytes 0111 KKKK dddd KKKK clear bits in KK - Bit mask
(16 ≤ d ≤ 31, 0 ≤ K ≤ register DD -
255) Destination register
SBIS 2 bytes 1001 1011 AAAA Abbb skip if bit in set DD - Destination
(0 ≤ A ≤ 31, 0 ≤ b ≤ 7) register
KK - Bit number
SBIC 2 bytes 1001 1001 AAAA Abbb skip if bit in DD - Destination
(0 ≤ A ≤ 31, 0 ≤ b ≤ 7) clear register
KK - Bit number
SBI 2 bytes 1001 1010 AAAA Abbb set bit in I/O DD - Destination
(0 ≤ A ≤ 31, 0 ≤ b ≤ 7) register register
KK - Bit number
CBI 2 bytes 1001 1000 AAAA Abbb clear bit in I/O DD - Destination
(0 ≤ A ≤ 31, 0 ≤ b ≤ 7) register register
KK - Bit number
ADIW 2 bytes 1001 0110 KKdd KKKK Add immediate KK - Immediate value
(d ∈ {24,26,28,30}, 0 ≤ K to word DD -
≤ 63) Destination register p
air
SBIW 2 bytes 1001 0111 KKdd KKKK Subtract KK - Immediate value
(d ∈ {24,26,28,30}, 0 ≤ K immediate DD -
≤ 63) from word Destination register p
air
LD 2 bytes 1001 000d dddd 1100 Load indirect PQQQQQ - Register
(0 ≤ d ≤ 31) from data pair pointer
space
ST 2 bytes 10q0 qq1r rrrr 1qqq Store indirect PQQQQQ - Register
(0≤ r ≤ 31, 0 ≤ q ≤ 63) to data space pair pointer

3-Bytes Instruction
CBR 3 bytes 0111KKKKDDDDKKKK clear bits in KK - Bit mask
register DD - Destination register
SBIS 3 bytes 1001101DDDDKKKKK skip if bit in set DD - Destination register
KK - Bit number
SBIC 3 bytes 1001100DDDDKKKKK skip if bit in DD - Destination register
clear KK - Bit number
SBI 3 bytes 1001100DDDDKKKKK set bit in I/O DD - Destination register
register KK - Bit number
CBI 3 bytes 1001100DDDDKKKKK clear bit in I/O DD - Destination register
register KK - Bit number
ADIW 3 bytes 10010110KKDDKKKK Add immediate KK - Immediate value
to word DD -
Destination register pair
SBIW 3 bytes 10010111KKDDKKKK Subtract KK - Immediate value
immediate DD -
from word Destination register pair
LD 3 bytes 1001000PPQQQQQQQ Load indirect PQQQQQ - Register pair
from data pointer
space
ST 3 bytes 1001001PPQQQQQQQ Store indirect PQQQQQ - Register pair
to data space pointer

4-bytes Instruction
LDS 4 bytes 1001 010k kkkk 110k kkkk Load direct from data K - Data
kkkk kkkk kkkk space address
(0 ≤ d ≤ 31, 0 ≤ k ≤ 65535)
JMP 4 bytes 1001 010k kkkk 110k kkkk Jump to an address K - Data
kkkk kkkk kkkk address
(0 ≤ k < 4M)
CALL 4 bytes 1001 010k kkkk 111k kkkk Calls to a subroutine K - Data
kkkk kkkk kkkk within the entire address
(0 ≤ k < 4M) Program memory
STS 4 bytes 1001 001d dddd 0000 kkkk Store direct from K - Data
kkkk kkkk kkkk data space address
(0 ≤ d ≤ 31, 0 ≤ k ≤ 65535)

Comparison of AVR with SIC/XE Features

It compares the AVR instruction set to the SIC/XE instruction
set. SIC/XE is a classic RISC instruction set that is often used in
teaching computer architecture.
Aspect AVR
Memory Typically, Flash (16/32
KB or more),SRAM (1-8
KB), and EEPROM (1-4
KB)
Registers 32 general-purpose
registers (32 x 8 bits)
special-purpose
registers. (program
counter, stack pointer,
status registers, etc.)
Data Format 8 or 16-bit binary data
Addressing Modes Various addressing
modes including
register, direct, indirect,
indexed, and relative
addressing modes
Instruction Format RISC architecture with
16/32-bit fixed-length
instructions
Input/Output Specialized I/O ports,
peripherals, and
memory-mapped I/O
SIC
Single flat address
space, typically 2048
memory words.
Limited registers
including the
accumulator (16 bits),
index register (16 bits),
and condition code
register
16-bit binary data
Simpler addressing
modes including
immediate, direct,
indexed, relative, etc.
CISC architecture with
variable-length
instructions.
Input/output operations
often done through
custom instructions or
memory-mapped I/O

The AVR instruction set is very similar to the SIC/XE instruction

set. However, the AVR instruction set has a few additional
features, such as a two-level subroutine call stack, hardware
support for multiplication and division, and power-saving
modes.
Here are some additional specific differences between the two
instruction sets:
The AVR instruction set has a wider range of addressing modes
than the SIC/XE instruction set. This makes the AVR instruction
set more flexible and efficient.
The AVR instruction set has a number of instructions that are
specifically designed for controlling peripherals, such as the
timer and ADC. This makes the AVR instruction set well-suited
for embedded systems development.
The SIC/XE instruction set has a number of instructions that are
specifically designed for floating-point arithmetic. The AVR
instruction set does not have any floating-point instructions,
but it can be used to perform floating-point operations using
software routines.
Overall, the AVR instruction set is a more powerful and versatile
instruction set than the SIC/XE instruction set. It is well-suited
for a wide variety of applications, including embedded systems
development.
Conclusion
This report provides a comprehensive overview of the AVR
instruction set. It is a valuable resource for anyone who wants
to learn more about AVR microcontrollers and how to program
them.It is Versatile, efficient, and fundamental in the world of
embedded systems.

References
 AVR Instruction Set Manual