Schematics - Jimny Row - Moto g8 Play

5 4 3 2 1
[7] DVDD_MODEM
[7] DVDD_GPU
U101E
C101 22uF;20%;6.3V;0603 MT6771-DDR4 C102 22uF;20%;6.3V;0603
C103 22uF;20%;6.3V;0603 MT6771-SBS C104 22uF;20%;6.3V;0603

Schematic design notice of "10_BB_POWER_PDN" page.
[7] DVDD_MODEM_PMIC_FB Note: 10-3 VMODEM VGPU Note: 10-1 DVDD_GPU_PMIC_FB [7]
[7] DVDD_MODEM_PMIC_GND DVDD_GPU_PMIC_GND [7]
AA15 J19
AA19 DVDD_MODEM1 DVDD_GPU1 J20 Note 10-1: Differential pair of DVDD_GPU remote sense
DVDD_MODEM2 DVDD_GPU2
SH101 1 L1 2 SH102 1 L1 2
AB16
AB20 DVDD_MODEM3 DVDD_GPU3
L19
M20 SH103 1 L1 2 SH104 1 L1 2
must be close to BB's ball.
AC15 DVDD_MODEM4 DVDD_GPU4 N19
AC19 DVDD_MODEM5 DVDD_GPU5 P20 Remote sense trace with GND shielding to PMIC (Differential)
D
C105 1.0UF;20%;6.3V;0201 AD16 DVDD_MODEM6 DVDD_GPU6 R19 C106 1.0UF;20%;6.3V;0201
D
DVDD_MODEM7 DVDD_GPU7 T20
C107 1.0UF;20%;6.3V;0201 DVDD_GPU8 C108 1.0UF;20%;6.3V;0201
Note 10-2: Differential pair of DVDD_PROC remote sense
C109 1.0UF;20%;6.3V;0201 C110 1.0UF;20%;6.3V;0201 must be close to BB's ball
C111 1.0UF;20%;6.3V;0201 C112 1.0UF;20%;6.3V;0201
Remote sense trace with GND shielding to PMIC (Differential)
C113 1.0UF;20%;6.3V;0201 C114 1.0UF;20%;6.3V;0201
C115 1.0UF;20%;6.3V;0201 C116 1.0UF;20%;6.3V;0201

Note 10-3: Differential pair of DVDD_MODEM remote sense must be
close to BB's ball.
[2,7] DVDD_CORE
Remote sense trace with GND shielding to PMIC (Differential)
[8] DVDD_VSRAM_GPU_PMU
VCORE VGPU SRAM
C117 22uF;20%;6.3V;0603 H21 T18 C118 0.1uF;20%;6.3V;0201
J11 DVDD_CORE1 DVDD_SRAM_GPU Note 10-4: Differential pair of DVDD_CORE remote sense must be
DVDD_CORE2
C119 22uF;20%;6.3V;0603 J16
K12 DVDD_CORE3
C120 0.1uF;20%;6.3V;0201 close to BB's ball.
K16 DVDD_CORE4
L11 DVDD_CORE5 [7] DVDD_PROC_B Remote sense trace with GND shielding to PMIC (Differential)
L15 DVDD_CORE6
[7] DVDD_CORE_PMIC_FB Note: 10-4 M12 DVDD_CORE7
[7] DVDD_CORE_PMIC_GND DVDD_CORE8
M16 C121 10uF;20%;6.3V;0402
N11 DVDD_CORE9
N15 DVDD_CORE10 C122 22uF;20%;6.3V;0603
SH106 1 2L1 SH105 1 L1 2 P7 DVDD_CORE11
P12 DVDD_CORE12 C123 10uF;20%;6.3V;0402
P16 DVDD_CORE13
C124 1.0UF;20%;6.3V;0201 P21 DVDD_CORE14 VPROC1 Note: 10-2 DVDD_PROC_B_PMIC_FB [7]
R7 DVDD_CORE15 AA10
DVDD_CORE16 DVDD_PROC_B1 DVDD_PROC_B_PMIC_GND [7]
C125 1.0UF;20%;6.3V;0201 R8 AB9
R11 DVDD_CORE17 DVDD_PROC_B2 AC9
C126 1.0UF;20%;6.3V;0201 R15 DVDD_CORE18 DVDD_PROC_B3 AC10
DVDD_CORE19 DVDD_PROC_B4 L1
C T7 AC11 SH107 1 L1 2 SH108 1 2 C
C127 1.0UF;20%;6.3V;0201 T8 DVDD_CORE20 DVDD_PROC_B5 AD9
T12 DVDD_CORE21 DVDD_PROC_B6 AD10
C128 1.0UF;20%;6.3V;0201 T16 DVDD_CORE22 DVDD_PROC_B7 C129 1.0UF;20%;6.3V;0201
U15 DVDD_CORE23
C130 1.0UF;20%;6.3V;0201 U19 DVDD_CORE24 C131 1.0UF;20%;6.3V;0201
U21 DVDD_CORE25
V16 DVDD_CORE26 C132 1.0UF;20%;6.3V;0201
V20 DVDD_CORE27
W15 DVDD_CORE28 C133 1.0UF;20%;6.3V;0201
W19 DVDD_CORE29
Y16 DVDD_CORE30 C134 1.0UF;20%;6.3V;0201
Y20 DVDD_CORE31
AB7 DVDD_CORE32 C135 1.0UF;20%;6.3V;0201
AB22 DVDD_CORE33
AC22 DVDD_CORE34 C136 1.0UF;20%;6.3V;0201
AD7 DVDD_CORE35
DVDD_CORE36 C137 1.0UF;20%;6.3V;0201
C138 1.0UF;20%;6.3V;0201
[8] DVDD_SRAM_CORE [8] DVDD_SRAM_PROC_B

VCORE SRAM VPROC1 SRAM
J12 AC13 C139 0.1uF;20%;6.3V;0201
T11 DVDD_SRAM_CORE1 DVDD_SRAM_PROC_B
C140 0.1uF;20%;6.3V;0201 V21 DVDD_SRAM_CORE2 C141 0.1uF;20%;6.3V;0201
Y15 DVDD_SRAM_CORE3
C142 0.1uF;20%;6.3V;0201 AC14 DVDD_SRAM_CORE4
DVDD_SRAM_CORE5
[7] DVDD_PROC_L
B B
[7,8,17,18] EMI_VDD2 C143 22uF;20%;6.3V;0603
C144 22uF;20%;6.3V;0603
VDD2 VPROC2
G18 U7
AVDD2_EMI1 DVDD_PROC_L1 DVDD_PROC_L_PMIC_FB [7]
H11 U8 Note: 10-2 DVDD_PROC_L_PMIC_GND [7]
C145 22uF;20%;6.3V;0603 H13 AVDD2_EMI2 DVDD_PROC_L2 U9
H16 AVDD2_EMI3 DVDD_PROC_L3 U10
C146 10uF;20%;6.3V;0402 AVDD2_EMI4 DVDD_PROC_L4 W9
DVDD_PROC_L5 W11
DVDD_PROC_L6 SH109 1 L1 2 SH110 1 L1 2
C147 1.0UF;20%;6.3V;0201
C148 1.0UF;20%;6.3V;0201 C149 1.0UF;20%;6.3V;0201
C150 1.0UF;20%;6.3V;0201 C151 1.0UF;20%;6.3V;0201
C152 1.0UF;20%;6.3V;0201 C153 1.0UF;20%;6.3V;0201
C154 1.0UF;20%;6.3V;0201
C155 1.0UF;20%;6.3V;0201
C156 1.0UF;20%;6.3V;0201
[8,17,18] EMI_VDDQ
C163 1.0UF;20%;6.3V;0201
[8] DVDD_SRAM_PROC_L
VDDQ VPROC2 SRAM

C157 1.0UF;20%;6.3V;0201 G14 W7 C158 0.1uF;20%;6.3V;0201
G15 AVDDQ_EMI1 DVDD_SRAM_PROC_L
C159 1.0UF;20%;6.3V;0201 H10 AVDDQ_EMI2 C160 0.1uF;20%;6.3V;0201
A A
H12 AVDDQ_EMI3
C161 1.0UF;20%;6.3V;0201 H17 AVDDQ_EMI4
H19 AVDDQ_EMI5
C162 1.0UF;20%;6.3V;0201 AVDDQ_EMI6
Title REV: V10
01_BB_POWER_PDN
DOCUMENT NO.: Design Name Size C
DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI
Date: Thursday, May 30, 2019 Sheet 3 of 65
5 4 3 2 1
5 4 3 2 1
U101F
MT6771-DDR4 VA12_PMU [2,8]
MT6771-SBS C201
0.1uF;20%;6.3V;0201
GND AVDD Schematic design notice of "11_BB_POWER_IO" page.
A21 AH20
B9 DVSS1 AVDD12_MD
B13 DVSS2
B21 DVSS3
DVSS4 AVDD18_MD
AH19
AVDD18_SOC [2,8]
Note 11-1: C216 closed DVDD18_MSDC0 150mil
B23
D
B25 DVSS5
DVSS6 AVDD18_CPU
AC7
AVDD18_SOC [2,8]
C217 closed DVDD18_MSDC1 150mil D
C3
C6 DVSS7 AH21
DVSS8 AVDD18_AP AVDD18_SOC [2,8]
C10
C11 DVSS9
DVSS10 AVDD18_DDR
G9 EMI_VDD1 [15,17]
Note 11-2: C218 closed DVDD28_MSDC1 150mil
C18
C19 DVSS11
C24 DVSS12 C202 C203 C204 C205 C206
D3 DVSS13
DVSS14 0.1uF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
D12
D16 DVSS15
DVSS16
Note 11-3: Connects "AVDD09_SSUSB" to GND
D21
E2 DVSS17
DVSS18
PLL when USB3.0 is not used.
E3 AA13
DVSS19 AVDD12_PLLGP VA12_PMU [2,8]
E4
E14 DVSS20 AB13
E15 DVSS21
DVSS22
AVDD18_PLLGP AVDD18_SOC [2,8]
Note 11-4: Connects "AVDD09_UFS" to GND when UFS is not used.
E26
F3 DVSS23 C207 C208
F4 DVSS24
DVSS25 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 [2] VIO18_PMU_AP
F5
F9 DVSS26
F10 DVSS27
F11 DVSS28 PERI_D
F17 DVSS29 L2
F18 DVSS30 DVDD18_IORT AA1
F19 DVSS31 DVDD18_IORB
G3 DVSS32 W27 SH201 1 2
DVSS33 DVDD18_IOLM VIO18_PMU [3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84]
G4 M27
DVSS34 DVDD18_IOLT SINGLE-GND-L4
G5
G6 DVSS35 AJ21
G21 DVSS36 DVDD18_IOBL
H2 DVSS37
H24 DVSS38 C209 C210 C211 C212 C213 C214 C215
H25 DVSS39
DVSS40 NF_0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201
H26
J3 DVSS41
J8 DVSS42
C C
J10 DVSS43
J13 DVSS44 F24
DVSS45 DVDD_VQPS VEFUSE_PMU [8]
J17
J23 DVSS46
J26 DVSS47 E27
DVSS48 DVDD18_MSDC0 VIO18_PMU_AP [2]
K10
K14 DVSS49 AA27
DVSS50 DVDD18_MSDC1 VIO18_PMU_AP [2]
K18
K24 DVSS51 AB27
DVSS52 DVDD28_MSDC1 VMC_PMU [8]
K25
L1 DVSS53
L9 DVSS54 C216 C217 C218 C219
L13 DVSS55
L17 DVSS56 Note: 11-1 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
M5 DVSS57
M10 DVSS58
M14 DVSS59 Note: 11-2
M18 DVSS60 AG27
DVSS61 DVDD18_SIM VIO18_PMU_AP [2]
N9
N13 DVSS62 AF25
DVSS63 DVDD28_SIM1 VSIM1_PMU [8,45]
N17
N21 DVSS64 AE27
DVSS65 DVDD28_SIM2 VSIM2_PMU [8,45]
P10
P14 DVSS66
P18 DVSS67 C220 C221 C222
R9 DVSS68
DVSS69 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201
R13
R17 DVSS70
R26 DVSS71
T10 DVSS72 PERI_A
T14 DVSS73 V27
DVSS74 AVDD04_DSI DVDD_CORE [1,7]
T21
U5 DVSS75 V23
U13 DVSS76 AVDD12_DSI
U17 DVSS77
U23 DVSS78 W3
DVSS79 AVDD12_CSI VA12_PMU [2,8]
V5
B
V8 DVSS80 B
V9 DVSS81 C223 C224 C225
V10 DVSS82
DVSS83 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
V12
V14 DVSS84
V18 DVSS85
V26 DVSS86
W1 DVSS87 H22
DVSS88 AVDD12_USB VA12_PMU [2,8]
W12
W13 DVSS89 F27
DVSS90 AVDD18_USB AVDD18_SOC [2,8]
W17
W21 DVSS91 F25
DVSS92 AVDD33_USB VUSB_PMU [8]
Y8
Y9 DVSS93 K27
Y10 DVSS94 AVDD09_SSUSB
Y14 DVSS95 H23
DVSS96 AVDD18_SSUSB AVDD18_SOC [2,8]
Y18
AA12 DVSS97
AA17 DVSS98
AA21 DVSS99 Note: 11-3 C226 C227 C228 C229
AB8 DVSS100
DVSS101 0.1uF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
AB14
AB18 DVSS102
AB21 DVSS103
AC12 DVSS104
AC17 DVSS105
AD8 DVSS106
AE10 DVSS107 C2
DVSS108 AVDD12_WBG VA12_PMU [2,8]
AE14
AE15 DVSS109 B2
DVSS110 AVDD18_WBG AVDD18_SOC [2,8]
AE16
AF8 DVSS111
AF9 DVSS112 C230 C231
AF15 DVSS113
DVSS114 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201
AG8
AG9 DVSS115
AG15 DVSS116
AH8 DVSS117
A A
AH9 DVSS118 C22
AH15 DVSS119 AVDD09_UFS
AH18 DVSS120 C23
Note: 11-4
DVSS121 AVDD12_UFS VA12_PMU [2,8]
AJ9
DVSS122 Title REV: V10
AVDD18_UFS
D23 AVDD18_SOC [2,8] 02_BB_POWER_IO
5 4 3 2 1
5 4 3 2 1
VIO18_PMU U101A U101B

Note: 12-1 MT6771-DDR4 MT6771-DDR4
R301
MT6771-DDR4 MT6771-SBS
12K;5%;0201
PMU_IF SIM 26M
[9] SYSRSTB K23 [45] SIM1_SCLK AE23 AE17 PMIC_CLK_BB [11]
SYSRSTB AF24 SIM1_SCLK MAIN_X26M_IN
[45] SIM1_SIO SIM1_SIO
M23 AE22
[9] WATCHDOG WATCHDOG [45] SIM1_SRST SIM1_SRST
R302 PWRAP_SPI0_CSN AG24
[45] INT_SIM1 INT_SIM1
NF_12K;5%;0201
N23
[9] PWRAP_SPI0_CSN PWRAP_SPI0_CSN
[45] SIM2_SCLK
AD23 ABB_IF
P23 AE24 SIM2_SCLK AG11
[9] PWRAP_SPI0_CK PWRAP_SPI0_CK [45] SIM2_SIO SIM2_SIO TX_BB_IP1
AE25 AF11
61,62,67,70,84] VIO18_PMU [45] SIM2_SRST SIM2_SRST TX_BB_IN1
P25
D [9] PWRAP_SPI0_MO PWRAP_SPI0_MO AG25 D
[45] INT_SIM2 INT_SIM2
Note: 12-2 P24 AF12
[9] PWRAP_SPI0_MI PWRAP_SPI0_MI TX_BB_QP1 AG12
TX_BB_QN1
R303
NF_12K;5%;0201 M25 AF13
[10] AUD_CLK_MISO AUD_CLK_MISO RFI_C TX_BB_IP0 AG13
LTE_TX_BB_IP0
LTE_TX_BB_IN0
[58]
[58]
N24 AE21 TX_BB_IN0
AUD_DAT_MISO0 [10] AUD_DAT_MISO0 AUD_DAT_MISO0 [58] RFIC0_BSI_EN RFIC0_BSI_EN
L23 [58] RFIC0_BSI_CK AF21 AF14 LTE_TX_BB_QP0 [58]
AUD_DAT_MISO1 [10] AUD_DAT_MISO1 AUD_DAT_MISO1 RFIC0_BSI_CK TX_BB_QP0 AG14
TX_BB_QN0 LTE_TX_BB_QN0 [58]
M26 [41] REAR_CAM_DVDD_EN AG20
[10] AUD_SYNC_MISO AUD_SYNC_MISO RFIC0_BSI_D2
R304 R305 AE20 AF16
[58] RFIC0_BSI_D1 RFIC0_BSI_D1 PRX_BB_I1 LTE_PRX_BB_I1 [58]
12K;5%;0201 AJ16 LTE_PRX_BB_I0 [58]
M24 AF20 PRX_BB_I0
12K;5%;0201 [10] AUD_CLK_MOSI AUD_CLK_MOSI [58] RFIC0_BSI_D0 RFIC0_BSI_D0
[10] AUD_DAT_MOSI0 J22 AG16 LTE_PRX_BB_Q1 [58]
AUD_DAT_MOSI0 PRX_BB_Q1 AJ15
PRX_BB_Q0 LTE_PRX_BB_Q0 [58]
[10] AUD_DAT_MOSI1 N27
61,62,67,70,84] VIO18_PMU AUD_DAT_MOSI1
L26 AG17
[10] AUD_SYNC_MOSI AUD_SYNC_MOSI RF MIPI DRX_BB_I1 AH16
LTE_DRX_BB_I1
LTE_DRX_BB_I0
[58]
[58]
AD6 DRX_BB_I0
AE6 MISC_BSI_CK_3
R306 MISC_BSI_DO_3 AF17
DRX_BB_Q1 LTE_DRX_BB_Q1 [58]
NF_12K;5%;0201 AF6 AH17
[48,70] MIPI2_SCLK MISC_BSI_CK_2 DRX_BB_Q0 LTE_DRX_BB_Q0 [58]
[48,70] MIPI2_SDATA AG6
MISC_BSI_DO_2
AUD_DAT_MOSI0 AH7 AH12
[62] MIPI1_SCLK MISC_BSI_CK_1 DET_IP1
AG7 AH11
BC_IF [62] MIPI1_SDATA MISC_BSI_DO_1 DET_IN1
R307 [13] CHD_DP G25 [67] MIPI0_SCLK AJ7
CHD_DP AJ8 MISC_BSI_CK_0 AH10
12K;5%;0201 [67] MIPI0_SDATA MISC_BSI_DO_0 DET_QP1
[13] CHD_DM G24 AJ10
CHD_DM DET_QN1
C AJ13 C
SCP_IF BPI DET_IP0 AJ12
LTE_DET_BB_IP0
LTE_DET_BB_IN0
[58]
[58]
N25 AG4 DET_IN0
[11] SCP_VREQ_VAO SCP_VREQ_VAO BPI_PA_VM1
Note: 12-1 AH3 AH14
BPI_PA_VM0 DET_QP0 LTE_DET_BB_QP0 [58]
AH13
32K [69] BPI_ANT2
AJ25 DET_QN0 LTE_DET_BB_QN0 [58]
K26 BPI_ANT2
[11] RTC32K_CK RTC32K_CK AJ4 AE13
[73] BPI_ANT1 BPI_ANT1 APC APC1 [62]
AJ24
SRCLKEN [69] BPI_ANT0 BPI_ANT0
R24 [42] TORCH_EN AH26
[11,58] SRCLKENA1 SRCLKENA1 BPI_OLAT1
R23 AH4
[11] SRCLKENA0 SRCLKENA0 [40] BL_ISET_EN BPI_OLAT0
[72] BPI_BUS10
AJ22 ET
BPI_BUS10 AE11
SRCLKEN AI [13] EINT_CHG_0
AH22 RFIC_ET0_P AE12
W5 BPI_BUS9 RFIC_ET0_N
SRCLKENAI AJ26
[72] BPI_BUS8 BPI_BUS8
[72] BPI_BUS7 AH6
BPI_BUS7
PLLs Test Pin [40] GPIO_CTP_RSTB
AJ5
Y13 BPI_BUS6
TP_PLLGP1 AD5
[62] BPI_BUS5 BPI_BUS5
Y12
TN_PLLGP1 AE5
[62] BPI_BUS4 BPI_BUS4 AUX IN Note: 12-3
J15 [61] BPI_BUS3 AF5 AG18 HW_ID [6]
EMI_TP BPI_BUS3 AUXIN4
J14 [61] BPI_BUS2 AG5 AE18 BAT_ID [6,36]
EMI_TN BPI_BUS2 AUXIN3
AH5 AE19
[62] BPI_BUS1 BPI_BUS1 AUXIN2 AUX_IN2_NTC [6]
AF7
CDM3P5A AC6 AF18
[72] BPI_BUS0 BPI_BUS0 AUXIN1 AUX_IN1_NTC [67]
AE7
B CDM5P5A AF19 B
AUXIN0 AUX_IN0_NTC [6]
C305
C304
TEST MODE 1.0UF;20%;6.3V;0201
L24 1.0UF;20%;6.3V;0201
TESTMODE
C306 C301 C302
REF POWER
AJ18 REFP 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
NC REFP
A1
A27 NC1 C303
AJ1 NC2
NC3 0.1uF;20%;6.3V;0201
AJ27
NC4
Note: 12-4
Schematic design notice of "12_BB_1" page.
Note 12-1: "PWRAP_SPI0_CSN" and "AUD_DAT_MOSI0" are bootstrap pins to select which interface will be the JTAG pin out. Note 12-3: To shunt a 1uF capacitor in the AUXIN ADC input to prevent noise coupling. It should be placed
PWRAP_SPI0_CSN AUD_DAT_MOSI0 AP_JTAG IO_JTAG as close to BB as possible. Connect the unused AUX ADC input to GND.
HI LO N/A N/A
Note 12-4: The de-coupling cap. for REFP (AJ18 ball) have to be placed as close to BB as possible.
HI HI SPI_CSB/SPI_CLK/ N/A
SPI_MO/SPI_MI/EINT8
Note 12-5: AUD_SYNC_MISO and AUD_CLK_MISO are DDR type feature in bootstrap
LO SPI_CSB/SPI_CLK/
LO DPI_11/DPI_HSYNC/DPI_VSYNC/DPI_DE/
SPI_MO/SPI_MI/EINT8 DPI_CK/DPI_D8/DPI_D9 AUD_SYNC_MISO AUD_CLK_MISO DDR
LO LO LPDDR4X
A
MSDC1_CLK/CMD/ N/A A
LO HI DAT0/DAT1/DAT2 LO HI LPDDR4X(Ext x 2 EN)

HI LO LPDDR3
Note 12-2: "AUD_DAT_MISO0" is bootstrap pin to enable serial JTAG output over USB2.0 interface or not.
HI HI LPDDR4X(Ext x 1 EN)
When "AUD_DAT_MISO0" is pulled to high in system start up and then USB2.0 interface will be switched into serial JTAG mode.
Title REV: V10
"AUD_DAT_MISO1" is bootstrap pin to select system booting up from eMMC or UFS device. 03_BB_1_RF&SIM_IF
AUD_DAT_MISO1 Booting device DOCUMENT NO.: Design Name Size C
LO eMMC
HI UFS
5 4 3 2 1
5 4 3 2 1
U101C U101D
MT6771-DDR4 MT6771-DDR4
MT6771-SBS MT6771-SBS
CSI DSI USB 2.0 MSDCs
P4 U25 R421 0;0.5A;0201 G26 D25
[41] RDP2 CSI0A_L0P_T0A DSI0_CKP DSI0_CKP [40] [36,47,48] USB_DP USB_DP MSDC0_RSTB MSDC0_RSTB [18]
[41] RDN2 P3 U24 DSI0_CKN [40]
CSI0A_L0N_T0B DSI0_CKN R422 0;0.5A;0201 F26 C27
[36,47,48] USB_DM USB_DM MSDC0_CMD MSDC0_CMD [18]
R2 T25 D24
[41] RDP0 CSI0A_L1P_T0C DSI0_D3P DSI0_D3P [40] MSDC0_CLK MSDC0_CLK [18]
R1 T24 AF23 E25
[41] RDN0 CSI0A_L1N_T1A DSI0_D3N DSI0_D3N [40] [48] USB_ID IDDIG MSDC0_DSL MSDC0_DSL [18]
[32] CODEC_IRQ_N AF26 D26
D DRVBUS MSDC0_DAT7 MSDC0_DAT7 [18] D
P5 V25 G23
[41] RCP CSI0A_L2P_T1B DSI0_D2P DSI0_D2P [40] MSDC0_DAT6 MSDC0_DAT6 [18]
N5 V24 C25
[41] RCN CSI0A_L2N_T1C DSI0_D2N DSI0_D2N [40] MSDC0_DAT5 MSDC0_DAT5 [18]
C26
MSDC0_DAT4 MSDC0_DAT4 [18]
E24
R3 U26 A26
[41] RDP1 CSI0B_L0P_T0A DSI0_D1P DSI0_D1P [40] MSDC0_DAT2 MSDC0_DAT2 [18]
R4 T26 B27
[41] RDN1 CSI0B_L0N_T0B DSI0_D1N DSI0_D1N [40] MSDC0_DAT1 MSDC0_DAT1 [18]
B26
USB 3.0 MSDC0_DAT0 MSDC0_DAT0 [18]
T2 T27 J25
[41] RDP3 CSI0B_L1P_T0C DSI0_D0P DSI0_D0P [40] SSUSB_TXP
T1 R27 AC24
[41] RDN3 CSI0B_L1N_T1A DSI0_D0N DSI0_D0N [40] MSDC1_CLK MSDC1_CLK [45]
J24
SSUSB_TXN AD26
MSDC1_CMD MSDC1_CMD [45]
Note: 13-1 T3 AH23
CSI0B_L2P_T1B DISP_PWM DISP_PWM [40]
T4 AD27 MSDC1_DAT3 [45]
CSI0B_L2N_T1C AG26 H27 MSDC1_DAT3 AC23
DSI_TE DSI_TE [40] SSUSB_RXP MSDC1_DAT2 MSDC1_DAT2 [45]
AE26
R420 0;1A;0402 AA4 AH27 J27 AD24
[41] CAM_CLK0 CAM_CLK0 LCM_RST LCM_RST [40] SSUSB_RXN MSDC1_DAT0 MSDC1_DAT0 [45]
AA3
C421 CAM_RST0
W6
NF_18pF;5%;50V;0201
[41] CAM_PDN0 CAM_PDN0 KEYPAD WBG_IQ
AH1 B1
[47] HW_ID1 KPROW1 WF_IP WF_IP [77]
Note: 13-1 M2 C1
M1 CSI1A_L0P DPI AA5 WF_IN WF_IN [77]
CSI1A_L0N AC25 [43] FP_1V8_EN KPROW0 D1
DPI_CK HAC_EN [37] WF_QP WF_QP [77]
D2
WF_QN WF_QN [77]
M3 AC26 AE3
[41] RDP0_A CSI1A_L1P DPI_DE AMP1_IRQN [37] [40] SPI2_MI KPCOL1
[41] RDN0_A M4
CSI1A_L1N AA24 AC4 F2
DPI_VSYNC EINT_SD [45] [46] KPCOL0 KPCOL0 BT_IP BT_IP [77]
F1
BT_IN BT_IN [77]
N1 Y23
[41] RCP_A CSI1A_L2P DPI_HSYNC KPCOL2 [46]
N2 G1
[41] RCN_A CSI1A_L2N BT_QP BT_QP [77]
G2
AA23
SPI3_CODEC_CLK [32]
UART BT_QN BT_QN [77]
N3 DPI_D11 AD1
CSI1B_L0P [47] UTXD0 UTXD0
N4 AA26 J2
CSI1B_L0N DPI_D10 SPI3_CODEC_MOSI [32] GPS_I GPS_I [77]
AD2 J1
[47] URXD0 URXD0 GPS_Q GPS_Q [77]
U401 Y26 SPI3_CODEC_CSN [32]
P2 DPI_D9 R401 NF_2.2K;5%;0201
CSI2_LANE3_P_F [41] A3 A2
Note: 13-1 P1 CSI1B_L1P AB24
[2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU I2C CONN_IF
RDP3_B [4] SPI3_CODEC_MISO [32] R402 NF_2.2K;5%;0201
CSI2_LANE3_N_F [41] B3 CLKAP CLKP A1 CSI1B_L1N DPI_D8 AB6 J4
CLKAN CLKN RDN3_B [4] [40] SCL0 SCL0 CONN_TOP_CLK CONN_TOP_CLK [77]
Y24 AC5 J5
DPI_D7 SPI4_PA_CLK [37] [40] SDA0 SDA0 CONN_TOP_DATA CONN_TOP_DATA [77]
CSI2_CLK_P_F [41] A4 B2 RCP_B [4] R417 0;1A;0402 AC2 H3
B4 DA1P D1P B1 [41] CAM_CLK1 CAM_CLK1 CONN_HRST_B CONN_HRST_B [77]
CSI2_CLK_N_F [41] RCN_B [4] W24 R403 NF_2.2K;5%;0201
DA1N D1N DPI_D6 [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84]
SPI4_PA_MOSI [37] VIO18_PMU
AA2 R404 NF_2.2K;5%;0201
CSI2_LANE0_P_F [41] A5 C2 C422 CAM_RST1 AB23 AE4 H4
DA2P D2P RDP0_B [4] DPI_D5 SPI4_PA_CSN [37] [44] SCL1 SCL1 CONN_BT_CLK CONN_BT_CLK [77]
CSI2_LANE0_N_F [41] A6 C1 Y5 AF4 H5
DA2N D2N RDN0_B [4] CAM_PDN1 [44] SDA1 SDA1 CONN_BT_DATA CONN_BT_DATA [77]
NF_18pF;5%;50V;0201 AB26 SPI4_PA_MISO [37]
CSI2_LANE1_P_F [41] B5 D2 DPI_D4 R405 NF_2.2K;5%;0201
DA3P D3P RDP1_B [4] [4,8,41] VCAMIO_PMU
C CSI2_LANE1_N_F [41] B6 D1 U2 W26 R406 NF_2.2K;5%;0201 C
DA3N D3N RDN1_B [4] [4] RDP2_B CSI2A_L0P DPI_D3 CODEC_GPIO14 [32]
U1 AB2 K6
C5 E2 [4] RDN2_B CSI2A_L0N [41] SCL2 SCL2 CONN_WB_PTA CONN_WB_PTA [77]
CSI2_LANE2_P_F [41] RDP2_B [4] W25 AB1 H6
C6 DA4P D4P E1 DPI_D2 [41] SDA2 SDA2 CONN_WF_CTRL2 CONN_WF_CTRL2 [77]
CSI2_LANE2_N_F [41] RDN2_B [4] J7
DA4N D4N CONN_WF_CTRL1 CONN_WF_CTRL1 [77]
T5 AA25 R407 NF_2.2K;5%;0201 J6
[4] RDP0_B CSI2A_L1P DPI_D1 [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU CONN_WF_CTRL0 CONN_WF_CTRL0 [77]
R5 R408 NF_2.2K;5%;0201
[4] RDN0_B CSI2A_L1N W23 AF22 R22
1 DPI_D0 [37,84] SCL3 SCL3 ANT_SEL2 CAM_SWITCH_SEL [4]
AG22 T23
D6 TP402 [37,84] SDA3 SDA3 ANT_SEL1 CODEC_VDD_EN [32]
CSI2_LANE3_P_R [41] U4 P22
CLKBP [4] RCP_B CSI2A_L2P ANT_SEL0 GPIO_GPS_LNA_EN [79]
CSI2_LANE3_N_R [41] D5 U3 R410 NF_2.2K;5%;0201
CLKBN [4] RCN_B CSI2A_L2N [4,8,41] VCAMIO_PMU
R409 NF_2.2K;5%;0201
CSI2_CLK_P_R [41] E6 F1 Y2 H8
E5 DB1P /OE F2 [41] SCL4 SCL4 XIN_WBG XIN_WBG [77]
CSI2_CLK_N_R [41] CAM_SWITCH_SEL [4] V2 W2
DB1N SEL C3 [4] RDP1_B CSI2B_L0P [41] SDA4 SDA4
[4] RDN1_B V1
CSI2_LANE0_P_R [41] F6 NC C4 R415 0;0.5A;0201 CSI2B_L0N R411 NF_2.2K;5%;0201
CSI2_LANE0_N_R [41] F5 DP2P
DB2N
VCC
GND
D3
VCAMA_PMU [8,41]
AUD_IF [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU
R412 NF_2.2K;5%;0201
D4 V4 AG23 AH24
CSI2_LANE1_P_R [41] E4 NC1 R416 NF_0;0.5A;0201 RCAM_AVDD [41]
[4]
[4]
RDP3_B
RDN3_B
V3 CSI2B_L1P I2S1_BCK I2S3_CODEC_BCLK [32] [13,40,48]
[13,40,48]
SCL5
SDA5
AH25 SCL5 PWM
CSI2_LANE1_N_R [41] F4 DB3P C420 CSI2B_L1N AD21 SDA5 AA6
DB3N C419 I2S1_LRCK I2S3_CODEC_LRCLK [32] PWM_A
CSI2_LANE2_P_R [41] E3 R418 0;1A;0402 K4 AG21
F3 DB4P 1.0UF;20%;6.3V;0201 33pf;30%;50V;0201 [41] CAM_CLK2 CAM_CLK2 I2S1_DO I2S3_CODEC_SDO [32]
CSI2_LANE2_N_R [41] N26
DB4N L5 AG19 [43] EINT_FP_N P26 SCL6
[32] CLKM0 CAM_PDN2 I2S2_DI I2S0_CODEC_SDI [32] [48] CC_INT SDA6
C423
BCT644EWX-TR K5
NF_18pF;5%;50V;0201
[41] CAM_RST2 CAM_RST2 AD20
CODEC_RST_N [32]
PERI. EN GPIO
I2S1_MCK AA7 Y4
[42] FLASH_EN PERIPHERAL_EN14 EINT10 CODEC_GPIO11 [32]
AD19
[40] GPIO_LCM_LED_EN PERIPHERAL_EN13
AD22 W4 SAR_INT [84]
[47] HW_ID2 Y6 PERIPHERAL_EN12 EINT9
SPI [43]
[43]
FP_3V3_EN
GPIO_FP_RST_N
Y7 PERIPHERAL_EN11 AD4
JTRST [47]
R419 0;1A;0402 L4 AG3 PERIPHERAL_EN10 EINT8
[41] CAM_CLK3 CAM_CLK3 SPI_CSB SPI0_CSB [43]
V22 AE1
[41] REAR_CAM_AVDD_EN PERIPHERAL_EN9 EINT7 CODEC_GPIO12 [32]
[41] CAM_PDN3 L3 AF3 SPI0_CLK [43]
C424 CAM_PDN3 SPI_CLK K22 AE2
K3 AH2 [39] EAR_EINT PERIPHERAL_EN8 EINT6 EINT_CTP [40]
[41] CAM_RST3 CAM_RST3 SPI_MO SPI0_MO [43]
T22 AF2
NF_18pF;5%;50V;0201 [42] LED_EN PERIPHERAL_EN7 EINT5 EINT_ALPS [44]
AJ2
SPI_MI SPI0_MI [43]
N22 AC3
[41] CAM_DVDD_1P2_EN PERIPHERAL_EN6 EINT4 ACC_GYRO_INT1 [44]
AD25 AG1
[44] PSENSOR_3V3_EN PERIPHERAL_EN5 EINT3 CODEC_GPIO13 [32]
AB25
SPI1_CSB SCP_SPI_CSB [44]
Y25 AG2
[37] VIB_RST_N PERIPHERAL_EN4 EINT2 SPI2_CK [40]
AA22
SPI1_CLK SCP_SPI_CLK [44]
[37] SPK_AMP1_RST_N L22 AB4
PERIPHERAL_EN3 EINT1 SPI2_MO [40]
Y22
SPI1_MO SCP_SPI_MO [44]
M22 AB5
[13] EINT_CHG_CE PERIPHERAL_EN2 EINT0 SPI2_CS [40]
W22
SPI1_MI SCP_SPI_MI [44]
[40] ENN L25
PERIPHERAL_EN1
B R25 B
[40] ENP PERIPHERAL_EN0

Note 13-1: CSI ports which are no use could be connected to GND or set in NC.
For detail information, please refer to MT6771 Design Notice
A A
Title 04_BB_2_MIPI&GPIO REV: V10
DOCUMENT NO.: Design Name Size D
5 4 3 2 1
5 4 3 2 1
U101G
MT6771-DDR4
MT6771-SBS
EMI_IF EMI_IF
EMI1_DQ15 D14 C16 EMI1_CS1
[18] EMI1_DQ15 EMI1_DQ15 EMI1_CS1 EMI1_CS1 [18]
D EMI1_DQ14 B14 E17 EMI1_CS0 D
[18] EMI1_DQ14 EMI1_DQ14 EMI1_CS0 EMI1_CS0 [18]
EMI1_DQ13 A15
[18] EMI1_DQ13 EMI1_DQ13 A7 EMI0_CS1
EMI1_DQ12 EMI0_CS1 EMI0_CS1 [18]
C12
[18] EMI1_DQ12 EMI1_DQ12 D8 EMI0_CS0
EMI1_DQ11 EMI0_CS0 EMI0_CS0 [18]
D15
[18] EMI1_DQ11 EMI1_DQ11
EMI1_DQ10 A13
EMI1_DQ9 C14 E18 EMI1_CKE1
[18] EMI1_DQ9 EMI1_DQ9 EMI1_CKE1 EMI1_CKE1 [18]
EMI1_DQ8 C13 D18 EMI1_CKE0
[18] EMI1_DQ8 EMI1_DQ8 EMI1_CKE0 EMI1_CKE0 [18]
EMI1_DQ7 C21
[18] EMI1_DQ7 EMI1_DQ7 D7 EMI0_CKE1
EMI1_DQ6 EMI0_CKE1 EMI0_CKE1 [18]
A19
[18] EMI1_DQ6 EMI1_DQ6 E8 EMI0_CKE0
EMI1_DQ5 EMI0_CKE0 EMI0_CKE0 [18]
B19
EMI1_DQ4 C20
EMI1_DQ3 E19 B15 EMI1_DMI1
[18] EMI1_DQ3 EMI1_DQ3 EMI1_DMI1 EMI1_DMI1 [18]
EMI1_DQ2 D20 B18 EMI1_DMI0
[18] EMI1_DQ2 EMI1_DQ2 EMI1_DMI0 EMI1_DMI0 [18]
EMI1_DQ1 E20
[18] EMI1_DQ1 EMI1_DQ1 C8 EMI0_DMI1
EMI1_DQ0 EMI0_DMI1 EMI0_DMI1 [18]
F20
[18] EMI1_DQ0 EMI1_DQ0 B4 EMI0_DMI0
EMI0_DMI0 EMI0_DMI0 [18]
EMI1_CA5 D19 F13 EMI1_DQS1_C

[18] EMI1_CA5 EMI1_CA5 EMI1_DQS1_C EMI1_DQS1_C [18]
EMI1_CA4 C17 E13 EMI1_DQS1_T
[18] EMI1_CA4 EMI1_CA4 EMI1_DQS1_T EMI1_DQS1_T [18]
EMI1_CA3 A17 E21 EMI1_DQS0_C
C EMI1_CA2 EMI1_DQS0_T C
B17 F21
[18] EMI1_CA2 EMI1_CA2 EMI1_DQS0_T EMI1_DQS0_T [18]
EMI1_CA1 C15
[18] EMI1_CA1 EMI1_CA1
EMI1_CA0 D17 E12 EMI0_DQS1_C
F12 EMI0_DQS1_T
EMI0_DQ15 EMI0_DQS1_T EMI0_DQS1_T [18]
D11
[18] EMI0_DQ15 EMI0_DQ15 C4 EMI0_DQS0_C
EMI0_DQ14 EMI0_DQS0_C EMI0_DQS0_C [18]
C9
[18] EMI0_DQ14 EMI0_DQ14 D4 EMI0_DQS0_T
EMI0_DQ13 EMI0_DQS0_T EMI0_DQS0_T [18]
D9
EMI0_DQ12 A11
EMI0_DQ11 A9 F16 EMI1_CK_C
[18] EMI0_DQ11 EMI0_DQ11 EMI1_CK_C EMI1_CK_C [18]
EMI0_DQ10 B10 E16 EMI1_CK_T
[18] EMI0_DQ10 EMI0_DQ10 EMI1_CK_T EMI1_CK_T [18]
EMI0_DQ9 E11
[18] EMI0_DQ9 EMI0_DQ9 E10 EMI0_CK_C
EMI0_DQ8 EMI0_CK_C EMI0_CK_C [18]
B11
[18] EMI0_DQ8 EMI0_DQ8 D10 EMI0_CK_T
EMI0_DQ7 EMI0_CK_T EMI0_CK_T [18]
A3
EMI0_DQ6 A5
EMI0_DQ5 C5
[18] EMI0_DQ5 EMI0_DQ5 D22 EMI_RESET_N
EMI0_DQ4 EMI_RESET_N EMI_RESET_N [18]
B3
EMI0_DQ3 D6
EMI0_DQ2 E6
EMI0_DQ1 D5
B EMI0_DQ0 E5 B
EMI0_CA5 E7 UFS_IF
[18] EMI0_CA5 EMI0_CA5 F23
EMI0_CA4 B7 UFS_CKIN_26M
[18] EMI0_CA4 EMI0_CA4
EMI0_CA3 B6
[18] EMI0_CA3 EMI0_CA3 B24
EMI0_CA2 B5 UFS_TX0_P A24
[18] EMI0_CA2 EMI0_CA2 UFS_TX0_N
EMI0_CA1 C7
[18] EMI0_CA1 EMI0_CA1 A22
EMI0_CA0 E9 UFS_RX0_RXP B22
[18] EMI0_CA0 EMI0_CA0 UFS_RX0_RXN
E22
UFS_RST_N
R501 EMI_EXTR
2 1 EMI_EXTR A2
EMI_EXTR
60.4;1%;0201
Note: 14-1
A A
Title REV: V10

10_BB_ POWER_PDN
The resistor of EMI_EXTR for DRAM has to be placed near to BB as close as possible DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI
Note 14-1: R501, please select 60.4 ohm 1% resistor

5 4 3 2 1
5 4 3 2 1
D D
[2,3,4,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU
FOR BOADR ID 2
R601 R602 R605
390K;1%;0201 390K;1%;0201 NF_390K;1%;0201
R603
NF_10K;5%;0201
BAT_ID [3,36]
2
[3] HW_ID RT602 R604
RT601 100K;1%;0402 0;0.5A;0201
100K;1%;0402
RT603
1
BOADR ID 1 0;0.5A;0201
1. IF used for battery ID,R604 NC,R605=390K

Thermistor to sense charger Thermistor to sense AP
2. IF unused ,R604=0 R,R605 NC
C temperature temperature C
1. RT602must keep a distance about 6~8 mm away from AP and far from
other heat sources 10 mm at least.
AUX_IN2_NTC 2. The distance is the shortest distance from package edge to edge.
[3] AUX_IN2_NTC
AUX_IN0_NTC
[3] AUX_IN0_NTC
B B
A A
Title REV: V10

06_BB_AUXADC_Thermal
5 4 3 2 1
5 4 3 2 1
U701A
U / MT6358W / A_1
MT6358
R701 VBUCK CTRL
VSYS_SMPS E2
[8,9,13,15,32,37,40,41,42,43,44,48] VSYS VSYS_SMPS
1;5%;0201 C702
SG701
1.0UF;20%;6.3V;0201
L701£º
D
1 2 GND_SMPS E1
GND_SMPS
MT6771L ±¥ºÍµçÁ÷5.3A D
MT6771T ±¥ºÍµçÁ÷5.7A
SINGLE-GND-L4
L701
VPROC11 IN VPROC11 L close to chip
A6 A7 VPROC11 0.8V 5000mA DVDD_PROC_B [1]
B6 VSYS_VPROC11_1 VPROC11_1 B7
VSYS_VPROC11_2 VPROC11_2 0.47uH;20%;2016
C701 differential and shielding
SG702 A8 D6 4mil
10uF;20%;6.3V;0402 GND_VPROC11-1 VPROC11_FB DVDD_PROC_B_PMIC_FB [1] C712
1 2 GND_VPROC11 B8
GND_VPROC11_2 D7 4mil NF_10uF;20%;6.3V;0402
GND_VPROC11_FB DVDD_PROC_B_PMIC_GND [1]
SINGLE-GND-L4
L702 803401000931
VPROC12 IN VPROC12 L close to chip
A10 B9 VPROC12 0.8V 5000mA DVDD_PROC_L [1]
B10 VSYS_VPROC12_1 VPROC12_1 A9
VSYS_VPROC12_2 VPROC12_2 0.47UH;20%;2016
SG703
10uF;20%;6.3V;0402 D8 E9 4mil
GND_VPROC12 GND_VPROC12_1 VPROC12_FB DVDD_PROC_L_PMIC_FB [1]
1 2 D9
GND_VPROC12_2 D10 4mil
GND_VPROC12_FB DVDD_PROC_L_PMIC_GND [1]
SINGLE-GND-L4
VCORE IN VCORE L703

A15 A14 VCORE
B15 VSYS_VCORE_1 VCORE_1 B14
L close to chip 0.8V 5000mA DVDD_CORE [1,2]
VSYS_VCORE_2 VCORE_2
C704 0.47uH;20%;2016
SG704
10uF;20%;6.3V;0402 B13
1 2 GND_VCORE A13 GND_VCORE_1 differential and shielding
GND_VCORE_2 C16 4mil
VCORE_FB DVDD_CORE_PMIC_FB [1]
SINGLE-GND-L4 B16 4mil
GND_VCORE_FB DVDD_CORE_PMIC_GND [1]
C C
L704
VMODEM IN VMODEM L close to chip
F14 F15 VMODEM 0.8V 3250mA DVDD_MODEM [1]
VSYS_VMODEM VMODEM_1 F16 1.0UH;20%;2016
VMODEM_2
SG705 D15 4mil
4.7uF;20%;6.3V;0402 VMODEM_FB DVDD_MODEM_PMIC_FB [1]
1 2 GND_VMODEM G15
G16 GND_VMODEM_1 E14 4mil
GND_VMODEM_2 GND_VMODEM_FB DVDD_MODEM_PMIC_GND [1]
SINGLE-GND-L4
L705
VPA IN VPA L close to chip
A5 A4 VPA 0.5V 1000mA VPA_PMU [67]
VSYS_VPA VPA 1.0UH;20%;2016
C706 D5 C707
SG706 VPA_FB
10uF;20%;6.3V;0402 B4 2.2uF;20%;6.3V;0402
1 2 GND_VPA GND_VPA
Note: 20-1
SINGLE-GND-L4
close to VPA Inductor
VS1 IN VS1 PMIC feedback cap.
L706 Total cap. = 1uF+6.2uF
B1 A2 VS1
C1 VSYS_VS1_1 VS1_1 B2
L close to chip 2V 2000mA VS1_PMU [7,8,15]
VSYS_VS1_2 VS1_2
C708 1.0uH;20%;2016
SG707
4.7uF;20%;6.3V;0402 A3
1 2 GND_VS1 B3 GND_VS1_1
GND_VS1_2 E7
B VS1_FB VS1_PMU VS1
[7,8,15] sense to Cap B
SINGLE-GND-L4
VS2 IN VS2
L707
L15 VS2
K15 VS2_1 L16
L close to chip 1.35V 2000mA VS2_PMU [7,8,32,41]
K16 VSYS_VS2_1 VS2_2
VSYS_VS2_2 1.0uH;20%;2016
C709
SG708 L14
4.7uF;20%;6.3V;0402 GND_VS2
1 2 GND_VS2 D16 VS2 sense to Cap
VS2_FB VS2_PMU [7,8,32,41]
SINGLE-GND-L4
VGPU IN VGPU L708
B12 VGPU L close to chip
VGPU_1 A12 0.8V 5000mA DVDD_GPU [1]
A11 VGPU_2
B11 VSYS_VGPU_1 0.47UH;20%;2016
VSYS_VGPU_2
SG709
10uF;20%;6.3V;0402 D12 D14 4mil
GND_VGPU GND_VGPU_1 VGPU_FB DVDD_GPU_PMIC_FB [1]
1 2 D13
GND_VGPU_2 C15 4mil
GND_VGPU_FB DVDD_GPU_PMIC_GND [1]
SINGLE-GND-L4
L709
VDRAM1 VDRAM1 L close to chip
J15 VDRAM1 1.125V/1.225V 2000mA EMI_VDD2 [1,8,17,18]
J16 VDRAM1
VSYS_VDRAM1 1.0uH;20%;2016
H15 differential and shielding C713

C711
SG710 GND_VDRAM1 NF_10uF;20%;6.3V;0402
A 4.7uF;20%;6.3V;0402 D11 4mil
EMI_VDD2_FB [17] A
1 2 GND_VDRAM1 VDRAM1_FB
E12 4mil
EMI_VDD2_GND [17]
GND_VDRAM1_FB
SINGLE-GND-L4
All Buck Input Cap close to chip Title
07_POWER_MT6358-Buck REV: V10
Schematic design notice of "20_POWER_MT6358-Buck" page.

Note 20-1: Please select C707 with 0402 size
5 4 3 2 1
5 4 3 2 1
1. "Typical Cap" defined in design notice is the minimum cap. to LDO Cout.
U701B
2. NC cap can move to application, if (PCB L<20nH, PCB R<0.2 ohm)
U / MT6358W / A_1 => value and placement of Cap, please refer design notice
MT6358 Close to PMIC

LDO IN LDO
R7 2.8V 50mA
VFE28 VFE28_PMU [48,67]
P6 2.24V 50mA
P7 VXO22 VXO22_PMU
8,9,13,15,32,37,40,41,42,43,44,48] VSYS VSYS_LDO1 2.8V 50mA
R6
D VCN28 VCN28_PMU [77,79] D
P9
8,9,13,15,32,37,40,41,42,43,44,48] VSYS VSYS_LDO2
NF_1.0UF;20%;6.3V;0201
M10 1.8/2.5/2.7/2.8/2.9/3.0V 200mA
NF_1.0UF;20%;6.3V;0201
VCAMA1 VCAMA_PMU [4,41]
8,9,13,15,32,37,40,41,42,43,44,48] VSYS N11
VSYS_LDO3 M6 1.8V 50mA
VAUX18 VAUX18_PMU [11]
R5 2.8V 50mA
VAUD28 VAUD28_PMU [10]
C801 C802 C803
M9 2.8V 50mA
2.2uF;20%;6.3V;0201 2.2uF;20%;6.3V;0201 2.2uF;20%;6.3V;0201 ALDO VBIF28 VBIF28_PMU [9]
N10 1.8/2.5/2.7/2.8/2.9/3.0V 200mA
VCAMA2 VCAMA2_PMU [41]
C837 C838
C804 C805 C806 C807 C808 C809
1.0UF;20%;6.3V;0201 2.2uF;20%;6.3V;0402 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
[7,15] VS1_PMU E4 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
VS1_LDO1 N12 3.3/3.4/3.5/3.6V 800mA
VCN33 VCN33_PMU [77]
C846
P8 2.8/3.0V 400mA
10uF;20%;6.3V;0402 VLDO28 VLDO28_PMU [41]
C810 C845 C812
22uF;20%;6.3V;0603 10uF;20%;6.3V;0402 4.7uF;20%;6.3V;0402 N9 2.8V 200mA
VIO28 VIO28_PMU [44,84]
R9 1.86/2.9/3.0/3.3V 200mA
VMC VMC_PMU [2]
R10 2.9/3.0/3.3V 800mA
VMCH VMCH_PMU [45]
[1,7,17,18] EMI_VDD2 R15
VS2_LDO1 R11 2.9/3.0/3.3V 800mA
VEMC VEMC_PMU [17]
NF_1.0UF;20%;6.3V;0201
NF_1.0UF;20%;6.3V;0201
NF_1.0UF;20%;6.3V;0201
C813 N7 1.7/1.8/1.86/2.76/3.0/3.1V 200mA
VSIM1 VSIM1_PMU [2,45]
2.2uF;20%;6.3V;0402
P10 1.7/1.8/1.86/2.76/3.0/3.1V 200mA
VSIM2 VSIM2_PMU [2,45]
P11 1.2/1.3/1.5/1.8/2.0/2.8/3.0/3.3V 200mA
VIBR
N8 3.07V 200mA
VUSB VUSB_PMU [2]
N14
[7,32,41] VS2_PMU VS2_LDO2 DLDO
P13 C844 C815 C816 C817 C818 C819 C820 C839 C840 C841
VS2_LDO3 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
C C
C821 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
22uF;20%;6.3V;0603
F5 1.81V 450mA
VRF18 VRF18_PMU [58]
E3 1.71/1.8V/1.84V 300mA
VEFUSE VEFUSE_PMU [2]
All LDO Input Cap close to chip M14
VS2_LDO4 F6 1.8V 300mA
VCN18 VCN18_PMU [77]
NF_1.0UF;20%;6.3V;0201
VS2_LDO4
Connect to VS2 If VCAMD < 1.2V, VCAMD = 1.2V E6 1.8V 300mA
Connect to VS1 If VCAMD > 1.2V VCAMIO VCAMIO_PMU [4,41]
F3 1.8V 700mA
VIO18 VIO18_PMU [2,3,4,6,8,10,13,15,17,32,37,39
SH801 SINGLE-GND-L8
F7 C822 C823 C824 C825 C842 1 2
F8 D_GND1 AVDD18_SOC [2]
4.7uF;20%;6.3V;0402 1.0UF;20%;6.3V;0201
F9 D_GND2 1.0UF;20%;6.3V;0201 4.7uF;20%;6.3V;0402
G7 D_GND3 SLDO1
G8 D_GND4
G9 D_GND5 P16
Note: 21-1
H7 D_GND6 VRF12_S
H8 D_GND7 N15 1.2V 800mA
H9 D_GND8 VRF12 VRF12_PMU [58]
D_GND9 N16 1.2V 300mA
VA12 VA12_PMU [2]
P12 0.6~1.2(0.9)V 600mA
VSRAM_PROC11 DVDD_SRAM_PROC_B [1]
P14 0.55~1.2(0.9)V 600mA
VSRAM_OTHERS DVDD_SRAM_CORE [1]
R14 0.65~1.2(0.9)V 600mA
VREF
VREF VSRAM_GPU DVDD_VSRAM_GPU_PMU [1]
Close to IC
M12
C826 VREF R13 0.6~1.2(0.9)V 600mA
B SG801 VSRAM_PROC12 DVDD_SRAM_PROC_L [1] B
0.1uF;20%;6.3V;0201
1 2 GND_VREF N13 P15 0.6/1.8V 600/100mA
GND_VREF VDRAM2 EMI_VDDQ [1,17,18]
M15 0.9/1.0/1.05/1.1/1.2/1.3/1.5/1.8V 600mA
SINGLE-GND-L4 VCAMD VCAMD_PMU [41]
DIG Power SLDO2

7,48,58,61,62,67,70,84] VIO18_PMU L9
DVDD18_IO C827 C843 C828 C829 C830 C831 C832 C833
1.8V 10mA DVDD18_DIG J8 1.0UF;20%;6.3V;0201 2.2uF;20%;6.3V;0402 2.2uF;20%;6.3V;0402 2.2uF;20%;6.3V;0402
DVDD18_DIG DVDD18_DIG 22uF;20%;6.3V;0603 2.2uF;20%;6.3V;0402 2.2uF;20%;6.3V;0402 4.7uF;20%;6.3V;0402
L8
DVSS18_IO
C834 C835 C836 Note: 21-2
1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201 0.1uF;20%;6.3V;0201
SG802
1 2 DVSS18_IO
SINGLE-GND-L4
A A
Schematic design notice of "21_POWER_MT6358-LDO" page.
Note 21-1: Please set SH801 close to C825, making star connection between VIO18_PMU and AVDD18_SOC near to LDO cap. C825 Title
08_POWER_MT6358-LDO REV: V10
Please also refer to MT6358 design notice for further detail design information DOCUMENT NO.: Design Name Size C

Note 21-2: If these power trace can meet LDO layout constraint, these CAP can be NC or removed.
Please refer to MT6358 design notice.
5 4 3 2 1
5 4 3 2 1
D U701C D
MT6358
Control I/F Control I/F
[3] SYSRSTB D4 D2 PWRKEY D901 2 1 LRB521CS-30T5G PWRKEY_SW [13,46]
RESETB PWRKEY short to GND
[3] WATCHDOG F12 G13 if disable
WDTRSTB_IN HOMEKEY
J13 HOMEKEY
SD_CARD_DET_N_PMU
SD_CARD_DET_N SD_CARD_DET_N_PMU [45]
PMIC SPI TEST SD Detect pin for VMCH power off
[3] PWRAP_SPI0_CSN F13 L6

SPI_CSN FSOURCE
[3] PWRAP_SPI0_CK F11
SPI_CLK E8
G11 PMU_TESTMODE
[3] PWRAP_SPI0_MO SPI_MOSI
G10
[3] PWRAP_SPI0_MI SPI_MISO
Note: 22-1
PMIC CFG EXT PMIC EN
R901
UVLO_VTH M13 D3
UVLO_VTH EXT_PMIC_EN1
A1
200K;1%;0201 A16 NC1 E5
R1 NC2 EXT_PMIC_EN2
R16 NC3
NC4
C C
U / MT6358W / A_1
U701E
Cap close to chip

MT6358
Charger I/F Gauge
differential
[7,8,13,15,32,37,40,41,42,43,44,48] VSYS M11 N6
VSYSSNS CS_P CS_P [36]
M5 Fuel Gauge CS_N [36]
C901 CS_N
1.0UF;20%;6.3V;0201 L13 BATADC Battery Voltage BATADC [36]
BATADC
BATON L12
[8] VBIF28_PMU R902 24K;1%;0201 BATON
VCDT K12
R906 VCDT
1K;5%;0201
[36,47] BATON_CONN
Width =4mils, total Length<3000mils CHRLDO K13
CHRLDO C902
1.0UF;20%;6.3V;0201
[9,13,48] VBUS R903 330K;1%;0201
[9,13,48] VBUS R905 7.5K;1%;0201

R904 U / MT6358W / A_1
39K;1%;0201 Cap close to chip
C903
B B
1.0UF;20%;6.3V;0201
VCDT rating: 1.268V
A A
Schematic design notice of "22_POWER_MT6358-General"

Title
09_POWER_MT6358-General REV: V10
Note 22-1: EXT_PMIC_EN1 : For UFS_1V8, and keep floating if it is not used DOCUMENT NO.: Design Name Size C
EXT_PMIC_EN2 : For VA09 of SSUSB/UFS, and keep floating if it is not used
5 4 3 2 1
5 4 3 2 1
MT6358 HW trapping for DRAM U701D R1099 0;0.5A;0201

[10] AU_MICBIAS0 MICBIAS1A [32,48]
MT6358 R1098 0;0.5A;0201

MICBIAS1B [32,38]
AUD_CLK_MISO
AUDIO IF UL POWER
R1001 20mil
VAUD28_PMU [8]
12K;5%;0201
H10 J3
[3] AUD_CLK_MISO AUD_CLK_MISO AVDD28_AUD C1001 AVSS28_AUD [39] SH1001
J11 1.0UF;20%;6.3V;0201
[3] AUD_DAT_MISO0 AUD_DAT_MISO0 20mil
H11 J5
D [3] AUD_DAT_MISO1 AUD_DAT_MISO1 AVSS28_AUD D
J10 C1002 C1003
[3] AUD_SYNC_MISO AUD_SYNC_MISO
1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
K5
AU_MICBIAS0 AU_MICBIAS0 [10]
R1002 L11
[3] AUD_CLK_MOSI AUD_CLK_MOSI
12K;5%;0201 L5
AU_MICBIAS1 AU_MICBIAS1 [39]
[3] AUD_DAT_MOSI0 J9
AUD_DAT_MOSI0
[3] AUD_DAT_MOSI1 L10
AUD_DAT_MOSI1
[3] AUD_SYNC_MOSI
K10
AUD_SYNC_MOSI
Close to Chip
AUDIO INPUT
For P-N pair: differential pair & GND shielding!
K1
[38] AU_VIN0_P AU_VIN0_P CHARGE PUMP
[38] AU_VIN0_N L1 VIO18_PMU [2,3,4,6,8,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84]
AU_VIN0_N 20mil
H2 C1004
L4 AVDD18_AUD SH1002
[39] AU_VIN1_P AU_VIN1_P 2.2uF;20%;6.3V;0402
1 L1 2
L3 H1
[39] AU_VIN1_N AU_VIN1_N AVSS18_AUD
For P-N pair: differential pair & GND shielding! C1005
F1 4.7uF;20%;6.3V;0402
K4 AU_V18N
[38] AU_VIN2_P AU_VIN2_P
K3
1. AVSS18_AUD is connected to GND with
[38] AU_VIN2_N AU_VIN2_N very short trace
G2
FLYP
C C
R1003 R0201_NC
R1004 R0201_NC
F2
C1006 2. AVSS18_AUD is connected to de-couple
4.7uF;20%;6.3V;0402
G1001
G1002
ACCDET
FLYN cap of AVDD18_AUD and AU_V18N with 6mil
trace respectively
[39] ACCDET K6
ACCDET
Close to Chip
J4
[39] HP_EINT HP_EINT
-AU_HPL and AU_HPR should be routed as single end signal

and be guarded by GND, up and down, left and right respectively
-The suggested layout pattern of AU_HPL/ AU_HPR/ AU_REFN AUDIO OUTPUT
is " GND AU_HPL AU_REFN AU_HPR GND"
H4
[39] AU_HPL AU_HPL
H5
[39] AU_REFN AU_REFN
G4
[39] AU_HPR AU_HPR
G5
AU_LOLP
C1007 G6
AU_LOLN
1000pF;20%;50V;0201
J6
[37] AU_HSP AU_HSP
H6
[37] AU_HSN AU_HSN
B
Close to Chip B
U / MT6358W / A_1
Schematic design notice of "23_POWER_MT6358-Audio"

Note 23-1: VDRAM 2 / VDRAM1 output voltage vs. trap pin.
HW GPIO configuration Trapping Option VDRAM2 Power source

DRAM type
AUD_SYNC_MISO AUD_CLK_MISO VDRAM1 VDRAM2 (VS2_LDO1_ball)
0 0 1.125V 0.6V LP4X VDRAM1

0 1 OFF 1.8V LP4X (Ext x 2 EN) VS1
A A
1 0 1.225V OFF LP3 VDRAM1 Title REV: V10

10_POWER_MT6358-Audio
1 1 1.125V 1.8V LP4X (Ext x 1 EN) VS1 DOCUMENT NO.: Design Name Size C
5 4 3 2 1
5 4 3 2 1
U701G
R1107
1 2
MT6358 0;1A;0402
VAUX18_PMU [8]
AUXADC
Cap close to chip
M3
AVDD18_AUXADC
C1101
1.0UF;20%;6.3V;0201
M4
AVSS18_AUXADC SG1101
D D
1 2
differential Route AVDD18_AUXADC/AUXADC_VIN with 3mil trace
C1102 width and with well GND shielding.
0.1uF;20%;6.3V;0201
AVDD18_AUXADC/AUXADC_VIN need to be shielded with
M2
AUXADC_VIN GND or AVSS18_AUXADC.
AVSS18_AUXADC 15mil trace width
AUXADC_VIN 3mil trace width
AVDD18_AUXADC 3mil trace width
differential
differential
Y1101
R1101 100K;5%;0201
4 3
SENSOR HOT2 XTAL2 3mil trace width
DCXO XTAL1 1 2
HOT1 GND
N1 XTAL1 3mil trace width AVSS18_AUXADC

XTAL1 26MHz
P1 XTAL2 3mil trace width

XTAL2
C C
R2
AVSS22_XOBUF
Please connect DCXO GND to main
P2
GND by independent L12 GND via.
AVSS22_XO DON'T connect it through L1 GND
N2
AVSS22_XO_ISO
U / MT6358W / A_1
U701F
MT6358
CLK CTRL DCXO CLKOUT
L7 P4 XO_SOC R1102 0;0.5A;0201

[3] SRCLKENA0 SRCLKEN_IN0 XO_SOC PMIC_CLK_BB [3]
J7
[3,58] SRCLKENA1 SRCLKEN_IN1 XO_CEL
R3 R1103 0;0.5A;0201 PMIC_CLK_RF [58]
XO_CEL
P3 XO_WCN R1104 0;0.5A;0201

XO_WCN PMIC_CLK_WCN [77]
N4
Sensor Hub XO_NFC
P5
H13 XO_EXT
B [3] SCP_VREQ_VAO SCP_VREQ_VAO B
C1103 C1104 C1105

C0201_NC C0201_NC C0201_NC
U / MT6358W / A_1
VRTC28 2.8V 2mA U701H
R1106
1.5K;5%;0201 C1107
MT6358
0.1uF;20%;6.3V;0201 RTC
M8
C1108 VRTC28
2.2uF;20%;6.3V;0402
TP1101
1
RTC CLKOUT
12x15MIL
F10
[3] RTC32K_CK RTC32K_1V8_0
G12
RTC32K_1V8_1
M7
RTC32K_2V8
U / MT6358W / A_1
A A
Title REV: V10

11_POWER_MT6358_Clock
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title REV: V10

12_POWER_MT6370-General
5 4 3 2 1
5 4 3 2 1
D D
C1301
L1301
2.2uF;20%;16V;0402 U1301 1.0uH;20%;2520
1 19
24 VAC SW1 20 VSYS [7,8,9,15,32,37,40,41,42,43,44,48]
[9,48] VBUS VBUS SW2 C1306 C1307 C1308
0.047uF;20%;16V;0201 10uF;20%;6.3V;0402 10uF;20%;6.3V;0402
C1302 10uF;20%;16V;0603 23 21
PMID BTST
10 22 REGN
NC1 REGN
C1305 4.7uF;20%;6.3V;0402
3 17
[3] CHD_DM PG GND1
4 18
[42] WHITE_LED STAT GND2
R1301 10K;5%;0201
6 15
[4,40,48] SDA5 SDA SYS1
[2,3,4,6,8,10,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU 5 16
[4,40,48] SCL5 SCL SYS2
C [3] EINT_CHG_0 7 C
8 INT 13
NC BAT1 VBAT [36,47,67]
[4] EINT_CHG_CE 9 14
CE BAT2
C1304
R1303 51K;5%;0201
11 REGN 10uF;20%;6.3V;0402
TS
gnd-pad4
gnd-pad3
gnd-pad2
gnd-pad1
12 R1304 0;0.5A;0201
QON PWRKEY_SW [9,46]
2
[3] CHD_DP PSEL
BQ25601
R1302
28
27
26
25
51K;5%;0201
B B
A A
Title 13_POWER_MT6370-Charger + PP REV: V10
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Schematic design notice of "27_POWER_SubPMIC-HV powers" page. Title 14_POWER_MT6370-HV powers REV: V10
Note 27-1: It is recommended to reserve 0-ohm and cap. for BOM fine tune to minimize RF de-sense. DOCUMENT NO.: Design Name Size C

Note 27-2: It is recommended to reserve 0-ohm for BOM fine tune to minimize RF de-sense.
5 4 3 2 1
5 4 3 2 1
D D
LDO for EMI_VDD1 of LPDDR4 VDD1

R1502
[7,8,9,13,32,37,40,41,42,43,44,48] VSYS
NF_0;0.5A;0201
R1501
[7,8] VS1_PMU 20 mil U1502 R1505
0;0.5A;0201 VIO18_PMU [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84]
4 1 NF_0;0.5A;0201
C C1507 VIN VOUT C
1.0UF;20%;6.3V;0201 2 20 mil
3 GND1 5 1.8V 20 mil
EMI_VDD1 [2,17]
EN NC
[2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU ETA5053V180DF1E

C1509
1.0UF;20%;6.3V;0201
B B
A A
Title REV: V10

15_POWER_ThirdParty_Powers
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title REV: V10

16_BB_ POWER_PDN
5 4 3 2 1
5 4 3 2 1
Note: 44-3 eMMC_VDDi
U1701B
C1717 C1716
D D
KMDD60018M-B320 1.0UF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 U1701F
KMDD60018M-B320
BLOCKID
Close to Memory
GND BLOCKID
PWR
K13 G13
VSSM_1 VSS_18
K14 G15 L17 A4

VDDI VDD1_1 EMI_VDD1 [2,15]
VSSM_2 VSS_19
K16 H4 Note: 44-3 A9

VDD1_2 C1722 C1723 C1724 C1725
VSSM_3 VSS_20
0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 2.2uF;20%;6.3V;0402 2.2uF;20%;6.3V;0402
L12 H7 M17 A15
[8] VEMC_PMU VCC_1 VDD1_3
VSSM_4 VSS_21 Note: 44-1
L15 H13 N17 A16
C1719 C1718 C1701 VCC_2 VDD1_4
VSSM_5 VSS_22
4.7UF;10%;10V;0402 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201
L16 H15 P17 B15
VSSM_6 VSS_23 VCC_3 VDD1_5
M8 J6 AC15
VSSM_7 VSS_24 VDD1_6
M13 K4 J15 AD4

[2,3,4,6,8,10,13,15,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU VCCQ_1 VDD1_7
VSSM_8 VSS_25
M14 K7 J16 AD9

C1702 C1721 C1720 VCCQ_2 VDD1_8
VSSM_9 VSS_26
2.2uF;20%;6.3V;0402 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201
N8 K8 J17 AD15
VSSM_10 VSS_27 VCCQ_3 VDD1_9
N12 R4 K15 AD16

N15 R7 R13
VSSM_12 VSS_29 VCCQ_5
N16 R8 R14 A5 Note: 44-4 EMI_VDD2 [1,7,8,18]

P13 T6 T15 A8
C1703 C1704 C1705 C1706 C1707 C1708 C1726 C1727
P14 U4 T16 B9
1.0UF;20%;6.3V;0201
1.0UF;20%;6.3V;0201
1.0UF;20%;6.3V;0201
1.0UF;20%;6.3V;0201
1.0UF;20%;6.3V;0201
1.0UF;20%;6.3V;0201
1.0UF;20%;6.3V;0201
1.0UF;20%;6.3V;0201
VSSM_15 VSS_32 VCCQ_8 VDD2_3 C1709
SH1701
22uF;20%;6.3V;0603
R15 U7 B13
VDD2_4 1 L1 2
C VSSM_16 VSS_33 EMI_VDD2_FB [7] C
R16 U13 [1,8,18] EMI_VDDQ

Note: 44-4 A6 B14
VSSM_17 VSS_34 VDDQ_1 VDD2_5
R17 U15 A7 G7
VSSM_18 VSS_35 VDDQ_2 VDD2_6 SH1702
C1733 C1732 C1731 C1730 C1729 C1728
V4 A13 G8 1 L1 2
1.0UF;20%;6.3V;0201
1.0UF;20%;6.3V;0201
1.0UF;20%;6.3V;0201
1.0UF;20%;6.3V;0201
1.0UF;20%;6.3V;0201
1.0UF;20%;6.3V;0201
VDDQ_3 VDD2_7 EMI_VDD2_GND [7]
VSS_36
V5 A14 G9
VSS_37 VDDQ_4 VDD2_8
B4 V6 B5 K2
VSS_1 VSS_38 VDDQ_5 VDD2_9
B6 V13 H5 L7
B8 V15 H9 L8
C4 W14 J4 L9
C5 Y14 J5 P7
C7 AA4 J8 P8
C14 AA6 T4 P9
D4 AA8 T5 R2
D6 AA14 T8 V7
D8 AA15 U5 V8
D14 AB4 U9 V9
D15 AB5 AC5 AC9

E14 AB7 AD6 AC13

F14 AB14 AD7 AC14

G4 AC4 AD13 AD5

G5 AC6 AD14 AD8

B B
G6 AC8
VSS_17 VSS_54
Schematic design notice of "44_Memory_eMMC_LPDDR4X"

Note 44-1: Please refer to power supply related page select VDRAM 2 / VDRAM1
output voltage properly for LPDDR4X
Note 44-2: DRAM ZQx resistor = 240ohm (1%) that must be connected to VDDQ,
Note 44-3: Please refer to eMCP vendor's datasheet or MTK common design notice to get the
recommendation bypass cap. value for VCC/VCCQ/VDDI power domains of eMMC.
Note 44-4: VDD2 VDDQ decoupling cap: closed to DRAM ball.

For other cap for PMIC [>10uF, at PMIC page]:
please also refer to MMD and layout guide for placement.
A A
Title 17_Memory_LPDDR4_POWER REV: V10
5 4 3 2 1
5 4 3 2 1
U1701C
KMDD60018M-B320
U1701D
KMDD60018M-B320
BLOCKID
LPDDR4_A BLOCKID U1701A
KMDD60018M-B320
LPDDR4_B
[5] EMI_RESET_N AA16
RST_N_2
Note: 44-2 Y15 BLOCKID
[5] EMI1_CS0 CS0_B
240;1%;0201 2 1
R1802 B16 W15 AD3 EMMC
[1,8,17,18] EMI_VDDQ ZQ0_A [5] EMI1_CS1 CS1_B DQ0_B EMI1_DQ0 [5]
240;1%;0201 2 1
R1801 C16 U14 AC3
ZQ1_A NC_9 DQ1_B EMI1_DQ1 [5]
N9
AB3 [4] MSDC0_RSTB RST_N_1
D DQ2_B EMI1_DQ2 [5] D
E15 U16 AA3

[5] EMI0_CS0 CS0_A [5] EMI1_CK_T CLK_T_B DQ3_B EMI1_DQ3 [5]
M9
F15 A3 V16 AC7 [4] MSDC0_CMD CMD
[5] EMI0_CS1 CS1_A DQ0_A EMI0_DQ0 [5] [5] EMI1_CK_C CLK_C_B DQ4_B EMI1_DQ4 [5]
H14 B3 AB6
NC_7 DQ1_A EMI0_DQ1 [5] DQ5_B EMI1_DQ5 [5]
P12
C3 Y16 AA7 [4] MSDC0_CLK CLKM
DQ2_A EMI0_DQ2 [5] [5] EMI1_CKE0 CKE0_B DQ6_B EMI1_DQ6 [5]
H16 D3 W16 AB8

[5] EMI0_CK_T CLK_T_A DQ3_A EMI0_DQ3 [5] [5] EMI1_CKE1 CKE1_B DQ7_B EMI1_DQ7 [5]
M12
G16 B7 T14 R5 [4] MSDC0_DSL DS
[5] EMI0_CK_C CLK_C_A DQ4_A EMI0_DQ4 [5] NC_10 DQ8_B EMI1_DQ8 [5]
C6 R6
DQ5_A EMI0_DQ5 [5] DQ9_B EMI1_DQ9 [5]
E16 D7 T13 R3
[5] EMI0_CKE0 CKE0_A DQ6_A EMI0_DQ6 [5] [1,7,8,17,18] EMI_VDD2 ODT_B DQ10_B EMI1_DQ10 [5]
P16
F16 C8 T3 [4] MSDC0_DAT0 DAT0
[5] EMI0_CKE1 CKE1_A DQ7_A EMI0_DQ7 [5] DQ11_B EMI1_DQ11 [5]
M15
J14 K5 AB9 T7 [4] MSDC0_DAT1 DAT1
NC_8 DQ8_A EMI0_DQ8 [5] [5] EMI1_DQS0_T DQS0_T_B DQ12_B EMI1_DQ12 [5]
N13
K6 R9 V3 [4] MSDC0_DAT2 DAT2
DQ9_A EMI0_DQ9 [5] [5] EMI1_DQS1_T DQS1_T_B DQ13_B EMI1_DQ13 [5]
P15
J13 K3 U6 [4] MSDC0_DAT3 DAT3
[1,7,8,17,18] EMI_VDD2 ODT_A DQ10_A EMI0_DQ10 [5] DQ14_B EMI1_DQ14 [5]
M16
J3 AA9 U8 [4] MSDC0_DAT4 DAT4
DQ11_A EMI0_DQ11 [5] [5] EMI1_DQS0_C DQS0_C_B DQ15_B EMI1_DQ15 [5]
N14
C9 J7 T9 [4] MSDC0_DAT5 DAT5
[5] EMI0_DQS0_T DQS0_T_A DQ12_A EMI0_DQ12 [5] [5] EMI1_DQS1_C DQS1_C_B
L14
K9 G3 [4] MSDC0_DAT6 DAT6
[5] EMI0_DQS1_T DQS1_T_A DQ13_A EMI0_DQ13 [5]
L13
H6 V14 [4] MSDC0_DAT7 DAT7
DQ14_A EMI0_DQ14 [5] [5] EMI1_CA0 CA0_B
D9 H8 W13
[5] EMI0_DQS0_C DQS0_C_A DQ15_A EMI0_DQ15 [5] [5] EMI1_CA1 CA1_B
J9 AB13
[5] EMI0_DQS1_C DQS1_C_A [5] EMI1_CA2 CA2_B
AA13
[5] EMI1_CA3 CA3_B
G14 Y13
C [5] EMI0_CA0 CA0_A [5] EMI1_CA4 CA4_B C
F13 AB15
[5] EMI0_CA1 CA1_A [5] EMI1_CA5 CA5_B
C13
[5] EMI0_CA2 CA2_A
D13 AA5
[5] EMI0_CA3 CA3_A [5] EMI1_DMI0 DMI0_B
E13 U3
[5] EMI0_CA4 CA4_A [5] EMI1_DMI1 DMI1_B
C15
[5] EMI0_CA5 CA5_A
D5
[5] EMI0_DMI0 DMI0_A
H3
[5] EMI0_DMI1 DMI1_A
U1701E
KMDD60018M-B320
BLOCKID
B NC_DNU B
M3 A1
VSF1 DNU_1
N3
VSF2 DNU_2
A2 Schematic design notice of "44_Memory_eMMC_LPDDR4X"
M4 A17
VSF3 DNU_3
Note 44-1: Please refer to power supply related page select VDRAM 2 / VDRAM1
N4
VSF4 DNU_4
A18
output voltage properly for LPDDR4X
M5 B1
VSF5 DNU_5
N5 B18 Note 44-2: DRAM ZQx resistor = 240ohm (1%) that must be connected to VDDQ,
VSF6 DNU_6
M6 AC1
VSF7 DNU_7
N6 AC18 Note 44-3: Please refer to eMCP vendor's datasheet or MTK common design notice to get the
VSF8 DNU_8
M7 AD1
recommendation bypass cap. value for VCC/VCCQ/VDDI power domains of eMMC.
VSF9 DNU_9
AD2
DNU_10 Note 44-4: VDD2 VDDQ decoupling cap: closed to DRAM ball.
[1,8,17,18] EMI_VDDQ
1
R1803 2 NF_240;1%;0201 D16
NC_1 DNU_11
AD17 For other cap for PMIC [>10uF, at PMIC page]:
Reserved for DRAM with K17 AD18
please also refer to MMD and layout guide for placement.
NC_2 DNU_12
3-die integrated. N7
NC_3
T17
NC_4
AB16
NC_5
AC16
NC_6
A A
Title 18_Memory_eMMC_LPDDR4 REV: V10
5 4 3 2 1
5 4 3 2 1
[32] VDD_CODEC_1P2
SG3201
1
SG3203
U3201 SINGLE-GND-L4 GND_CP [32]
SINGLE-GND-L4
C3201
C3204 1.0UF;20%;6.3V;0201
C3203
D E8 B1 D
2
VDD_FLL VREF_FILT
1.0UF;20%;6.3V;0201 C3202 2.2uF;20%;6.3V;0402 SG3202
1.0UF;20%;6.3V;0201 D1 A4
VDD_D GND_A1 2 1
H6 A8
VDD_D1 GND_CP
B7
GND_CP1
[2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU G6 E1
GND_D2 GND_D SINGLE-GND-L4
G3
GND_D1
B8 A1
VDD_CP GND_SUB
A2
GND_SUB1 C0201_NC C0201_NC C0201_NC
A3 D8 C0201_NC
1.0UF;20%;6.3V;0201 VDD_A GND_SUB2
C3205 C3206 C3216 C3218 C3219
H3 C3217
C3208 VDD_IO
1.0UF;20%;6.3V;0201 0.1uF;20%;6.3V;0201
G4
[32] GND_CP /S/P/I/1/_/S/S SPI3_CODEC_CSN [4]
E4 VIO18_PMU [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84]
SPI1_SCK SPI3_CODEC_CLK [4] R3206
F4 R3207
SPI1_MOSI SPI3_CODEC_MOSI [4]
[38] AU_VIN2_P_CS A6 H4
IN1LP_2 SPI1_MISO SPI3_CODEC_MISO [4]
C3212 1.0UF;20%;6.3V;0201
[38] AU_VIN2_N_CS B2 100K;5%;0201 100K;5%;0201
C3213 IN1LP_1/IN1_PDMDATA
D2
1.0UF;20%;6.3V;0201 SPI2_SS/GPIO11 CODEC_GPIO11 [4]
B5 E2
IN1LN_2 SPI2_SCK/GPIO12 CODEC_GPIO12 [4]
G1
SPI2_SIO0/GPIO13 CODEC_GPIO13 [4] CODEC_IRQ_N [4]
B3 F1
IN1LN_1/IN1_PDMCLK SPI2_SIO1/GPIO14 CODEC_GPIO14 [3]
[39] MIC_IN2_P_CON D3 1
C3221 1.0UF;20%;6.3V;0201 SPI2_SIO2/GPIO15 TP3202 1 CODEC_RST_N [4]
H2 TP3203
SPI2_SIO3/GPIO16
[39] MIC_IN2_M_CON R3208 10;5%;0201 CLKM0 [4]
C3222
1.0UF;20%;6.3V;0201
E7
/I/R/Q/
C4 D5
IN1RP_2 /R/E/S/E/T/ C3224
[38,48] MIC_IN1_P_CON G8
C3210 1.0UF;20%;6.3V;0201 MCLK1
A5 E6 SYNC_PA [37] 12pF;2%;50V;0201
IN1RP_1/IN2_PDMDATA GPIO1 1
[38,48] MIC_IN1_M_CON F7 TP3201
C3220 GPIO2
1.0UF;20%;6.3V;0201 C5
IN1RN_2
I2S3_CODEC_BCLK [4]
B4 I2S3_CODEC_LRCLK [4]
IN1RN_1/IN2_PDMCLK
E5 I2S3_CODEC_SDO [4]
ASP1_BCLK/GPIO5
F6 I2S0_CODEC_SDI [4]
ASP1_FSYNC/GPIO6
H7
ASP1_DIN/GPIO4
G7
NF_0;0.5A;0201
NF_0;0.5A;0201
NF_0;0.5A;0201
NF_0;0.5A;0201
ASP1_DOUT/GPIO3
C7
R3201
R3202
R3203
R3204
CP_FLYP
C3215
D7
0.47uF;10%;10V;0402 CP_FLYN
D4
[32] GND_CP C3207 ASP2_BCLK/GPIO9
C8 F5
4.7uF;20%;6.3V;0402 CP_FILT ASP2_FSYNC/GPIO10
H5 AMP_BCLK2 [37]
ASP2_DIN/GPIO8
G5 AMP_WS2 [37]
ASP2_DOUT/GPIO7
AMP_SDO2 [37]
AMP_SDI2 [37]
C [10,48] MICBIAS1A C
D6 F3
MICBIAS1A AUXPDM1_CLK
C6 E3
MICBIAS1B AUXPDM1_DOUT
B6 F2
[10,38] MICBIAS1B MICBIAS1C AUXPDM2_CLK
NC2
NC1
NC3
NC4
NC5
A7 G2
NC
VOUT_MIC AUXPDM2_DOUT
CS48L33
C1
C3
C2
F8
H1
H8
C3223
4.7uF;20%;6.3V;0402
[7,8,41] VS2_PMU
C3209 1.2V LDO

1.0UF;20%;6.3V;0201 U3203
VSYS [7,8,9,13,15,37,40,41,42,43,44,48] 4
IN
CODEC_VDD_EN [4] 3 1 VDD_CODEC_1P2 [32]
EN OUT
2
GND
BIAS
C3211
C3214
1
SGM2038-1.2XUDY4G/TR
5
0.1uF;20%;6.3V;0201
1.0UF;20%;6.3V;0201
B TP3209 B
A A
Title 32.CODEC_Cirrus REV: V10
DOCUMENT NO.: 98860_1_12M13_201905302120 Size D
DEPARTMENT: DEPARTMENT DESIGNER: DESIGNER
5 4 3 2 1
5 4 3 2 1
D D
BATTERY
CONNECTOR [4,36,47,48]
[4,36,47,48]
USB_DM
USB_DP
TVS3604 TVS3605
USB_DM
USB_DP
[4,36,47,48]
[4,36,47,48]
1
N1
N1
SH3605 1 2 BATADC [9]
N2
N2
2
2
SINGLE-GND-L4
NF_PSED5V0H1BSF NF_PSED5V0H1BSF
Close to battery connector
C C
VBAT [13,47,67]
C3632
1
AZ3105-01F.R7G
C3629 C3630
10uF;20%;6.3V;0402
TVS3602 1.0UF;20%;6.3V;0201 33pf;30%;50V;0201
2
J3601
1 P+ P+ 8
2 7 2 R3601 1
BATON_CONN_THERM TH+ ID BAT_ID [3,6]
[9,36,47] SG3611 HT-COPPER GND
1 2 3 6 NF_0;0.5A;0201
TH ID
R3699
4 5
P P VBAT_GND [3,6]
0.01;1%;0805
SG3601 SG3602 5050060810
1 R3602 2
BATON_SUB
NF_0;0.5A;0201
R3603
1 2
[9,36,47] BATON_CONN_THERM BATON_CONN [9,36,47]
CS_N [9]
0;0.5A;0201
2
CS_P [9]
TVS3603
N2
PESD3V3V1BCSF
N1
1
Battery pack is considered not present if BAT_ON is above 0.944*TREF
B B
A A
Title 36_Battery/USB IF REV: V10

5 4 3 2 1
5 4 3 2 1
J3710
D ANT_PAD-4PIN D
1 [7,8,9,13,15,32,37,40,41,42,43,44,48] VSYS HAPTIC DRIVER

Receiver 2
3
4 C3785
C3781
0.1uF;20%;6.3V;0201
33pf;30%;50V;0201 AW8624 U3703
J3701 C2
VDD
ANT_PAD-4PIN B2
[4] VIB_RST_N NRST VSW_HAP_P [48]
DRV2624
A3 R3713 0;1A;0402
C3704 OUT+
A1
100pF;2%;50V;0201 1 J3702 TRIG/INTZ
2
3 ANT_PAD-4PIN SDA3 [4,84] B1
AU_HSP [10] R3720 0;1A;0402 4 SDA C3 R3714 0;1A;0402 VSW_HAP_M [48]
SCL3 [4,84] C1 OUT-
SCL
1
2 A2 C3783 C3784
GND
3 REG
4 NF_33pf;30%;50V;0201 NF_33pf;30%;50V;0201
AU_HSN [10] R3721 0;1A;0402
BGA9-DRV2624
B3
R3781
100K;1%;0201 C3782
0.1uF;20%;6.3V;0201
TVS3709 TVS3710
2
C3702 C3703
N2
N2
33pf;30%;50V;0201 33pf;30%;50V;0201
N1
N1
2
NF_PESD3V3V1BCSF
NF_PESD3V3V1BCSF
1
1
SG3711
SG3712
main GND SINGLE-GND-L4
SINGLE-GND-L4
1
C C
AUDIO PA
SMART PA/CIRRUSLOGIC/CS35L41/I2C Address Write 0X80 Read 0x81 AD1=0 AD0=0
[2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU
C3726
[7,8,9,13,15,32,37,40,41,42,43,44,48] VSYS
1.0UF;20%;6.3V;0201
HAC [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU GND
F5
U3701
A5
L3702
TP3704 TP3705 TP3706 TP3707 VA VP

R3766 1.0UH;20%;2016
1 2
GND C3708 C3727
100K;5%;0201 1.0UF;20%;6.3V;0201 10uF;20%;6.3V;0402
R3703
1
VSYS [7,8,9,13,15,32,37,40,41,42,43,44,48] E5
[4,37] SPI4_PA_MISO I2C_SCL/SPI_MISO
10K;1%;0201
[4,37] SPI4_PA_MOSI E3
C3730 E4 I2C_SDA/SPI_MOSI A2
B
[4,37] SPI4_PA_CSN I2C_AD0/SPI_SS SW1
D4 B2 B
[4,37] SPI4_PA_CLK
A2
1.0uF;20%;6.3V;0201 I2C_AD1/SPI_SCLK SW2

U3702
1 R37080;1A;0402
2 A1 SMARTPA_I2S_DI B4 A1
C3725 0.033uF;10%;6.3V;0201 [32] AMP_SDI2 ASP_DOUT VBST1
VDD
INP [32] AMP_SDO2 SMARTPA_I2S_DO C4 B1

SMARTPA_I2S_LRCK C5 ASP_DIN/ VBST2
C3731 1 R37090;1A;0402
0.033uF;10%;6.3V;0201 2 C1 A3 1 R37160;1A;0603
2 C3729 [32] AMP_WS2 ASP_FSYNC
INN VOP L3701 SMARTPA_I2S_BCK B5 C3715
[32] AMP_BCLK2 ASP_BCLK C3714 C3716 C3717 C3788
C2 C3 1 2 33pF;5%;50V;0201 680uH;20%;3012
[4] HAC_EN CTRL VON 2.2uF;20%;16V;0402
F4 B3 10uF;20%;16V;0603
R3717 0;1A;0603 0.1uF;20%;25V;0201 10uF;20%;16V;0603
C3732 C3728 [4] AMP1_IRQN SMART_PA_INT INT/GPIO2 GNDB
803200000381 GNDB
A4 2.2uF;20%;16V;0402
2
AGND1
E2 A3
AGND
PGND
C3799 680pF;20%;25V;0201 680pF;20%;25V;0201 [4] SPK_AMP1_RST_N SMART_PA_RSTN RESET GNDB

NF_0.1uF;20%;6.3V;0201 C3724 SG3704 G3702
NF_1000pF;20%;50V;0201 C1 2 1
VSPK1 D1
B1
B2
B3
AW8155AFCR D5 VSPK2 Place SG2703 on cap

LDO_FILT+ E1 HT-COPPER
VSNS- SPK1_N_FB [48]
C3719 F1 SPK1_P_FB [48]
TP3715 VSNS+
0.47UF;20%;6.3V;0201 D2 R3711 0;1A;0603
G3703 G3704 OUT+ 32mil SPK_OUT_P1 [48]
F2 C2 R3712 0;1A;0603
GNDA OUT- 32mil SPK_OUT_N1 [48]
C3
1
F3 GNDP D3
[32] SYNC_PA SYNC/GPIO1 GNDP C3722 C3723
2
SG3709 NF_220PF;10%;25V;0201 NF_220PF;10%;25V;0201
AW8155 FOR HAC
2
CS35L41 SG3706
<470PF
HT-COPPER
1
HT-COPPER
2
SG3708
HT-COPPER
1
[4,37] SPI4_PA_MISO
C8432
NF
A
[4,37] SPI4_PA_MOSI
[4,37]
For SPI test
SPI4_PA_CSN
SPK/Receiver/Vibrator A
C8435
NF
[4,37] SPI4_PA_CLK
Title 37_SPK/Receiver/Vibrator REV: V10

5 4 3 2 1
5 4 3 2 1
D D
MAIN MIC
main GND
[32,48] MIC_IN1_P_CON C3821 1.0UF;20%;6.3V;0201AU_VIN0_P [10]
C3813
33pf;30%;50V;0201
[32,48] MIC_IN1_M_CON C3812 1.0UF;20%;6.3V;0201AU_VIN0_N [10]

Close to PMIC
68pF;30%;50V;0201
C3818 C3802
68pF;30%;50V;0201 TO CODEC
2
SG3803
SINGLE-GND-L4
C C
1
main GND
TOP MIC
1 R3829 2
MICBIAS1B [10,32]
0;1A;0402
C3801 0.1uF;20%;6.3V;0201
C3822 33pf;30%;50V;0201 AU_VIN2_P_CS [32]

B B
AU_VIN2_N_CS [32]
1
U3801
VDD
3 Close to BB C3809 1.0UF;20%;6.3V;0201 [10] AU_VIN2_P

GND
OUT
SPV0842LR5H-1
C3808
2
100pF;30%;50V;0201
C3810 1.0UF;20%;6.3V;0201
[10] AU_VIN2_N
1
C3803 C3804
D3801
N1
C0201_NC C0201_NC
NF_PESD3V3V1BCSF
1
N2
R3828
0;0.5A;0201
2
2
main GND
2
SG3804
2
SINGLE-GND-L4
SG3801
1
SINGLE-GND-L4
1
A A
Title 38_MIC REV: V10

5 4 3 2 1
5 4 3 2 1
D D
[2,3,4,6,8,10,13,15,17,32,37,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU
1
R3908 4mil
NF_470K;5%;0201
10mil J3901
2
HP_MP3L L3902 1000OHM;250mA;0402 HS_L_CON
HS_MIC_IN_CON 1
Earphone [39]
[39]
EAR_OUT_L
EAR_OUT_R
4mil
L3905 1000OHM;250mA;0402 HS_R_CON
CONN_FM_ANT 2
GND/MIC+
MIC+/GND
DETECT/L_AUDIO
5
4
HS_DET_CON
HS_L_CON
HS_R_CON
3 L_AUDIO/DETECT
R3901 R_AUDIO
AU_HPL
[10] AU_HPL EAR_OUT_L [39] L3907 1800ohm;100mA;0402 HS_MIC_IN_CON
0;1A;0402 [39] AU_VIN1_P_MIC
TEST
R3902 R3906 47K;5%;0201 HS_DET_CON PH92-7B22C41M
AU_HPR
[10] AU_HPR
0;1A;0402
EAR_OUT_R [39] [10] HP_EINT
C3920
10mil 10mil LRGM
1
Earphone UL GND TVS3905
C <= 1pF
C3913 C3914 C3950 LESD9L5.0T5G
0.1uF;20%;6.3V;0201
2
33pF;5%;50V;0201 NF_33pF;5%;50V;0201
33pF;5%;50V;0201 C3917
C3916
2
R3907 NF_47K;5%;0201
C3908 C3907 [4] EAR_EINT
main GND
1000pF;20%;50V;0201 SG3910
33pF;5%;50V;0201
C0201_NC C0201_NC main SINGLE-GND-L4
GND
1
SG3907
SINGLE-GND-L4
main GND TVS3903
2
2
TVS3901
2
TVS3904
N2
N2
SG3905 TVS3902
2
PESD3V3V1BCSF
N2
SINGLE-GND-L4
N2
N1
N1
1
N1
C
main GND C
N1
PTVS4V5D1BL
1
GND
2
1
PTVS4V5D1BL main GNDSG3909
1
PTVS4V5D1BL
SINGLE-GND-L4
GND
1
GND
GND GND
GND
Close to PMIC [10] AU_MICBIAS1

SH3966
Need SMT ESD5651
1 L1 2 C3988 SG3902 Close to audio jack for AU_HPL/R/MIC
[32] MIC_IN2_P_CON
1 2
GND
SH3967
1 L1 2 SINGLE-GND-L4
[32] MIC_IN2_M_CON C0201_NC
R3903
1K;5%;0201
C3919
4 mil L3903 1800ohm;100mA;0402
[10] AU_REFN
C3905 1.0UF;20%;6.3V;0201 EAR_MIC_N
[10] AU_VIN1_N AU_VIN1_N_MIC [39]
C3903
C0201_NC
SG3901
R3905 4.7uF;20%;6.3V;0402 C3918
10 milC3915 1000pF;10%;25V;0201 RF_FM_ANT_WCN [77]
GND 33pF;5%;50V;0201
C3904 2 1
33pf;30%;50V;0201
C3909
SINGLE-GND-L4
1.5K;5%;0201
C0201_NC L3906
C3906 1.0UF;20%;6.3V;0201 EAR_MIC_P
[10] AU_VIN1_P AU_VIN1_P_MIC [39] 600ohm;700mA;0603
Connecting the GNDs C3910

to WCN ROUTE AS differential pair
together and then to main C0201_NC SG3903
GND through signle via [10] AVSS28_AUD 1 2
AU_VIN1_N_MIC [39]
R3904
HT-COPPER
2
[10] ACCDET
SG3906 main GND
1
0;0.5A;0201
SINGLE-GND-L4
C3901
0;0.5A;0201
1
SG3904
2
B B
1 2 FM_ANT_N [77]
HT-COPPER
Ear Jack @ Ear Jack @

Main board Sub board
C3901 0ohm 100nF
A A
Title 39_Earphone REV: V10

5 4 3 2 1
Schematic design notice of "62_PERI_AUDIO_IO" page.

Note 621: Part # of BEAD6202, BEAD6203, BEAD6204 and BEAD6205 needs changed to
"BLM18BD102SN1" for high THD performance (90dB) but this BOM change will
results in FM RSSI 10dB degraded .
Note 622: Reserved Cap for CS/RS test, please double check multikey function when used
Note 623: Earphone Jack Earphone Jack

@ Main board @ Sub board
R6513 0 ohm 100nF
Note 624: Please Select ACC Mode for Operator Project to Pass Electrical MOS Test;
More Information refer to Audio/Speech Design Notice
Note 625: Please select R6231 with 0402 size

5 4 3 2 1
,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU IOVCC _LCD_1.8V VIO18_PMU [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84]
C4001
1.0UF;20%;6.3V;0201
Common Mode Filter

D D
1 2
R0201_NC
R4005
MIPI_DSI1_LANE3_P_CON [40] 1 4 [4] DSI0_D3P
ICMF052P900MFR
MIPI_DSI1_LANE3_N_CON [40] 2 3 [4] DSI0_D3N
EMI4001
R4001 1 2
1 2 R0201_NC
[4] DSI_TE LCD_TE_CONN [40]
1K;5%;0201 D4003
LCDConnector R4002
2
N2
1 2
R0201_NC
J4001 R4008
N1
1 40 ICMF052P900MFR
2 39 MIPI_DSI1_LANE2_P_CON [40] 1 4 [4] DSI0_D2P
NF_PESD3V3V1BCSF
[4] SPI2_CK
1
3 38 MIPI_DSI1_LANE3_N_CON [40] EMI4002
[4] SPI2_MO 4 37 MIPI_DSI1_LANE3_P_CON [40] 1 2
R4006
1 2 [4] SPI2_MI 5 36 R0201_NC
[40] LCD_CABC_CON LCD_CABC [40] [4] SPI2_CS MIPI_DSI1_LANE0_N_CON [40] R4007
6 35
R4009
1K;5%;0201 MIPI_DSI1_LANE0_P_CON [40]
1 2 7 34
[4] LCM_RST LCD_RST_CONN [40] [3,40] GPIO_CTP_RSTB 8 33 1 2
1K;5%;0201 [4,40] SDA0 MIPI_DSI1_CLK_N_CON [40] R0201_NC
[40] LCM_AVEE 9 32 R4011
LCM_AVEE [40] [4,40] SCL0 MIPI_DSI1_CLK_P_CON [40]
10 31 MIPI_DSI1_CLK_P_CON [40] 1 4 [4] DSI0_CKP
[40] EINT_CTP_CON 11 30
[40] LCM_AVDD LCM_AVDD [40] ICMF052P900MFR
12 29 MIPI_DSI1_LANE1_N_CON [40] MIPI_DSI1_CLK_N_CON [40] 2 3 [4] DSI0_CKN
[40] LCM_LEDK_2 13 28 MIPI_DSI1_LANE1_P_CON [40]
EMI4003
[40] LCM_LEDK_1 14 27 1 2
[40] LCM_LEDA 15 26 MIPI_DSI1_LANE2_N_CON [40] R0201_NC
MIPI_DSI1_LANE2_P_CON [40] R4010
16 25
17 24
18 23 LCD_CABC_CON [40] 1 2
[40] LCM_AVEE 19 22 LCD_TE_CONN [40] R0201_NC
[40] LCM_AVDD LCD_RST_CONN [40] R4015
D4005 20 21 MIPI_DSI1_LANE1_P_CON [40] 1 4 [4] DSI0_D1P
2
VIO18_PMU [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84]
2
D4004 D4006
NF_WE07DF-B
ÓëIIC0ÉÏÀµçÑ¹ÏàÍ¬ ICMF052P900MFR
NF_WE07DF-B
N2
41 44 MIPI_DSI1_LANE1_N_CON [40] 2 3 [4] DSI0_D1N
2
N2
N2
C4003 C4004 42 GND4PIN 43 EMI4004
R4014 1 2
C4005
N1
NF_68pF;2%;50V;0201 NF_33pF;5%;50V;0201 NF_100K;5%;0201 R0201_NC
N1
N1
R4013
NF_68pF;2%;50V;0201 AXQ1401GX1
NF_PESD3V3V1BCSF
1
1
1
1
1 2
R0201_NC
R4017
MIPI_DSI1_LANE0_P_CON [40] 1 4 [4] DSI0_D0P
ICMF052P900MFR
C
TP 1
EMI4005
R4016
2
R0201_NC
C
[4] SPI2_CK SPI2_CK [4]
[4] SPI2_MO SPI2_MO [4]
[4] SPI2_MI SPI2_MI [4]
[4] SPI2_CS SPI2_CS [4]
1 R4018 2
0,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU
NF_10K;5%;0201
1 R4019 2
NF_10K;5%;0201 1 R4020 2
[40] EINT_CTP_CON EINT_CTP [4]
0;0.5A;0201
[3,40] GPIO_CTP_RSTB GPIO_CTP_RSTB [3,40]
[4,40] SDA0 SDA0 [4,40]
[4,40] SCL0 SCL0 [4,40]

D4009 D4008 D4010 D4011 D4012 D4013 D4014
2
2
D4007
2
C4008 C4009
N2
N2
N2
N2
N2
N2
N2
N2
NF_33pF;5%;50V;0201NF_33pF;5%;50V;0201
C4006
LCDBACKLIGHT
N1
N1
N1
N1
N1
N1
N1
C4007
N1
NF_33pF;5%;50V;0201 NF_33pF;5%;50V;0201
NF_PESD3V3V1BCSF
NF_PESD3V3V1BCSF
NF_PESD3V3V1BCSF
NF_PESD3V3V1BCSF
NF_PESD3V3V1BCSF
NF_PESD3V3V1BCSF
NF_PESD3V3V1BCSF
NF_PESD3V3V1BCSF
1
1
[7,8,9,13,15,32,37,40,41,42,43,44,48] VSYS
L4002 40V 1A
R4037 0;1A;0402
D4037 WSB5503W-2/TR
B 2 1 1 2 LCM_LEDA [40] B
C4061
10uH;20%;2520
1.0UF;20%;6.3V;0201 C4062
2
1.0uF;10%;50V;0603
R4040 C4064
0603 50V
10;5%;0402 C0201_NC
C3
U4001
1
C2
SW
VIN
[4] GPIO_LCM_LED_EN C1
EN
R4038 0;0.5A;0201
TP4003 R4034 0;0.5A;0201 A3 LCM_LEDK_1 [40]
1 2 IFB1
[40] LCD_CABC B1
LCD Gate Drive 1 PWM

IFB2
A2
R4039 0;0.5A;0201
LCM_LEDK_2 [40]
1
B2
GND
R4036 R4035 NF_0;0.5A;0201 LCM_BL_PWM COMP
A1
47K;5%;0201 1 2 ISET
LCD Gate Driver I2C address: 0X3E (Write:0x7C, Read:0x7D) [4] DISP_PWM
L4001 SGM3743
B3
2
C4025 C4014 C4015
47pF;5%;50V;0201 C0201_NC C0201_NC
[7,8,9,13,15,32,37,40,41,42,43,44,48] VSYS
4.7UH;20%;2016 C4017
C4016
C4098 1.0UF;20%;6.3V;0201 0.33uF;20%;6.3V;0201
4.7uF;10%;10V;0603
1
GND R4041
U4003 51K;1%;0201 R4042
C1 D1 NF_270K;1%;0201
VIN LX
2
[4] ENP B1 E3
2
ENP AVDD
A1 E2 C4013
[4] ENN ENN BSTO2 GND 3
10uF;20%;16V;0603 Q4001
[4,13,48] SCL5 B2 D3 NF_PNM723T30V01
SCL BSTO1 1
BL_ISET_EN [3]
C2 R4032
1 0;0.5A;0201
2 2
[4,13,48] SDA5 SDA LCM_AVDD [40]
A2
B3 AVEE
PGND1 R4033 0;0.5A;0201
E1 C3 1 2
PGND2 CFLY1 LCM_AVEE [40]
C4010
D2 A3
1 AGND CFLY2
TP4001 4.7UF;10%;10V;0402
C4011 C4012
OCP2131
10uF;20%;16V;0603 10uF;20%;16V;0603
1
A TP4002 A
GND GND
GND
Title REV: V10

40_LCD/CTP IF
5 4 3 2 1
5 4 3 2 1
Main Camera 13M [4,41]

[4,41]
CAM_RST2
[4,41] SCL4
SDA4 L4103
SCL4 [4,41]
SDA4
CAM_RST2
[4,41]
[4,41]
TP4124
[4] CAM_CLK2 CAM_MCLK2_CON [41]
NF_18pF;5%;50V;0201C4103
NF_33pF;5%;50V;0201C4104
NF_33pF;5%;50V;0201C4164
NF_33pF;5%;50V;0201C4165
68ohm;600mA;0402
J4101 Depth Camera 2M
1
24 1
GND_MCAMAVDD VCAMA1_R_CON [41]
23 2
[41] CAM_MCLK0_CON CAM_PDN0 [4,41]
22 3 J4102
21 4 SFYNC [41]
[4] RCN RDN0 [4] [41] DCAMA_CON 1 24 CAM1_AGND
20 5 RDP0 [4]
[4] RCP [4,41] CAM_RST2 2 23
19 6 RDN1 [4] CAM_MCLK2_CON [41]
[41] SFYNC 3 22
[4] RDN2 18 7 RDP1 [4] [4] RDN0_A 4 21 RCN_A [4]
17 8
[4] RDP2 RDN3 [4] 5 20
16 9 [4] RDP0_A RCP_A [4]
RDP3 [4] 6 19
[4,8,41] VCAMIO_PMU 15 10 SDA2 [4,41] DOVDD 1P8 7 18
14 11 [4,8,41] VCAMIO_PMU VCAMIO_PMU [4,8,41]
[8,41] VCAMD_PMU SCL2 [4,41] 8 17
13 12
[8,41] VLDO28_PMU R4144 0;1A;0402 AVDD 28 9 16
[4,8,41] VCAMA_PMU DCAMA_CON [41]
[4,41] SDA4 10 15
D 28 25 VCAMIO_PMU [4,8,41] D
11 14
27 GND4PIN 26 C4111 [4,41] SCL4 12 13
2
C4110 C4109
SG4111 CONN-24P-2ROW-GND4P SG4113
25 28
100pF;30%;50V;0201
4.7uF;20%;6.3V;0402
SINGLE-GND-L4 26 GND4PIN 27 SINGLE-GND-L4
1.0UF;20%;6.3V;0201
1
1
CONN-24P-2ROW-GND4P
SG4101 1 2
SINGLE-GND-L4
[8,41] VLDO28_PMU VLDO28_PMU [8,41]

[41] DEPTH_WIDE_DVDD DEPTH_WIDE_DVDD [41]
Wide Camera 8M
SCL2 [4,41] CONN-24P-2ROW-GND4P
SCL2 [4,41] [8,41] VCAMD_PMU VCAMD_PMU [8,41] [4,8,41] VCAMIO_PMU VCAMIO_PMU [4,8,41]
26 27
SDA2 [4,41] L4101 SDA2 [4,41] [4,8,41] VCAMIO_PMU 25
GND4PIN
28
VCAMIO_PMU [4,8,41] R4147 0;1A;0402
[4,8,41] VCAMA_PMU VCAMA1_W_CON [41]
CAM_CLK0 [4]
CAM_MCLK0_CON [41] [8] VCAMA2_PMU
R4162 0;1A;0402 VCAMA1_R_CON [41] [4,41] RCAM_AVDD R4148 [41] VCAMA1_W_CON 1 12 13 24 WCAM_AGND
CAM_PDN0 [4,41] [4,41] WCAM_RESET3 2 11 14 23 CAM_MCLK3_WCAM [41]
68ohm;600mA;0402 CAM_PDN0 [4,41] NF_0;1A;0402 C4160 C4159 C4161 C4162 10 15
R4143 NF_0;1A;0402 3 22
[4,41] RCAM_AVDD 9 16
C4114C4199 C4198 C4158 [4] CSI2_LANE0_N_R 4 21 CSI2_CLK_N_R [4]
C4107
C4115 C4116 C4117 C4118 [4,41] 8 17

C4119
C4108
C4166
C4167
5 20
100pF;30%;50V;0201
100pF;30%;50V;0201
4.7uF;20%;6.3V;0402
I2C_SCL_WIDE
[4,41]
1.0UF;20%;6.3V;0201
I2C_SCL_WIDE [4] CSI2_LANE0_P_R CSI2_CLK_P_R [4]
[4,41] L4104 6 7 18 19
2.2uF;20%;6.3V;0201 2.2uF;20%;6.3V;0201 [4] CSI2_LANE1_N_R
100pF;30%;50V;0201
I2C_SDA_WIDE
[4,41]
4.7uF;20%;6.3V;0402
I2C_SDA_WIDE
100pF;30%;50V;0201
7 6 19 18 CSI2_LANE2_N_R [4]
4.7uF;10%;10V;0603
1.0UF;20%;6.3V;0201
[4] CSI2_LANE1_P_R
1.0UF;20%;6.3V;0201
CAM_CLK3 [4] 5 20
CAM_MCLK3_WCAM [41] 8 17
NF_18pF;5%;50V;0201
NF_2.2uF;20%;6.3V;0201 [4] CSI2_LANE3_N_R CSI2_LANE2_P_R [4]

NF_33pF;5%;50V;0201
NF_18pF;5%;50V;0201
NF_33pF;5%;50V;0201
68ohm;600mA;0402 4 21
CAM_RST3 [4] WCAM_RESET3 [4,41] [4] CSI2_LANE3_P_R 9 3 22
16 VCAMIO_PMU [4,8,41]
R4157 10 15
NF_18pF;5%;50V;0201C4156
NF_18pF;5%;50V;0201 C4102
NF_33pF;5%;50V;0201C4157
NF_33pF;5%;50V;0201C4101
I2C_SDA_WIDE 2 23
[4,41] SDA4 11 1 24
14 DEPTH_WIDE_DVDD [41]
0;0.5A;0201 12 13
2
R4159
[4,41] SDA2 J4103 SG4114
2
NF_0;0.5A;0201 I2C_SCL_WIDE SINGLE-GND-L4
C SG4102 C
SINGLE-GND-L4 SG41101 2 [4,41] SCL4
1
R4158
0;0.5A;0201
SINGLE-GND-L4 R4160
1
[4,41] SCL2
NF_0;0.5A;0201
If use 8M WIDE R4157=0;R4158=0; R4159=NC;R4160=NC; R4155 R4156

0;0.5A;0201
If use 2M Micro R4157=NC;R4158=NC; R4159=0;R4160=0; NF_0;0.5A;0201
[8,41] VLDO28_PMU
If use 8M WIDE R4156=0;R4155=NC;
If use 2M Micro R4156=NC;R4155=0;
Rear CAM and other Camera AVDD 2P8
VSYS [7,8,9,13,15,32,37,40,41,42,43,44,48]
Front Camera 8M C4147
1.0UF;20%;6.3V;0201
U4104
4 1 RCAM_AVDD [4,41]
IN OUT
2
CONN-24P-2ROW-GND4P GND1 C4148 C4149
REAR_CAM_AVDD_EN [4] 3 5
26 27 EN GND2
33pf;30%;50V;0201
1.0UF;20%;6.3V;0201
GND4PIN
25 28
ETA5053V280DF1E
12 13
[4,41] SCL2 11 14 FCAM_DVDD [41] 1
10 15 TP4104
[4,41] SDA2 VCAMIO_PMU [4,8,41]
[4] CSI2_LANE3_P_F 9 16
8 17 CSI2_LANE2_P_F [4]
[4] CSI2_LANE3_N_F
B [4] CSI2_LANE1_P_F 7 18 CSI2_LANE2_N_F [4] B
6 19
[4] CSI2_LANE1_N_F 5 20
[4] CSI2_LANE0_P_F CSI2_CLK_P_F [4]
4 21
[4] CSI2_LANE0_N_F 3 22 CSI2_CLK_N_F [4]
2 23
[4,41] CAM_PDN3 CAM_CLK1_CON [41]
1 24 FCAM_AGND
[41] VCAMA1_F_CON
2
J4104
SG4112
SINGLE-GND-L4
1
5M 8M CAM DVDD
[7,8,32] VS2_PMU
[7,8,9,13,15,32,37,40,41,42,43,44,48] VSYS
C4152 U4102
0;0.5A;0201 R4163 C4131
VCAMD_PMU [8,41]
NF_1.0UF;20%;6.3V;0201 U4103 1.0UF;20%;6.3V;0201 4 VIN VOUT
1
DEPTH_WIDE_DVDD [41]
VSYS [7,8,9,13,15,32,37,40,41,42,43,44,48] 2
SCL2 [4,41] SCL2 [4,41] 4 CAM_DVDD_1P2_EN [4] 3 GND1 5
IN EN GND2
REAR_CAM_DVDD_EN [3] 3 1 FCAM_DVDD [41]
SDA2 [4,41] EN OUT AP7343D-12FS4-7B C4132
SDA2 [4,41] [41] FCAM_DVDD FCAM_DVDD [41] 1
L4102 2 TP4119
GND
BIAS 1.0UF;20%;6.3V;0201
[4,8,41] VCAMIO_PMU VCAMIO_PMU [4,8,41] C4151 C4153
CAM_CLK1 [4] C4150
CAM_CLK1_CON [41]
NF_SGM2038-1.2XUDY4G/TR
5
R4140 0;1A;0402 NF_0.1uF;20%;6.3V;0201
NF_33pf;30%;50V;0201
NF_1.0UF;20%;6.3V;0201
68ohm;600mA;0402 [4,8,41] VCAMA_PMU VCAMA1_F_CON [41] 1
TP4103
CAM_PDN3 [4,41] CAM_PDN3 [4,41]
R4142 NF_0;1A;0402
[4,41] RCAM_AVDD C4143 C4144 C4140 C4141 C4142
NF_18pF;5%;50V;0201C4136
NF_33pF;5%;50V;0201C4137
NF_33pF;5%;50V;0201C4138
NF_33pF;5%;50V;0201C4139
A A
100pF;30%;50V;0201
4.7uF;20%;6.3V;0402
1.0UF;20%;6.3V;0201
100pF;30%;50V;0201
4.7uF;10%;10V;0603
Title 41.Camera IF REV: V10

2
SG4108 DOCUMENT NO.: Size D

98860_1_12M13_201905302120
SINGLE-GND-L4
DEPARTMENT: DEPARTMENT DESIGNER: DESIGNER

1
5 4 3 2 1
5 4 3 2 1
R4210
[7,8,9,13,15,32,37,40,41,42,43,44,48] VSYS
0;0.5A;0201
1
C4215
0.1uF;20%;6.3V;0201
A-SP194W1D-C01-4T
LED4203
2
D D
R4201
[13] WHITE_LED
200;1%;0201
R4207
NF_200;1%;0201
3
Q4201
2
R4209 1 NF_PNM723T30V01 TVS4210
[4] LED_EN C4216
N2
2
NF_1K;1%;0201
R4208
C0201_NC
NF_100K;1%;0201
N1
NF_PESD5V0X1BCSF
1
C C
Input and output cap voltage confirm ?
EP
U4201
L4201
GND
[7,8,9,13,15,32,37,40,41,42,43,44,48] VSYS 5 8
SW1 OUT1
1
1.0UH;20%;2520 6 9
SW2 OUT2 NLW2016AY3B5258V23N9AWTLE
C4203
C4204 4 NLW2016AY3-B5060V23N9A
VIN
10uF;20%;6.3V;0603 1.0UF;20%;6.3V;0201 LED4201
12
2 2
LED1
2
14 TVS4202 TVS4203
LED2 C4201 C4211
N2
N2
[4] FLASH_EN 10 1
ENF RM
4.7uF;20%;6.3V;0402
4.7uF;20%;6.3V;0402
N1
N1
11 2
AGND1
AGND2
[3] TORCH_EN ENM RF
PGND
NF_PSED5V0H1BSF
NF_PSED5V0H1BSF
1
C4213 C4214
1
NF_0.1uF;20%;6.3V;0201 NF_0.1uF;20%;6.3V;0201 R4202
13
7
OCP8132AVAD R4203
12K;5%;0201
68K;5%;0201
Changed from 10uf 0603
2
B B
A A
Title REV: V10

42_Flash/RGB
5 4 3 2 1
5 4 3 2 1
Fingerprint
SPI0_MO_JTAG [47]
SPI0_MI_JTAG [47]
SPI0_CLK_JTAG [47]
D
SPI0_CSB_JTAG [47] D
[4] EINT_FP_N
R4310 0;0.5A;0201
[43] FP_3V3
J4301
EGND1 2 RST_N R4305 0;0.5A;0201
GPIO_FP_RST_N [4]
GND3 4 MOSI R4306 0;0.5A;0201
R4309 0;0.5A;0201 INT5 SPI0_MO [4]
6 MISO R4307 0;0.5A;0201 SPI0_MI [4]
VCC3V37 8 SCLK R4303 0;0.5A;0201
R4302 NF_0;0.5A;0201 VDD1V89 SPI0_CLK [4]
[2,3,4,6,8,10,13,15,17,32,37,39,40,44,45,47,48,58,61,62,67,70,84] VIO18_PMU 10 CS_N R4308 0;0.5A;0201
SPI0_CSB [4]
TVS4301 TVS4302
2
11 14
12 GND4PIN 13
N2
N2
TVS4303 TVS4304 TVS4305 TVS4306
2
TVS4307
2
C4306 C4307 C4308 C4309
C4305
N2
N2
N2
N2
C4311 GB04P-10S-H08-E5000 C0201_NC C0201_NC C0201_NC C0201_NC C0201_NC
N2
R4311 0;0.5A;0201 C4310 C4312 C4313 C4319
N1
N1
[43] FP_1V8
C0201_NC C0201_NC C0201_NC
NF__PESD5V0X1BCSF
N1
N1
N1
N1
NF_PESD3V3V1BCSF
0.1uF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
N1
1
NF_PESD3V3V1BCSF
NF_PESD3V3V1BCSF
NF_PESD3V3V1BCSF
NF_PESD3V3V1BCSF
1
1
PESD3V3V1BCSF
1
Fingerprint
C C
VSYS [7,8,9,13,15,32,37,40,41,42,43,44,48]
TP4301
1
B B
U4301 C4316
U4302
[43] FP_3V3 1 4 VSYS [7,8,9,13,15,32,37,40,41,42,43,44,48]
VOUT VIN 1.0UF;20%;6.3V;0201 4 1 FP_1V8 [43]
2 VIN VOUT
5 GND1 3
GND2 EN FP_3V3_EN [4] 2
FP_1V8_EN [4] 3 GND1 5
C4314 EN NC
C4315 AP7343D-33FS4-7B C4317 C4318
ETA5053V180DF1E
33pf;30%;50V;0201
1.0UF;20%;6.3V;0201
1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
1
TP4302
A A
Title 43.Fingerprint REV: V10
DOCUMENT NO.: 98860_1_12M13_201905302120 Size D
DEPARTMENT: Wingtech-SZ DESIGNER: DESIGNER

5 4 3 2 1
5 4 3 2 1
ALP-Sensor
ACCELEROMETER+GYRO
[4,44] SCP_SPI_CLK
[4,44] SCP_SPI_MO
D
[4,44]
[4,44]
SCP_SPI_MI
SCP_SPI_CSB
Proximity Sensor D
1
[44] LEDA R4424
TP4404 TP4403 TP4402 TP4401 [7,8,9,13,15,32,37,40,41,42,43,44,48] VSYS TP4405
0;0.5A;0201
C4405 C4407
1
0.1uF;20%;6.3V;0201
U4401 2.2uF;20%;6.3V;0402 U4402
[44] LEDA 1 4 VSYS [7,8,9,13,15,32,37,40,41,42,43,44,48]

VOUT VIN
[4,44] SCP_SPI_MI 1 8 2
SDO VDD VIO28_PMU [8,44,84] GND1
5 3
2 9 C4410 GND2 EN PSENSOR_3V3_EN [4]
R4415 NF_10K;5%;0201 ASDX INT2 C4417
[2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU R4413 NF_0;0.5A;0201
3 10 C4416 NF_AP7343D-33FS4-7B
ASCX OCSB 2.2uF;20%;6.3V;0402
4 11 R4414 NF_0;0.5A;0201
BMI160
[4] ACC_GYRO_INT1 INT1 OSDO
SCP_SPI_CSB [4,44] 1.0UF;20%;6.3V;0201 1.0UF;20%;6.3V;0201
5 12
VDDIO CSB
R4418 10K;5%;0201 6 13
GNDIO SCX SCP_SPI_CLK [4,44]
7 14
GND SDX SCP_SPI_MO [4,44]
C4402
0.1uF;20%;6.3V;0201
[2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU
C C
J4401
R4416
1
EINT_ALPS [4,44]
C4412
0;0.5A;0201 C0201_NC
CONN-1P
J4402
1
R4419
LEDA [44] Ambient Light Sensor

0;0.5A;0201
B CONN-1P B
[2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU
J4403 R4425
R4420 22;5%;0201
VIO28_PMU [8,44,84]
1 R4410
VIO18_PMU_LP [44]
R4409
10K;1%;0201 NF_22;5%;0201 VIO18_PMU [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84]
0;0.5A;0201 [44] VIO18_PMU_LP
CONN-1P
C4411
J4404
R4421 C4401
4.7uF;20%;6.3V;0402 NF_1.0UF;20%;6.3V;0201
1 SCL1 [4]
[4,44] EINT_ALPS
0;0.5A;0201 C4414
CONN-1P
C0201_NC
J4405
R4422
1 SDA1 [4]
0;0.5A;0201 C4413
CONN-1P
C0201_NC
J4406
CONN-1P
A A
Title REV: V10

44_Sensor
5 4 3 2 1
5 4 3 2 1
J4501
MSDC1_DAT2_CON [45] P1 G1
P2 DAT2 GND G2
MSDC1_DAT3_CON [45]
P3 CT/DAT3 GND G3
MSDC1_CMD_CON [45]
VMCH_PMU [8,45] P4 CMD GND G4
VDD GND
TF
MSDC1_CLK_CON [45] P5 G5
P6 CLK GND G6
P7 VSS GND G7
MSDC1_DAT0_CON [45]
P8 DAT0 GND G8
MSDC1_DAT1_CON [45]
DAT1 GND G9
GND G10
GND G11
TF CARD EINT_SIM_SD_CON [45]
A1
A2
DET_LEVER
GND
GND
G12
DET_SW
D D
R4509 VSIM1_PMU_CON [45] AC11 AC51

[4] MSDC1_DAT2 22;5%;0201 AC12 VCC-SIMA GND AC52
MSDC1_DAT2_CON [45]
AC13 VCC1-SIMA SIMA GND AC53
VCC2-SIMA GND
[4] MSDC1_DAT3 R4510 22;5%;0201 AC21 AC61
MSDC1_DAT3_CON [45]
SIM1_SRST_CON [45] AC22 RST-SIMA VPP-SIMA AC62
AC23 RST1-SIMA VPP1-SIMA AC63
[4] MSDC1_CMD R4511 22;5%;0201 RST2-SIMA VPP2-SIMA
MSDC1_CMD_CON [45]
AC31 AC71
SIM1_SCLK_CON [45] AC32 CLK-SIMA I/O-SIMA AC72 [45] SIM1_SIO_CON
[8,45] VMCH_PMU AC33 CLK1-SIMA I/O1-SIMA AC73
CLK2-SIMA I/O2-SIMA
[4] MSDC1_CLK R4512 22;5%;0201

MSDC1_CLK_CON [45]
BC11 BC51
VSIM2_PMU_CON [45] BC12 VCC-SIMB GND BC52
BC13 VCC1-SIMB GND BC53
VCC2-SIMB GND
BC21 SIMB BC61
[4] MSDC1_DAT0 R4513 22;5%;0201 BC22 RST-SIMB VPP-SIMB BC62
MSDC1_DAT0_CON [45] SIM2_SRST_CON [45]
BC23 RST1-SIMB VPP1-SIMB BC63
RST2-SIMB VPP2-SIMB
[4] MSDC1_DAT1 R4514 22;5%;0201 BC31 BC71
MSDC1_DAT1_CON [45]
SIM2_SCLK_CON [45] BC32 CLK-SIMB I/O-SIMB BC72 [45] SIM2_SIO_CON
BC33 CLK1-SIMB I/O1-SIMB BC73
CLK2-SIMB I/O2-SIMB
2
TVS4514 TVS4513 TVS4512
2
2
2
TVS4517 TVS4516 TVS4502 TVS4515
C4570
N2
N2
N2
N2
N2
N2
N2
SIM-T-CAF00-20137-1029
C0201_NC
C4511
Note:
N1
N1
N1
HIGH when Tray inserted
N1
N1
N1
N1
2.2uF;20%;6.3V;0402
NF_PSED5V0H1BSF
NF_PSED5V0H1BSF
1
NF_PSED5V0H1BSF
1
1
NF_PSED5V0H1BSF PESD5V0S1BL
SIM&SD Connector
C C
SIM1 [8,45] VMCH_PMU
[3] SIM1_SCLK R4503 22;5%;0201

SIM1_SCLK_CON [45]
[3] SIM1_SRST R4504 22;5%;0201

SIM1_SRST_CON [45]
R4501 22;5%;0201
[2,8] VSIM1_PMU VSIM1_PMU_CON [45]
R4525
100K;5%;0201
C4530
0.1uF;20%;6.3V;0201
[3] SIM1_SIO 22;5%;0201 R4505 SIM1_SIO_CON [45]
2
2
2
TVS4511 TVS4503 TVS4504

2
TVS4505
N2
N2
N2
B B
N2
N1
N1
N1
C4501
N1
1
1
1.0UF;20%;6.3V;0201
1
SIM2 [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU
[3] SIM2_SCLK R4516 22;5%;0201 R4529

SIM2_SCLK_CON [45]
[9] SD_CARD_DET_N_PMU R4521
R4517 22;5%;0201 0;0.5A;0201
[3] SIM2_SRST SIM2_SRST_CON [45] 100K;1%;0201
R4518 22;5%;0201
[2,8] VSIM2_PMU VSIM2_PMU_CON [45]
SH4511
[4] EINT_SD L1
EINT_SIM_SD_CON [45]
SH4512
22;5%;0201 R4520
2
[3] SIM2_SIO SIM2_SIO_CON [45] L1 TVS4501
[3] INT_SIM1
N2
SH4513
2
L1
2
TVS4507 TVS4508 TVS4509 [3] INT_SIM2

2
N1
TVS4518
N2
N2
N2
N2
NF_PSED5V0H1BSF
1
N1
N1
N1
C4502
N1
1
1
1.0UF;20%;6.3V;0201
1
A A
Title 45_SIM/TF IF REV: V10
5 4 3 2 Date: 1 Thursday, May 30, 2019 Sheet 31 of 65

5 4 3 2 1
D D
Power Key / Key Pad

DO NOT put pull-up resistor on PWRKEY
[47] KPCOL2_TP
[47] PWRKEY_CONN_TP
[47] KPCOL0_TP
J4601 J4602
AT12-110001-04 AT12-110001-04
VOLUME DOWN:KPCOL2+GND
1 1
2 2
J4603
AT12-110001-04
J4605
Note: 75-1
AT12-110001-04
C
POWKEY£ºPWR+GND C
1 R4601 1K;5%;0201 PWRKEY_SW [9,13]
2
1 J4604
AT12-110001-04
2
2
TVS4601
N2
5V PESD5V0X1BCSF C4601
C0201_NC
VOLUME UP:KPCOL0+GND
N1
1
1
[4] KPCOL0 R4602 1K;5%;0201
GND
2
TVS4604
N2
Note: 75-3
Note: 75-3
N1
PESD5V0X1BCSF
1
[4] KPCOL2 R4603 1K;5%;0201
TVS4602
2
Note: 75-3
N2
N1
SIDEKEY
PESD5V0X1BCSF
1
VOLUME UP: KPCOL0+GND
POWERON PWRKEY+GND
VOLUME DOWN: KPCOL2+GND
B B
Note 751:DO NOT put pullup resistor on PWRKEY

Note 752: Volume Up:KPCOL0+GND
Volume Down:KPCOL2+GND
A A
Title 46_Sidekey REV: V10
5 4 3 2 Date: 1Thursday, May 30, 2019 Sheet 32 of 65

5 4 3 2 1
CT BT USB
Grounding
TP4712 TP4780 TP4765 TP4714 TP4716 TP4717
DEVICE MODE CONF
TP4713 J4709
[13,36,67] VBAT 1 TP-1.5MM TP-1MM TP-1MM TP-1.5MM TP-1MM TP-1MM
TP-1.5MM
[2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU AT12-110001-04
D D
1
1
TP4721
[4,36,48] USB_DM 1
1 TP-1.5MM R4723
[9,36] BATON_CONN R4724
[4,36,48] USB_DP J4708 2
1
TP4731 [48] VBUS_USB_CON AT12-110001-04
1 TP-1.5MM
USB_CC1_CON [48] 10K;5%;0201 10K;5%;0201 BOARD_ID
2
TP4730
1 TP-1.5MM USB_CC2_CON [48] R4706 0;0.5A;0201 [4] 1
HW_ID2
J4706 2
R4707 0;0.5A;0201 [4] HW_ID1
BAT GND place near the connect AT12-110001-04
KEYS R709 R710

1
1
TP4781
1 [46] PWRKEY_CONN_TP
POWER_ON 1
TP4703
TP-1MM C4721 C4722 J4707
2
[3,6] VBAT_GND TP-1.5MM
FASTBOOT VOL_DOWN 1 TP-1MM
0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201
[46] KPCOL2_TP TP4705 10K;5%;0201 10K;5%;0201 AT12-110001-04
2
HOLE4700 HOLE4702 HOLE4703 HOLE4704 HOLE4710
FORCE DOWNLOAD VOL_UP 1

PTH-1.6MM PTH-1.6MM PTH-1.6MM PTH-1.6MM PTH-1.6MM
[46] KPCOL0_TP 1
TP4766 TP-1MM
J4701 2
AT12-110001-04
1
1
HOLE4707 HOLE4708 HOLE4709
2 HOLE4705 HOLE4706
PTH-1.6MM PTH-1.6MM PTH-1.6MM
PTH-1.6MM PTH-1.6MM
SPR4702
AT05-110001-01
PTH
1
1
1
C C
JTAG CONNECTOR
1
J4703
J4705 AT12-110001-04
[43] SPI0_CSB_JTAG
1
3
TMS 5
2 TDO
4 TCK
6 TDI
SPI0_MI_JTAG [43]
SPI0_CLK_JTAG
SPI0_MO_JTAG [43]
[43]
UART
7 8
1
9 10
11 12 VIO18_PMU [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] R4716 1K;5%;0201 1
[4,47] UTXD0 [4,47] UTXD0 TP4761 2
13 14
[4,47] URXD0 R4717 1K;5%;0201
15 16 [4,47] URXD0
JTRST [4] TP-0.8MM
J4704
1
17 18 TP4762 AT12-110001-04
C4723
NF_0.01uF;20%;25V;0201 TP-0.8MM
CONN-16P-2ROW-GND2P-A
TOP BOSS Grounding
B B
SHIELDING
SH4701
BOT SH4702
MARK Waterproof
SH4706
FM4701 FM4703
FM4702 FM4704 J4712
ÆÁ±ÎÕÖ ÆÁ±ÎÕÖ ÆÁ±ÎÕÖ 1mm 1mm 1mm 1mm
1
PMU WCN
1
RF
1
1
1
1
ICO-WATERPROOF-D3
A
TOP BAD MARK J4713 A
BM4705 BM4706
SH4704 SH4705 SH4703 BAD Mark BAD Mark 1
SC10-210001-01
ÆÁ±ÎÕÖ ÆÁ±ÎÕÖ ÆÁ±ÎÕÖ
1
RF PA BB
1
Smart PA
Title 47_Testpoint/Shielding/GND REV: V10
5 4 3 2 1
5 4 3 2 1
OVP
D D
SUB CONN.
R4801 0;1A;0603
U4801
J4801 R4802 0;1A;0603 6.8V
[47,48] VBUS_USB_CON
42 41 B3 A2
1
POWER VBUS_USB_CON [47,48] IN1 OUT1 VBUS [9,13,48]
C2 A3
R4804 R4805 IN2 OUT2
C4804 C3 B2
1 40 C4805 NF_51K;5%;0201 IN3 OUT3
[37] SPK1_P_FB 2 39 SPK1_N_FB [37] 1.0uF;10%;25V;0402
2
150pF;10%;50V;0201 C4806
2
3 38
3
4 37 C1 B1
N2
GND
47K;5%;0201 OVLO ACOK
[37] SPK_OUT_P1 5 36 0.01uF;20%;25V;0201
SPK_OUT_N1 [37] D4802 D4801
6 35
1
7 34 MIC_IN1_M_CON [32,38] NF_PTVS18VU1UPA NF_WE07DF-B
N1
[3,70] MIPI2_SCLK AW33905
A1
8 33 MIC_IN1_P_CON [32,38] R4806
[3,70] MIPI2_SDATA 9 32 0;0.5A;0201
1
10 31 MICBIAS1A [10,32]
[47,48] USB_CC2_CON 11 30
2
[47,48] USB_CC1_CON 12 29 USB_DM [4,36,47]
13 28
BATON_SUB USB_DP [4,36,47]
14 27
15 26 VSW_HAP_P [37]
16 25
[2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU VSW_HAP_M [37]
17 24
18 23
[84] HB_ANT_SAR_PRI VFE28_PMU [8,67]
[84] LMB_ANT_SAR_REF 19 22
20 21
[84] LMB_ANT_SAR_PRI
43 44
POWER
WP27D-SX40VA3
C C
MAIN MIC CS7331P.
R4857
1 2
NF_0;0.5A;0201
U4802
1 4 VSYS [7,8,9,13,15,32,37,40,41,42,43,44]
[48] VDD_CCLOGIC VOUT VIN
2
5 GND1 3 VIO18_PMUC4816
[2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84]
GND2 EN
AP7343D-33FS4-7B C4817
1.0UF;20%;6.3V;0201
VIO18_PMU [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] NF_1.0UF;20%;6.3V;0201
1
R4856
NF_200K;1%;0201
[47,48] VBUS_USB_CON
2
[4] USB_ID
R4812
CC LOGIC R4859NF_0;0.5A;0201
1 2
NF_51K;5%;0201 1 2
[2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU
R4858NF_0;0.5A;0201
R4810 33;5%;0201
[48] VDD_CCLOGIC
[47,48] USB_CC1_CON USB_TYPEC_CC1 [48]
C4815
USB_TYPEC_CC2 [48]
12
11
10
[47,48] USB_CC2_CON
9
U4804
R4811 33;5%;0201 NF_0.1uF;20%;6.3V;0201
2
ID
VDD
EN_N
GND
D4825 D4826
N2
N2
WE07DF-B WE07DF-B SCL5 [4,13,40,48]

1 8
CC1 SCL/OUT2
N1
N1
2 7
INT_N/OUT3
CC2 SDA/OUT1
VBUS_DET
B SDA5 [4,13,40,48] B
1
PORT
ADDR
3
6
NF_TUSB320LI
VIO18_PMU [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84]
U4803
R4853
USB_TYPEC_CC1 [48] C1 B1 1 2 VDD_CCLOGIC [48]
CC1 VCONN
1
USB_TYPEC_CC2 [48] A1 A3
CC2 VDD 0;0.5A;0201
R4851 4.7K;5%;0201 R4817
1 2 A2 B3 SCL5 [4,13,40,48] 2.2K;5%;0201
[9,13,48] VBUS VBUS SCL
150K C3
2
C2 SDA SDA5 [4,13,40,48]
GND B2
INT_N CC_INT [4]
C4810 RT1711H C4811 C4812

C4813 C4814 0.1uF;20%;25V;0201
0.1uF;20%;25V;0201
0.1uF;20%;25V;0201220pF;20%;50V;0201220pF;20%;50V;0201
Change 330pF
A A
Title 48_Sub PCB IF REV: V10

5 4 3 2 1
5 4 3 2 1
D D
GPIO Interface MIPI Interface POWER Interface

[3,69] BPI_ANT2
[3,73] BPI_ANT1 [3,67] MIPI0_SCLK

[3,67] MIPI0_SDATA
[3,69] BPI_ANT0 [13,36,47,67] VBAT
[3,62] MIPI1_SCLK
[3,62] MIPI1_SDATA [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU
[8,48,67] VFE28_PMU
[3,48,70] MIPI2_SCLK
[8,44,84] VIO28_PMU
[3,48,70] MIPI2_SDATA
[7,67] VPA_PMU
[3,72] BPI_BUS7
[8,77,79] VCN28_PMU
[3,62] BPI_BUS5
[8,77] VCN18_PMU
[3,62] BPI_BUS4
[8,77] VCN33_PMU
[3,61] BPI_BUS3
[3,61] BPI_BUS2
[3,62] BPI_BUS1
[3,72] BPI_BUS0
C C
I2C Interface
[4,37,84] SDA3
[4,37,84] SCL3
B B
A A
Title
Page Name = 56_RF InterfaceREV: V10
DOCUMENT NO.: Size

Design Name = 98860_1_12M13_201905302120 D
DEPARTMENT: DEPARTMENT = WINGTECH-SZDESIGNER: DESIGNER = LIUFENGLEI
Date: Page Modify Date = Thursday, May 30, 2019

Sheet 35 of 65
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title
<Title>
Size Document Number Rev

A1 <Doc> 1.0
5 4 3 2 1
5 4 3 2 1
D D
RF_B2_PRX_RFIC [65]
Attenuator for Detector
RF_B7_PRX_RFIC [65]
[58] RF_TXDET_RFIC R5810 33;5%;0201
RF_TXDET_SPDT [62]
RF_B4_PRX_RFIC [65]
[72] RF_B8_DRX_RFIC
R5808 R5809
RF_B1_PRX_RFIC [65]
150;5%;0201 150;5%;0201
[72] RF_B20_DRX_RFIC
RF_B41B40_PRX_RFIC [67]
[72] RF_B5_DRX_RFIC Note2:
RF_B3_PRX_RFIC [65]
RF_B28B_PRX_RFIC [64]
RF_DCSPCS_PRX_RFIC [65]
[72] RF_B2_DRX_RFIC
RF_B5_PRX_RFIC [64]
RF_B8_PRX_RFIC [64]
[72]
[73]
RF_B1B3_DRX_RFIC
RF_B7_DRX_RFIC
RF_B28A_PRX_RFIC [64] Power For MT6177
RF_B20_PRX_RFIC [64]
[58] VRF18_TXHV R5802 0;0.5A;0201 VRF18_PMU [8]

C5806
C11
C12
D11
B10
A11
A12
B11
B12
E11
E12
U5801 R5803 0;0.5A;0201
D1
D2
C2
E2
A1
B1
B2
A2
A3
B3
B4
B5
A5
A6
B6
B8
A8
A9
B9
F1
[58] VRF18_RXHV
4.7uF;20%;6.3V;0402
NC1
DRX14
DRX13
DRX12
DRX11
DRX10
DRX9
DRX8
DRX7
DRX6
DRX5
DRX4
DRX3
DRX2
DRX1
NC2
PRX14
PRX13
PRX12
PRX11
PRX10
PRX9
PRX8
PRX7
PRX6
PRX5
PRX4
PRX3
PRX2
PRX1
B7 R5804 0;0.5A;0201
GND1 [58] VRF18_SXLF
C3
C4 GND2
GND3
Note1:
C5 DRX PRX G12
C C6 GND4 TX_UHB R5805 0;0.5A;0201 C
GND5 [58] VRF12_RXLV VRF12_PMU [8]
C7 G11
C8 GND6 TX_HB1 C5807
C9 GND7 H11 R5806 0;0.5A;0201
GND8 TX_HB2 RF_HB_TX_RFIC_OUT [67] [58] VRF12_SXLV
C10 4.7uF;20%;6.3V;0402
D3 GND9 J11
D4 GND10 TX_MB1 R5807 0;0.5A;0201
GND11 [58] VIO18_RFIC VIO18_PMU [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,61,62,67,70,84]
D5 J12
GND12 RF_MB_TX_RFIC_OUT [67]
D6 TXO TX_MB2
D7 GND13 K12
GND14 TX_MB3 RF_2GHB_TX_RFIC_OUT [62]
D8
D9 GND15 K11
GND16 TX_LB1 RF_LB_TX_RFIC_OUT [67]
D10
E3 GND17 L11
E4 GND18 TX_LB2
E5
E8
E9
GND19
GND20
GND21
MT6177 TX_LB3
M11
M12
RF_2GLB_TX_RFIC_OUT [62]
E10 GND22 TX_LB4

F2 GND23 M7
F3 GND24 TXDET1 RF_TXDET_RFIC [58]
F4 GND25
F5 GND26
F6 GND27
F7 GND28 N8
F8 GND29 VDD_TXHV VRF18_TXHV [58]
F9 GND30 N5
F10 GND31 VDD_SXLF VRF18_SXLF [58]
F11 GND32 K5
GND33
F12
GND34
Power VDD_SXLV VRF12_SXLV [58]
G2 E6 VRF12_RXLV [58]
G3 GND35 VDD_RXLV
G5 GND36 E7
GND37 VDD_RXHV VRF18_RXHV [58]
G6
G7 GND38 J2
GND39 VIO VIO18_RFIC [58]
G8
G9 GND40
G10 GND41
H2 GND42 J1 C5801 C5802 C5803 C5804 C5805 C5808
GND43 XOI PMIC_CLK_RF [11]
H3 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201 0.1uF;20%;6.3V;0201
H6 GND44 H4
GND45 EN_BB SRCLKENA1 [3,11]
H7
H8 GND46 G1
H9 GND47 DETIF DRX(I/Q) PRX(I/Q) TX(I/Q) BSI TMEAS
H10 GND48 H1 RFIC_RCAL
J3 GND49 RCAL
DRX_BB_Q1
DRX_BB_Q0
PRX_BB_Q1
PRX_BB_Q0
TX_BB_QN0
TX_BB_QP0
TXO_GND1
TXO_GND2
TXO_GND3
TXO_GND4
DRX_BB_I1
DRX_BB_I0
GND50
PRX_BB_I1
PRX_BB_I0
TX_BB_IN0
TX_BB_IP0
J6
BSI_0_EN
BSI_0_CK
DET_QN0
DET_QP0
BSI_0_D0
BSI_0_D1
GND51
DET_IN0
DET_IP0
J7
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND65
GND66
GND67
GND68
GND69
J8 GND52
J9 GND53
B GND54 R5801 B
2K;1%;0201
K2
K6
K7
K8
K9
L3
L4
L5
L6
L7
L8
L9
M2
M9
M10
L10
K10
J10
N7
M6
M5
N6
L2
L1
M3
N3
M1
N1
N4
M4
N9
N10
N11
N12
J5
H5
J4
K3
K4
MT6177W/ACA-E-H
LTE_DET_BB_QN0
LTE_DET_BB_QP0
LTE_DET_BB_IN0
LTE_DET_BB_IP0
LTE_DRX_BB_Q1
LTE_DRX_BB_Q0
LTE_PRX_BB_Q1
LTE_PRX_BB_Q0
LTE_TX_BB_QN0
LTE_TX_BB_QP0
LTE_DRX_BB_I1
LTE_DRX_BB_I0
LTE_PRX_BB_I1
LTE_PRX_BB_I0
LTE_TX_BB_IN0
LTE_TX_BB_IP0
RFIC0_BSI_EN
RFIC0_BSI_CK
RFIC0_BSI_D0
RFIC0_BSI_D1
[3] LTE_DET_BB_IP0 RX Port Assignment
[3] LTE_DET_BB_IN0 RFIC0_BSI_D1 [3]
PRX1 LTE Band20 DRX1 UNUSED
[3] LTE_DET_BB_QP0 RFIC0_BSI_D0 [3] PRX2 LTE Band28A DRX2 LTE Band8/WCDMA Band8
PRX3 LTE Band8/WCDMA Band8/GSM900 DRX3 UNUSED
[3] LTE_DET_BB_QN0 RFIC0_BSI_CK [3] PRX4 LTE Band5/WCDMA Band5/GSM850 DRX4 LTE Band20
PRX5 UNUSED DRX5 UNUSED
RFIC0_BSI_EN [3] PRX6 DCS1800/PCS1900 DRX6 LTE Band5/WCDMA Band5
PRX7 UNUSED DRX7 LTE Band28
PRX8 LTE Band28B DRX8 UNUSED
PRX9 LTE Band3 DRX9 LTE Band40
[3] LTE_DRX_BB_Q1 LTE_TX_BB_IP0 [3] PRX10 LTE Band40/LTE Band41/LTE Band38 DRX10 LTE Band2/WCDMA Band2
PRX11 LTE Band1/WCDMA Band1 DRX11 LTE Band41/LTE Band38
[3] LTE_DRX_BB_I1 LTE_TX_BB_IN0 [3] PRX12 LTE Band4/WCDMA Band4 DRX12 LTE Band1/LTE Band3/LTE Band4/WCDMA Band1/WCDMA Band4
PRX13 LTE Band7 DRX13 LTE Band7
[3] LTE_DRX_BB_Q0 LTE_TX_BB_QP0 [3] PRX14 LTE Band2/WCDMA Band2 DRX14 UNUSED
[3] LTE_DRX_BB_I0 LTE_TX_BB_QN0 [3]
Note1: 4.7uF close to RFIC and check connection with pmic

[3] LTE_PRX_BB_Q1
[3] LTE_PRX_BB_I1
Note2: 6dB Attenuator and check connection with coupler
[3] LTE_PRX_BB_Q0
[3] LTE_PRX_BB_I0
A A
Title Page Name = 58_TransceiverREV: V10
DOCUMENT NO.: Size

Design Name = 98860_1_12M13_201905302120 D

Sheet 37 of 65
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title REV: V10

Reserved
DOCUMENT NO.: Design Name Size A1
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title REV: V10

Reserved
5 4 3 2 1
5 4 3 2 1
D D
ANT_LMB
J6101
ECT818000500
J6102
C6101 C6123 C6107

2 RF_AntMLB_TRX_ANT RF_AntMLB_TRX_RFSWITCH_OUT 2 1 RF_AntMLB_TRX_RFSWITCH_IN
I/O OUT IN RF_AntMLB_TRX_RFSWITCH [62]
GND1
GND2
GND3
GND2
GND1
33pF;5%;50V;0201 33pF;5%;50V;0201 33pF;5%;50V;0201
L6125
3
4
1
L0201_NC 818004112
4
3
Note2:
L6130
68nH;5%;0201
R6103
10K;5%;0201
ANT_DET_LMB
U6101
C6108
5
RF-MXD8546C
RF_AntMLB_TRX_DPDT_IN1 R6104
4 6
GND3
[69] RF_Ant_DRX_DPDT_OUT2 RFI1 RFI2 BPI_BUS3 [3]
3 7 0;0.5A;0201
C6124 GND2 GND4 33pF;5%;50V;0201
RF_AntMLB_TRX_DPDT_OUT1 2 8
RFO1 RFO2 RF_AntMLB_TRX_DPDT_OUT2 [69]
VDD
1 9 R6105
C 33pF;5%;50V;0201 GND1 VCTL 100K;5%;0201 C
C6102
VIO_1P8_ANT_DET_LMB
10
47pF;10%;50V;0201
L6131
VIO18_PMU [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84]
[3] BPI_BUS10 68nH;5%;0201
[62,67,69,70,72] LTE_VFE28
100pF;5%;50V;0201 C6122 100pF;5%;50V;0201

C6103
C6121 100pF;5%;50V;0201
ANT_HB
J6103
ECT818000500 Note1: J6104
C6104
2 RF_AntHB_TRX_ANT RF_AntHB_TRX_RFSWITCH_OUT 2 1
I/O OUT IN RF_AntHB_TRX_RFSWITCH [62]
GND1
GND2
GND3
GND2
GND1
33pF;5%;50V;0201
B L6101 B
3
4
1
818004112
L0201_NC
4
3
R6106
10K;5%;0201
ANT_DET_HB
R6107
BPI_BUS2 [3]
0;0.5A;0201
C6105 Note1: RF SWITCH DETECT,MUST BE CAP IF DPDT IS WITHOUT DC BLOCK

R6108
100K;5%;0201
47pF;10%;50V;0201
Note2: MUST BE IND FOR RF SWITCH DETECT
VIO_1P8_ANT_DET_HB
L6102
VIO18_PMU [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84]
68nH;5%;0201
C6106
100pF;5%;50V;0201
A A
Title REV: V10
DOCUMENT NO.:Design Name = 98860_1_12M13_201905302120Size D

Sheet 40 of 65
5 4 3 2 1
5 4 3 2 1
ASM_LMB
D D
VBAT_RF [67]
2
N2
TVS6201
C6202 C6203 C6204 C6205
ESD5651N-2/TR
100pF;5%;50V;0201 1000pF;20%;50V;0201 10uF;20%;6.3V;0402 10uF;20%;6.3V;0402
N1
[62] RF_MLB_TXDET_SPDT
1
VRAMP_ASM R6201
19
17
38
23
21
20
18
16
15
14
13
12
11
APC1 [3]
0;0.5A;0201
NC1
CPL
GND13
GND12
GND11
GND10
GND9
GND8
GND7
GND6
GND5
GND4
GND3
LTE_VMIPI [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,67,70,84]
C6221 C6222
C6207 10
RF_AntMLB_TRX_ASM_OUT
22 VBATT C0201_NC C0201_NC C6210
[61] RF_AntMLB_TRX_RFSWITCH ANT 9
VCC 1000pF;20%;50V;0201
100pF;5%;50V;0201
8
VRAMP
L6202 L6203 7
L0201_NC L0201_NC VIO
24 U6201 6 ASM_MIPI_DATA R6202
NC2 SDATA MIPI1_SDATA [3]
25 5 ASM_MIPI_CLK 0;0.5A;0201
NC3 VC7912-53 SCLK C6209
26 4
NC4 GND2
27 3 RF_2GHB_TX_ASM_IN C0201_NC
[65] RF_B2_TRX_TXM TRX10 TX_HB_IN
28 2 RF_2GLB_TX_ASM_IN
[65] RF_B4_TRX_TXM TRX9 TX_LB_IN
29 1 R6203
[65] RF_B1_TRX_TXM TRX8 GND1 MIPI1_SCLK [3]
30 0;0.5A;0201
[65] RF_B3_TRX_TXM TRX7 C6208
GNDP1
TRX6
TRX5
TRX4
TRX3
TRX2
TRX1
C0201_NC
NC5
C6211 C6212
31
32
33
34
35
36
37
39
RF_2GHB_TX_RFIC_MATCH
RF_2GHB_TX_RFIC_OUT [58]
[64] RF_B28B_TRX_TXM
22pF;5%;50V;0201 22pF;5%;50V;0201
C
[64] RF_B5_TRX_TXM
C6213 C6214 GSM_HB C
[64] RF_B8_TRX_TXM C0201_NC C0201_NC
[64] RF_B28A_TRX_TXM C6215 C6216
[64] RF_B20_TRX_TXM RF_2GLB_TX_RFIC_MATCH
RF_2GLB_TX_RFIC_OUT [58]
[65] RF_DCSPCS_PRX_TXM
100pF;5%;50V;0201 100pF;5%;50V;0201
C6217
C0201_NC
C6218
C0201_NC
GSM_LB
RF_2GLB_TX_NOTCH
C6201
C0201_NC
ASM_HB ASM_CPL_SPDT
[67] RF_B41_TRX_TXM
[67] RF_B40_TRX_TXM
B U6202 B
11
10
8
MXD8641
NC3
RF4
RF2
NC2
FL6201 Note1:
12
C6223 C6219 NC4 7
RF_AntHB_TRX_COUPLER_MATCH RF_AntHB_TRX_COUPLER_OUT 6 1 RF_AntHB_TRX_ASM_OUT 13 V1
[61] RF_AntHB_TRX_RFSWITCH Main Out IN ANT
Note2:
100pF;5%;50V;0201 100pF;5%;50V;0201 5 2 14 6 BPI_BUS5 [3]
GND2 GND1 NC5 V2
L6208 4 3 15
L6201 Termination Coupled Out RF_HB_TXDET_SPDT [62] GND BPI_BUS4 [3]
82nH;5%;0201 L6209 5
RF_HB_CPL_TER
L0201_NC V3
L0201_NC
VDD
NC1
U6203
RF3
RF1
CP1608-24R0822T/LF
C6227 C6228 1 6 BPI_BUS1 [3]
[62] RF_HB_TXDET_SPDT RF2 V1
100pF;5%;50V;0201 100pF;5%;50V;0201
4
2 5
GND ANT RF_TXDET_SPDT [58]
3 4
R6206 [62] RF_MLB_TXDET_SPDT RF1 VDD LTE_VFE28 [62,67,69,70,72,73]
51;5%;0201 LTE_VFE28 [62,67,69,70,72,73]
MXD8621C
C6231 C6229
[65] RF_B7_TRX_TXM C6225
100pF;5%;50V;0201
MXD8641 100pF;5%;50V;0201 100pF;5%;50V;0201
[65] RF_B4_PRX_TXM
V2 V3 Operating mode
L L RF1 TO ANT MXD8621C
L H RF2 TO ANT V1 Operating mode
H L RF3 TO ANT L RF1 TO ANT
H H RF4 TO ANT H RF2 TO ANT
Note1: MXD8641 V1 CAN GROUD CONFIRMED WITH FAE
Note2: MUST BE IND FOR RF SWITCH DETECT

A A
Title Page Name = 62_Primary_ASM REV: V10
DOCUMENT NO.: Size D

Design Name = 98860_1_12M13_201905302120

Sheet 41 of 65
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title
<Title>

A1 <Doc> 1.0
5 4 3 2 1
5 4 3 2 1
[67] RF_B5_PA_DPX
B5 PRX
FL6401
D5DA881M5K2E4
L6401
D RF_B5_TRX_DPX 6 3 D
[62] RF_B5_TRX_TXM ANT TX C6401 L6402
1.0NH;0.1nH;0201 1 RF_B5_PRX_DPX_RFIP1 RF_B5_PRX_MATCH
RX RF_B5_PRX_RFIC [58]
GND1
GND2
GND3
GND4
GND5
5.1NH;3%;0201
L6403 L6420 33pF;5%;50V;0201
L0201_NC 8.2NH;3%;0201 L6404 C6402
2
4
5
7
8
D5DA881M5K2E4 FOR ROW 10NH;3%;0201 L0201_NC
B39881B8626P810 FOR BR/LA
[67] RF_B28B_PA_DPX
FL6404
SAYEY733MBC0F0A
B28B PRX
R6404
RF_B28B_TRX_DPX 6 3
[62] RF_B28B_TRX_TXM ANT TX C6408 L6413
100pF;5%;50V;0201 1 RF_B28B_PRX_DPX_RFIP1 RF_B28B_PRX_MATCH
RX RF_B28B_PRX_RFIC [58]
GND1
GND2
GND3
GND4
GND5
1.0NH;0.1nH;0201
2.2pF;0.25pF;50V;0201
L6412 L6414
2
4
5
7
8
L0201_NC 8.2NH;3%;0201 L6415
C6409
15NH;3%;0201
L0201_NC
C C
[67] RF_B28A_PA_DPX
FL6402
B28A PRX
SAYEY718MBC0F0A
RF_B28A_TRX_DPX 6 3
[62] RF_B28A_TRX_TXM ANT TX C6403 L6405
R6402 1 RF_B28A_PRX_DPX_RFIP1 RF_B28A_PRX_MATCH
RX RF_B28A_PRX_RFIC [58]
GND1
GND2
GND3
GND4
GND5
33pF;5%;50V;0201
3.3NH;0.1nH;0201
33pF;5%;50V;0201
L6408 L6406
2
4
5
7
8
L0201_NC 8.2NH;3%;0201 C6404
L6407
L0201_NC
L0201_NC
B8 PRX
[67] RF_B8_PA_DPX
FL6403
SFX897EYT02
B R6403 B
RF_B8_TRX_DPX 6 3 L6409
[62] RF_B8_TRX_TXM ANT TX C6405
33pF;5%;50V;0201
1 RF_B8_PRX_DPX_RFIP1 RF_B8_PRX_MATCH
18pF;5%;50V;0201 RX RF_B8_PRX_RFIC [58]
GND1
GND2
GND3
GND4
GND5
1.8pF;0.05pF;50V;0201
L6410 L6411
L0201_NC 9.1NH;3%;0201
2
4
5
7
8
C6406
C6407
6.8NH;3%;0201
6.2NH;3%;0201
B20 PRX
RF_B20_PRX_DPX_RFIP1
[67] RF_B20_PA_DPX
C6410
R6401 RF_B20_PRX_LPF_COMM
FL6405
0;0.5A;0201
B39851B8622P810
R6405 2.7pF;0.25pF;50V;0201
Note1: FL6406 Note1:
33pF;5%;50V;0201
RF_B20_TRX_DPX 6 3 RFLPF10050G9DM1T76
[62] RF_B20_TRX_TXM ANT TX C6412 C6413
L6416
1 RF_B20_PRX_LPF_IN6 4 RF_B20_PRX_LPF_OUT RF_B20_PRX_MATCH
RX INPUT OUTPUT RF_B20_PRX_RFIC [58]
GND1
GND2
GND3
GND4
GND5
GND1
GND2
L6417 L6418
33pF;5%;50V;0201
NC1
NC2
L0201_NC C0201_NC C0201_NC

10NH;3%;0201 C6411
Note1: COMPATIBLE DESIGN FOR LPF,AND SHARE PAD IN PCB
2
4
5
7
8
B39851B8622P810 FOR ROW 6.8NH;3%;0201

D5DA737M5K2H2 FOR BR/LA
1
3
2
5
C6414
12NH;3%;0201
A A
Title Page Name = 64_TRX_LB REV: V10

Design Name = 98860_1_12M13_201905302120

Sheet 43 of 65
5 4 3 2 1
5 4 3 2 1
[67] RF_B1_PA_DPX
D FL6503 [67] RF_B7_PA_DPX D
B39212B8651P810
L6522
33pF;5%;50V;0201 FL6505
RF_B1_TRX_DPX 6 3
[62] RF_B1_TRX_TXM ANT TX L6531
C6516 SAYEY2G53BA0F0A
1 RF_B1_PRX_DPX_RFIP1 RF_B1_PRX_MATCH
RX RF_B1_PRX_RFIC [58] L6528
GND1
GND2
GND3
GND4
GND5
33pF;5%;50V;0201 18pF;5%;50V;0201 RF_B7_TRX_DPX 6 3 C6511
[62] RF_B7_TRX_TXM ANT TX 3.3pF;0.25pF;50V;0201
L6524 C6517 L6532 1.2NH;0.1nH;0201 1 RF_B7_PRX_DPX_RFIP1 RF_B7_PRX_MATCH
RF_B7_PRX_RFIC [58]
2
4
5
7
8
RX
GND1
GND2
GND3
GND4
GND5
L6523 3.0NH;0.1nH;0201 L0201_NC 1.5NH;0.1nH;0201
L0201_NC L6530 L6518
L6529 2.7NH;0.1nH;0201 8.2pF;0.25pF;50V;0201
C6513
L0201_NC C6512
2
4
5
7
8
2.4NH;0.1nH;0201 2.0NH;0.1nH;0201
B1 PRX
B7 PRX
[67] RF_B4_PA_DPX
[67] RF_B3_PA_DPX
FL6502
B4 PRX
D6DA1G842K2C4 FL6504
C L6512 C
SAYEY1G73BA0F0A
RF_B3_TRX_DPX 6 3 C6508 L6515
[62] RF_B3_TRX_TXM ANT TX C6510
2.7pF;0.25pF;50V;0201 22pF;5%;50V;0201
1.0NH;0.1nH;0201 1 RF_B3_PRX_DPX_RFIP1 RF_B3_PRX_MATCH RF_B4_TRX_DPX 6 3 L6535 C6503 L6506
RX RF_B3_PRX_RFIC [58] [62] RF_B4_TRX_TXM ANT TX
GND1
GND2
GND3
GND4
GND5
C0201_NC 18pF;5%;50V;0201 33pF;5%;50V;0201
L6513 L6514 L0201_NC 1 RF_B4_PRX_DPX_RFIP1 RF_B4_PRX_MATCH
RX RF_B4_PRX_RFIC [58]
GND1
GND2
GND3
GND4
GND5
L0201_NC 4.3NH;3%;0201 L6517
1.8NH;0.1nH;0201 L6519 L6520
2
4
5
7
8
L6516 L0201_NC L0201_NC C6505
2.4NH;0.1nH;0201 L0201_NC
2
4
5
7
8
C6504
RF_B4_PRX_SAW_COMM
L0201_NC
B3 PRX
Note1:
FL6506 SAFFB2G14AA0F0A L6536

L6533
22pF;5%;50V;0201
RF_B4_TRX_SAW 1 4 RF_B4_PRX_SAW_OUT
[62] RF_B4_PRX_TXM UNBL1 UNBL2
1.0NH;0.1nH;0201
GND1
GND2
GND3
L6534
L0201_NC
5
[67] RF_B2_PA_DPX
B2 PRX FL6501
SAYEY1G88BA0B0A
L6504
RF_B2_TRX_DPX 6 3
[62] RF_B2_TRX_TXM ANT TX C6514 L6525 FL6507
1.0NH;0.1nH;0201 1 RF_B2_PRX_DPX_RFIP1 RF_B2_PRX_MATCH
RX RF_B2_PRX_RFIC [58] RFBPF16081G9DMAT79
GND1
GND2
GND3
GND4
GND5
B L6505 L6507 1.8pF;0.05pF;50V;0201 18pF;5%;50V;0201 C6502 C6501 L6501 B

L0201_NC 4.3NH;3%;0201 RF_DCSPCS_PRX_BPFIN
1 3 RF_DCSPCS_PRX_BPFOUT RF_DCSPCS_PRX_MATCH
[62] RF_DCSPCS_PRX_TXM IN/OUT1 IN/OUT2 RF_DCSPCS_PRX_RFIC [58]
2
4
5
7
8
L6526 L6527 1.0NH;0.1nH;0201
GND2
GND1
1.8pF;0.05pF;50V;0201 18pF;5%;50V;0201
2.7NH;0.1nH;0201 1.5NH;0.1nH;0201
C6506 C6507
L0201_NC L0201_NC L6503
2
1.5NH;0.1nH;0201
Note1: COMPATIBLE DESIGN FOR B4 PRX SAW AND DUPLEXER,AND SHARE PAD IN PCB
Band Note:
FL4704 FL4701 FL4707 FL4701 FL4702 FL4703 FL4702 FL4601 FL4602 FL4604 FL4603 U4802 U4805
China B1 B3 G1900 B34/39 B5 B8 B40 B38/B41
CMCC B1 B2 B3 G1900 B7 B34/39 B5 B8 B40 B38/B41
A A
Asia Pacific Simple B1 B3 G1900 B5 B8 B40 B38/B41

Asia Pacific B1 B3 G1900 B7 B5 B8 B40 B38/B41
Overseas Full Band B1 B3 B20 G1900 B7 B5 B8 B28A B28B B40 B38/B41 Title
Page Name = 65_TRX_MHB REV: V10
DOCUMENT NO.: Size

Design Name = 98860_1_12M13_201905302120 D

Sheet 44 of 65
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title
<Title>

A1 <Doc> 1.0
5 4 3 2 1
5 4 3 2 1
B28B R6722
[2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] VIO18_PMU
[64] RF_B28B_PA_DPX RF_B28B_PA_PA_OUT [67]
L6733 0;0.5A;0201
C0201_NC R6704
390K;1%;0201
L6724
L6723 7.5NH;3%;0201
L0201_NC
L6734
[3] AUX_IN1_NTC
L0201_NC
D B28A L6732
RT6704
100K;1%;0402
D
RF_B28A_PA_DPX_MATCHR6723
[64] RF_B28A_PA_DPX RF_B28A_PA_PA_OUT [67]
6.8NH;3%;0201
0;0.5A;0201
L6703 L6726
L0201_NC 1.5NH;0.1nH;0201 GND
L6727
C0201_NC
B8 TX R6724
[64] RF_B8_PA_DPX RF_B8_PA_PA_OUT [67]

12pF;5%;50V;0201
L6729
L6728 7.5NH;3%;0201
22NH;3%;0201
Power Net Connection
B5 TX R6719
RF_B5_PA_DPX_MATCH
R6720
RF_B5_PA_PA_OUT [67]
[2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84] LTE_VMIPI VIO18_PMU [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84]
[64] RF_B5_PA_DPX L6725

C6730
[67] RF_B20_PA_PA_OUT RF_LB_TX_RFIC_PA_MATCH
0;0.5A;0201 0;0.5A;0201 RF_LB_TX_RFIC_OUT [58]
L6721 C6728 C6729 [67] RF_B28A_PA_PA_OUT
9.1NH;3%;0201 33pF;5%;50V;0201
C0201_NC C0201_NC 2.7pF;0.25pF;50V;0201 [67]
[67]
RF_B8_PA_PA_OUT
RF_B5_PA_PA_OUT
C6731 C6732
V28 to FEM
3.3pF;0.25pF;50V;0201 3.3pF;0.25pF;50V;0201
B20 TX C6735
RF_B20_PA_DPX_MATCH
R6725
RF_B20_PA_PA_OUT [67]
[67]
[67]
RF_B28B_PA_PA_OUT
RF_B3_PA_PA_OUT R6718
C6751 [62,69,70,72,73] LTE_VFE28
SH6712
L1 VFE28_PMU [8,48]
[64] RF_B20_PA_DPX 33pF;5%;50V;0201
12pF;5%;50V;0201 [67] RF_B1_PA_PA_OUT RF_MB_TX_RFIC_PA_MATCH
L6730 0;0.5A;0201 RF_MB_TX_RFIC_OUT [58]
L6722 [67] RF_B2_PA_PA_OUT 4.3NH;3%;0201
7.5NH;3%;0201
L0201_NC [67] RF_B4_PA_PA_OUT
RF_LB_TX_RFIC_PA_IN
L6731 C6726 C6727
RF_MB_TX_RFIC_PA_IN
C0201_NC [7,67] VPA_VCC2
1.0pF;0.05pF;50V;0201 1.0pF;0.05pF;50V;0201
56
55
54
21
20
19
18
17
16
53
52
51
C6710 C6709
0.47UF;20%;6.3V;0201 100pF;5%;50V;0201
VBAT_RF [62,67] VBAT to TXM SH6711
GNDP14
GNDP13
GNDP12
MB1
LB5
LB1
LB2
LB3
LB4
GNDP11
GNDP10
GNDP9
C C
TVS6702
2
VBATT_MMMBPA
15 [62,67] VBAT_RF L1 VBAT [13,36,47]
GND3
N2
[7,67] VPA_VCC1 14
R6717 22 RFIN_L2 13 C6721 C6722
23 GND4 RFIN_L1 12 C6723
MB2 RFIN_M
N1
[65] RF_B3_PA_DPX RF_B3_PA_PA_OUT [67] C6711 C6712 24 11 100pF;5%;50V;0201 0.1uF;20%;6.3V;0201 4.7uF;20%;6.3V;0402
100pF;5%;50V;0201 25 GND5 NC4 10
2.0NH;0.1nH;0201 0.47UF;20%;6.3V;0201 MB3 VC7643-62 NC3
B3 TX 26 9 NF_PTVS4V5D1BL
1
C6724 27 MB4 NC2 8
L0201_NC C6725 28 GND6 U6702 VBATT 7
4.3NH;3%;0201 VCC2_2 VIO MMMBPA_MIPI_SCLK LTE_VMIPI [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70,84]
29 6 R6714 0;0.5A;0201
VCC1 SCLK MMMBPA_MIPI_DATA MIPI0_SCLK [3]
[7,67] VPA_VCC2 30 5
VCC2 SDATA MIPI0_SDATA [3]
31 4
RF_HB_TX_RFIC_PA_IN
32 GND7 NC1 3
R6711 33 MB5 RFIN_H 2
C6713 C6714
100pF;5%;50V;0201 34 HB1 GND2 1 C6720 C6718 C6717
[65] RF_B1_PA_DPX RF_B1_PA_PA_OUT [67] 0.47UF;20%;6.3V;0201 GND8 GND1
35
36 HB2 1000pF;20%;50V;0201 C0201_NC C0201_NC
B1 TX 0;0.5A;0201 GND9 [7,67] VPA_VCC1
GNDP1
GNDP2
GNDP3
GNDP4
GNDP5
GNDP6
GNDP7
GNDP8
GND10
GND11
HBRX1
HBRX2
L6719 L6720
HB3
HB4
L0201_NC 4.3NH;3%;0201
R6710 C6719
RF_HB_TX_RFIC_PA_MATCH
RF_HB_TX_RFIC_OUT [58]
37
38
39
40
41
42
43
44
45
46
47
48
49
50
[67] RF_B7_PA_PA_OUT 3.3NH;0.1nH;0201
8.2pF;0.25pF;50V;0201
[67] RF_B41_PA_PA_OUT 60mil
R6713 60mil
C6715 [7,67] VPA_VCC2 VPA_PMU [7]
C6716
0;0.5A;0201 1.2pF;0.1pF;50V;0201
[67] RF_B40_PA_PA_OUT 1.2pF;0.1pF;50V;0201
L6717
B4/B66 TX L0201_NC L6718
4.3NH;3%;0201
C6734
1.0UF;20%;6.3V;0201
C6733
4.7uF;20%;6.3V;0402
[67] RF_B41B40_PRX_PA_OUT
R6701
1.5NH;0.1nH;0201
L6715
B2 TX L0201_NC L6716
4.3NH;3%;0201
B B
B38/41(120M)TRX R6702
F6FC2G595H4PD
U6701
R6703
[62] RF_B41_TRX_TXM RF_B41_TRX_DPX 4 1 RF_B41_PA_DPX
UNBL2 UNBL1 RF_B41_PA_PA_OUT [67]
GND3
GND2
GND1
1.8pF;0.05pF;50V;0201
0;0.5A;0201 L6707
L6704 L6705 L6706
L0201_NC 2.4NH;0.1nH;0201 2.4NH;0.1nH;0201 L0201_NC C6738 R6708
R6709
5
RF_B41_PRX_PA_LNA RF_B41_RFIC_MATCH
[67] RF_B41B40_PRX_PA_OUT RF_B41B40_PRX_RFIC [58]
1.2NH;0.1nH;0201 33pF;5%;50V;0201
27pF;5%;50V;0201
C6705 L6713
2.7pF;0.25pF;50V;0201 1.5pF;0.1pF;50V;0201
B40 TRX R6706

885075 U6703
R6707
RF_B40_TRX_DPX 4 1 RF_B40_PA_DPX RF_B40_PA_DPX_MATCH
R6705 0;0.5A;0201
[62] RF_B40_TRX_TXM UNBL2 UNBL1 RF_B40_PA_PA_OUT [67]
GND3
GND2
GND1
0;0.5A;0201 2.7pF;0.25pF;50V;0201
L6712
L6709 L6711 L0201_NC L6708
5
L0201_NC L6710 8.2NH;3%;0201 L0201_NC

8.2NH;3%;0201
B7 TX C6701
[65] RF_B7_PA_DPX
A
RF_B7_PA_PA_OUT [67] A
1.8pF;0.05pF;50V;0201
L6702
L6701 2.4NH;0.1nH;0201
L0201_NC
Title Page Name = 67_RF_MMPA REV: V10

Design Name = 98860_1_12M13_201905302120

Sheet 46 of 65
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title
<Title>

A1 <Doc> 1.0
5 4 3 2 1
5 4 3 2 1
D D
ANT_DIV_FEED
J6901
AT12-110001-04
Note1: J6905
C6905 R6906 L6907 C6910 C6911

1 RF_Ant_DRX_ANT RF_Ant_DRX_ANT_MATCH1 RF_Ant_DRX_ANT_MATCH2 RF_Ant_DRX_RFSWITCH_OUT 2 1
OUT IN RF_Ant_DRX_RFSWITCH [70]
GND2
GND1
2
33pF;5%;50V;0201 33pF;5%;50V;0201 0;0.5A;0201 33pF;5%;50V;0201 33pF;5%;50V;0201
Note2:
C6909 C6096
L6905 R6907 818004112
4
3
82nH;5%;0201 L0201_NC L6903
J6902 L6901
L0201_NC
100nH;5%;0201 33pF;5%;50V;0201 33pF;5%;50V;0201
AT14-110001-04
1 C6907
2 ANT_SAR_DIV [84]
U6902
100pF;5%;50V;0201
9
RF-MXD8546C
RFI2
GND4
RFO2
VCTL
C6908
5 10
GND3 VDD
100pF;5%;50V;0201
GND2
GND1
C C
RFO1
RFI1
4
1
BPI_BUS8
LTE_VFE28
[3] [62,67,69,70,72]
[69] RF_Ant_DRX_DPDT_OUT2
[69] RF_AntMLB_TRX_DPDT_OUT2
C6902
L6923
[84] DIV_ANT_SAR_REF
100nH;5%;0201
33pF;5%;50V;0201
ANT_DIV_TUNER
J6903
B AT14-110001-04 B
Note1:
1 RF_Ant_DRX_SP4T R6908 RF_Ant_DRX_SP4T_RFC
2
J6904
33pF;5%;50V;0201
1
Note2:
AT12-110001-04 NF_PESDUC2XD18VB L6902
N1
TVS6901 82nH;5%;0201
N2
1
2
J6911
10
U6901
AT12-110001-04 4
RFC
[62,67,70,72,73] LTE_VFE28 VDD
[3] BPI_ANT2 5
CTRL1 1 RF_Ant_DRX_SP4T_RF1 R6903
1 0;0.5A;0201
6 RF1
[3] BPI_ANT0 CTRL2 RF_Ant_DRX_SP4T_RF2 R6904 0;0.5A;0201
2
2 RF2
RF_Ant_DRX_SP4T_RF3_L 82nH;5%;0201 RF_Ant_DRX_SP4T_RF3
R6901 BGSA14GN10
RF_Ant_DRX_GND
C6901 C6904 9 L6904 0;0.5A;0201

C6903 7 RF3
100pF;5%;50V;0201 100pF;5%;50V;0201 GND2 R6902
100pF;5%;50V;0201 8 RF_Ant_DRX_SP4T_RF4 0;0.5A;0201
3 RF4
GND1
BGSA14GN10 CTRL1 CTRL2 Operating mode

Note1: L L RF1 TO RFC
L6922
33pF;5%;50V;0201 L H RF2 TO RFC
H L RF3 TO RFC
H H RF4 TO RFC Note1: MUST BE CAP FOR SAR DETECT DESIGN
A A
Note2: MUST BE IND FOR SAR DETECT DESIGN
Note3: 0R RES IS RESERVED FOR SAR SENSOR DESENSE,PLACE CLOSE TO ANTENNA
Note4: share pad in PCB
Title REV:
Page Name = 69_Diversity_ANT V10
DOCUMENT NO.: Size

Design Name = 98860_1_12M13_201905302120 D

Sheet 48 of 65
5 4 3 2 1
5 4 3 2 1
D D
RF_B3_DRX_ASM [72]
RF_B1_DRX_ASM [72]
RF_B7_DRX_ASM [73]
RF_B41_DRX_ASM [73]
RF_B40_DRX_ASM [73]
11
12
13
14
15
16
21
C C
RF5
RF4
RF3
RF2
RF1
GND4
GNDP
10 17 LTE_VFE28 [62,67,69,72,73]
C7007 GND3 VDD
RF_Ant_DRX_ASM_OUT 9 U7001 18
[69] RF_Ant_DRX_RFSWITCH ANT VIO LTE_VMIPI [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,84]
8 19
15pF;5%;50V;0201 GND2 MXD86A0S SDATA MIPI2_SDATA [3,48]
7 20
GND1 SCLK MIPI2_SCLK [3,48]
L7003
L0201_NC L7002
RF10
C7001 C7002 C7004 C7003
RF6
RF7
RF8
RF9
L0201_NC
NC
C0201_NC C0201_NC 33pF;5%;50V;0201 0.01uF;20%;25V;0201
1
RF_B2_DRX_ASM [72]
RF_B28_DRX_ASM [72]
RF_B5_DRX_ASM [72]
RF_B20_DRX_ASM [72]
RF_B8_DRX_ASM [72]
B B
A A
Title REV:
Page Name = 70_Diversity ASM V10

Design Name = 98860_1_12M13_201905302120

Sheet 49 of 65
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title REV: V10

Reserved
5 4 3 2 1
5 4 3 2 1
D D
B1/4/66 DRX L7207 L7208

B2 DRX
L7209 RF_B1B3_DRX_LNA_COMM
RF_B1_DRX_SAW_IN U7205
[70] RF_B1_DRX_ASM 1.5NH;0.1nH;0201 U7206 SAFFB1G96AB0F0A
1.2NH;0.1nH;0201 SFWG42CBB02 22pF;5%;50V;0201 C7223 L7220 C7203
RF_B2_DRX_SAW_IN 1 4 RF_B2_DRX_SAW_OUT RF_B2_DRX_RFIC_MATCH
Note1: [70] RF_B2_DRX_ASM UNBL1 UNBL2 RF_B2_DRX_RFIC [58]
L7210 U7208
1.0NH;0.1nH;0201
GND1
GND2
GND3
7.5NH;3%;0201 1.8pF;0.05pF;50V;0201 18pF;5%;50V;0201
6 1 Note1:
L7218 VEN GND1 L7222 L7229
C7224
6 1 RF_B1B3_DRX_SAW_OUT RF_B1B3_DRX_LNA_IN
5 2 L0201_NC 1.5NH;0.1nH;0201
5
B1 B1 / B3 RFIN VDD C7207 C7206 2.7NH;0.1nH;0201
L7230 L0201_NC 4 3 RF_B1B3_DRX_LNA_OUT RF_B1B3_DRX_RFIC_MATCH
?MHZ
RF_B3_DRX_SAW_IN 9 GND2 RF OUT RF_B1B3_DRX_RFIC [58]
[70] RF_B3_DRX_ASM B3
2.0NH;0.1nH;0201 2 [3] BPI_BUS7 C0201_NC 10PF;5%;50V;0201
GND1 100pF;5%;50V;0201 RTC8606M L7226
L7211
L7270 C7232 L0201_NC 1.5NH;0.1nH;0201
10NH;3%;0201 7 3
B3 DRX 8
GND5
GND6
GND2
GND3
4
L7219
2.7NH;0.1nH;0201
10 5 LTE_VFE28 [62,67,69,70,72,73]
GND7 GND4
1000pF;20%;50V;0201
L7212
C C
B5 DRX
L7201 L7202
U7203 MS11U881M-RX05S
RF_B8_DRX_LNA_COMM L7214 C7208
L7213
7.5NH;3%;0201 RF_B5_DRX_ASM RF_B5_DRX_SAW_IN 1 4 RF_B5_DRX_SAW_OUT RF_B5_DRX_RFIC_MATCH
B8 DRX 22pF;5%;50V;0201
[70] RF_B5_DRX_ASM
4.3NH;3%;0201
UNBL1 UNBL2
8.2NH;3%;0201
RF_B5_DRX_RFIC [58]
GND1
GND2
GND3
15pF;5%;50V;0201
Note1: U7202 L7216
MS11U942M-RX08S Note1: 15NH;3%;0201
5
U7201 6 1 C7209 C7225
C7201 L7204 VEN GND1 1.0pF;0.05pF;50V;0201 15NH;3%;0201
RF_B8_DRX_SAW_IN 1 4 RF_B8_DRX_SAW_OUT RF_B8_DRX_LNA_IN
5 2
[70] RF_B8_DRX_ASM UNBL1 UNBL2 RFIN VDD C7210 C7215
L0201_NC RF_B8_DRX_LNA_OUT RF_B8_DRX_RFIC_MATCH
GND1
GND2
GND3
4 3
33pF;5%;50V;0201 GND2 RF OUT RF_B8_DRX_RFIC [58]
L7205 C0201_NC
L7203 12NH;3%;0201 27pF;5%;50V;0201
L0201_NC [3] BPI_BUS0
RTC8606L L7227
2
330pF;5%;25V;0201 L7206
C7211 L0201_NC
12NH;3%;0201
LTE_VFE28 [62,67,69,70,72,73]
1000pF;20%;50V;0201
B C7214 B
B28 DRX
RF_B20_DRX_LPF_COMM1
Note1:
B20 DRX R7294
0;0.5A;0201
RF_B20_DRX_LPF_COMM
C7229
C7230
RF_B28_DRX_SAW_IN 1
U7207 SAFFB780MAA0F0A
4 RF_B28_DRX_SAW_OUT
L7224 C7231
RF_B28_DRX_RFIC_MATCH
22pF;5%;50V;0201 [70] RF_B28_DRX_ASM UNBL1 UNBL2 RF_B28_DRX_RFIC [58]
Note1: FL7209 4.3NH;3%;0201
GND1
GND2
GND3
RFLPF10050G9DM1T76 U7220 SFH806BA002 33pF;5%;50V;0201 22pF;5%;50V;0201
R7262 C7221 C7222 C7216 C7217
L7223 L7225
RF_B20_DRX_ASM RF_B20_DRX_LPF_IN 6 4 RF_B20_DRX_LPF_OUT RF_B20_DRX_SAW_IN 4 1 RF_B20_DRX_SAW_OUT RF_B20_DRX_RFIC_MATCH 15NH;3%;0201
[70] RF_B20_DRX_ASM RF_B20_DRX_RFIC [58] 15NH;3%;0201
5
INPUT OUTPUT UNBL2 UNBL1 L7217
10NH;3%;0201
GND1
GND2
GND3
GND2
GND1
C0201_NC 1.0pF;0.05pF;50V;0201
39pF;5%;50V;0201
NC1
NC2
0;0.5A;0201 C0201_NC C7218

L7215
C7204 15NH;3%;0201
C7205
1
3
2
5
27nH;3%;0201 C0201_NC
C0201_NC
A A
Note1: COMPATIBLE DESIGN ,AND SHARE PAD IN PCB
Title REV: V10

Page Name = 72_DRX_LMB
DOCUMENT NO.: Size
Design Name = 98860_1_12M13_201905302120 D

Sheet 51 of 65
5 4 3 2 1
5 4 3 2 1
D D
Note1:
L7302 L7303
Note1:
RF_B7_DRX_LNA_COMM
0;0.5A;0201 U7301 0;0.5A;0201
U7302 MS11U2G65-RX07S 6 1
C7304 L7301 VEN GND1
RF_B7_DRX_ASM RF_B7_DRX_SAW_IN 1 4 RF_B7_DRX_SAW_OUT RF_B7_DRX_LNA_IN 5 2
[70] RF_B7_DRX_ASM UNBL1 UNBL2 RFIN VDD L7305 C7305
L0201_NC RF_B7_DRX_LNA_OUT RF_B7_DRX_RFIC_MATCH
GND1
GND2
GND3
4 3
33pF;5%;50V;0201 GND2 RF OUT RF_B7_DRX_RFIC [58]
L0201_NC
L7909 [3] BPI_ANT1 C7302 8.2pF;0.25pF;50V;0201
L7307 RTC8606M
5
5.1NH;3%;0201
5.1NH;3%;0201
C7312
100pF;5%;50V;0201 2.2pF;0.25pF;50V;0201
L7316
L0201_NC
B7 DRX C7301
LTE_VFE28 [62,67,69,70,72]
100pF;5%;50V;0201
C C
U7307 SFHG96AA402 C7310

C7320 L7318
5.6pF;0.25pF;50V;0201
RF_B41_DRX_ASM RF_B41_DRX_SAW_IN 1 4 RF_B41_DRX_SAW_OUT RF_B41_DRX_RFIC_MATCH
[70] RF_B41_DRX_ASM UNBL1 UNBL2 RF_B41_DRX_RFIC [58]
1.5NH;0.1nH;0201
GND1
GND2
GND3
33pF;5%;50V;0201
L7322
3.9NH;0.1nH;0201 C7311
2.2pF;0.25pF;50V;0201 L7319
5
L0201_NC
B38/41 DRX
B B
U7303 SAFFB2G35AA0F0A
L7309 C7321 C7322
RF_B40_DRX_ASM RF_B40_DRX_SAW_IN 1 4 RF_B40_DRX_SAW_OUT RF_B40_DRX_RFIC_MATCH
[70] RF_B40_DRX_ASM UNBL1 UNBL2 RF_B40_DRX_RFIC [58]
GND1
GND2
GND3
6.8pF;0.25pF;50V;0201
27pF;5%;50V;0201 6.8pF;0.25pF;50V;0201
C7314 L7314
L7312
9.1NH;3%;0201 3.9NH;0.1nH;0201 1.5NH;0.1nH;0201
2
B40 DRX
A A
Note1: COMPATIBLE DESIGN ,AND SHARE PAD IN PCB
Title Page Name = 73_DRX_HB REV: V10
DOCUMENT NO.: Size

Design Name = 98860_1_12M13_201905302120 D
DEPARTMENT: DEPARTMENT = WINGTECH-SZ DESIGNER: DESIGNER = LIUFENGLEI

Sheet 52 of 65
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title
<Title>

A1 <Doc> 1.0
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title REV: V10

Reserved
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title REV: V10

Reserved
5 4 3 2 1
5 4 3 2 1
D D
[77] AVDD18_WBT
C7701 0.1uF;20%;6.3V;0201
CONN_BT_DATA
CONN_BT_DATA [4]
C7702 100pF;5%;50V;0201 CONN_BT_CLK
CONN_BT_CLK [4]
CONN_WF_CTRL0
CONN_WF_CTRL0 [4]
CONN_WF_CTRL1
U7702 CONN_WF_CTRL1 [4] L7712
CONN_WF_CTRL2
30
29
28
27
26
25
24
23
22
21
CONN_WF_CTRL2 [4]
[77] FM_AVDD28 VCN28_PMU [8,79]
WIFI_AUX_2G
WB_VDET_2G
WIFI_VDET_5G
AVDD18_WBT2
AVDD18_WBT1
BT_DATA
BT_CLK
WF_CTRL0
WF_CTRL1
WF_CTRL2
120ohm;200mA;0201
C7718
1.0UF;20%;6.3V;0201
31 20 WF_IP
[78] RF_WB_TRX_ANT WB_RF_2G WF_IP WF_IP [4]
R7711 0;0.5A;0201
[77] AVDD18_GPS VCN18_PMU [8]
[77] AVDD33_WBT
Note4: 32 19 WF_IN
C NC1 WF_IN WF_IN [4] C
C7719
C7703 4.7uF;10%;10V;0603 1.0UF;20%;6.3V;0201
R7712 0;0.5A;0201
33 18 WF_QP [77] AVDD18_WBT
C7704 100pF;5%;50V;0201
AVDD33_WBT WF_QP WF_QP [4]
34 17 WF_QN
WF_RF_5G WF_QN WF_QN [4]
R7768 0;1A;0402
35 16 BT_IP [77] AVDD33_WBT VCN33_PMU [8]
WF_AUX_5G Note2: BT_IP BT_IP [4]
[77] FM_AVDD28
C7707 0.01uF;20%;25V;0201 36
AVDD28_FM
MT6631N/A BT_IN
15 BT_IN
BT_IN [4]
Note1:
L7705 L0201_NC
37 Note3: 14 BT_QP
[39] FM_ANT_N FM_LANT_N BT_QP BT_QP [4]
L7709
[39] RF_FM_ANT_WCN
82nH;5%;0201
FM_LANT_P 38
FM_LANT_P
MT6631N BT_QN
13 BT_QN
BT_QN [4]
L7704 39 12 GPS_I
L0201_NC [79] RF_GPS_RX_RFIN GPS_RFIN GPS_IP GPS_I [4]
40 11
[77] AVDD18_GPS AVDD18_GPS GPS_IN
AVDD28_FSOURCE
CONN_TOP_DATA
C7711
CONN_TOP_CLK
CONN_HRST_B
4700pF;20%;6.3V;0201 41
DVSS
GPS_QN
WB_PTA
GPS_QP
XO_IN
CEXT
NC2
1
10
MT6631_CEXT
MT6631
C7714
[4] CONN_HRST_B GPS_Q

100pF;5%;50V;0201 GPS_Q [4]
[4] CONN_TOP_DATA
B [4] CONN_TOP_CLK RF_MT6631_XO_IN B
[4] CONN_WB_PTA C7713
R7701 0;0.5A;0201
1.0UF;20%;6.3V;0201 PMIC_CLK_WCN [11]
R7702 0;0.5A;0201
XIN_WBG [4]
A Note1: If WiFi 5G were no need, VCN33 could be chosen from PMIC output (VCN33_PMU) A
Note2: If WiFi 5G not support, connect pin 34(WF_RF_5G) to GND
Note3: Pin 36 (AVDD28_FM) must be connected to VCN28 even if FM not support
Title REV: V10

Page Name = 77_WCN_MT6631
Note4: 0603 package use 802167100028
Design Name = 98860_1_12M13_201905302120

Sheet 56 of 65
5 4 3 2 1
5 4 3 2 1
D D
WIFI GPS ANT

R7801 Note1:
J7801
AT12-110001-04
C0201_NC
J7802
1 FL7810 DP1608-V1524CAT F6HG2G441EG65 U7801
L7801 C7801 L7802 R7803 R7804
2 RF_WBG_TRX_ANT RF_WBG_TRX_ANT_MATCH RF_WBG_TRX_RFSWITCH_OUT
2 1 RF_WBG_TRX_RFSWITCH_IN RF_WBG_TRX_DIP_OUT
5 1 RF_WB_TRX_DIP_IN RF_WB_TRX_SAW_OUT
4 1 RF_WB_TRX_SAW_IN
OUT IN COMMON H_PORT UNBL2 UNBL1 RF_WB_TRX_ANT [77]
1.0NH;0.1nH;0201 1.0NH;0.1nH;0201
GND2
GND1
GND3
GND2
GND1
33pF;5%;50V;0201 3.9pF;0.05pF;50V;0201 33pF;5%;50V;0201
L7804 L7809 L7805 L7806
GND1
GND2
GND3
C7802 C7803 3
C7804 L_PORT RF_GPS_RX_DIP_OUT [79]
L7807
L7808
C0201_NC C0201_NC 818004112 6.8NH;3%;0201
J7805 C0201_NC L0201_NC
4
3
2
2
4
6
AT12-110001-04
L0201_NC L0201_NC L0201_NC 6.8NH;3%;0201
C C
B B
A Note1: COMPATIBLE DESIGN FOR WBG RF SWITCH, USE 0R AFTER MP A

Title REV: V10
Reserved
5 4 3 2 1
5 4 3 2 1
D D
R7903 R0201_NC RF_GPS_RX_POST_SAW_COMM R7904 R0201_NC
Note1: Note1:
U7901 U7903 SAFFB1G56KB0F0A RF_GPS_ATT
1 6 RF_GPS_RX_LNA_OUT R7902 0;0.5A;0201 RF_GPS_RX_POST_SAW_IN1 4 RF_GPS_RX_POST_SAW_OUT

R7905 0;0.5A;0201 R7901 0;0.5A;0201 RF_GPS_RX_RFIN [77]
GND1 RFOUT UNBL1 UNBL2
U7902 SAFFB1G56KB0F0A
GND1
GND2
GND3
2 5
C7902 L7902 GND2 EN C7903 C7904
C7909 C7910 R0201_NC R0201_NC
C7901 18pF;5%;50V;0201 RF_GPS_RX_SAW_IN 4 1 RF_GPS_RX_SAW_OUT RF_GPS_RX_SAW_MATCH RF_GPS_RX_LNA_IN 3 4
[78] RF_GPS_RX_DIP_OUT UNBL2 UNBL1 RFIN VCC R0201_NC R0201_NC
GPS_LNA_EN
5
9.1NH;3%;0201
GND3
GND2
GND1
18pF;5%;50V;0201
AW5005DNRZ
GPS_LNA_VCC
C7906
L7903 C7905
2
C0201_NC L7904
L0201_NC L0201_NC [8,77] VCN28_PMU L7901
RF_GPS_NOTCH GPIO_GPS_LNA_EN [4]
100nH;5%;0201
100nH;5%;0201
C7911 C7907 C7908
C C
C0201_NC 0.01uF;20%;25V;0201
0.01uF;20%;25V;0201
B B
A Note1: COMPATIBLE DESIGN FOR GPS POST SAW,SHARE PAD IN PCB

A
Title REV: V10
Reserved
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title REV: V10

Reserved
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title REV: V10

Reserved
5 4 3 2 1
5 4 3 2 1
4 4
3 3
2 2
1 1
Title REV: V10

10_BB_ POWER_PDN
DEPARTMENT: WINGTECH-SZ DESIGNER: LIUFENGLEI
5 4 3 2 1
If SYS CLKis used, the SYS_CLK_REQ signal needs to be

connected to the host GPIO pin that configures as
SRCLKENAI mode and this pin must be default low
NOTE6:
C8218/C8219 place close to XIN/XOUT Balls (less than 5mm)
5 4 3 2 1
D D
C C
B B
A A
Title REV: V10

Reserved
5 4 3 2 1
5 4 3 2 1
D [69] ANT_SAR_DIV
C8443
1K;5%;0201
R8492
D
C0201_NC
R8457 560;5%;0201
[69] ANT_SAR_DIV_SEM
[48] LMB_ANT_SAR_PRI
C8444
C0201_NC
R8491 560;5%;0201
[48] LMB_ANT_SAR_PRI_SEM SAR_NIRQ_ABO [84]
R8478
[48] LMB_ANT_SAR_REF
C8445
1K;5%;0201
R8459
ABOV SAR IC C8439
C0201_NC
C0201_NC
U8401
1K;5%;0201
R8488 SAR_IC_PIN10 10 1 SAR_IC_PIN1
CS3/DSDA/P10 CS4/DSCL/P11
[48] LMB_ANT_SAR_REF_SEM SAR_IC_PIN9 9 2 R8486 R0201_NC
560;5%;0201 CS1/P03 INT0/P12 [84] SAR_NIRQ_SEM SAR_INT [4]
SAR_IC_PIN8 [84] SAR_NIRQ_ABO R8487 0;0.5A;0201
R8479 1K;5%;0201 8 3
[48] HB_ANT_SAR_PRI CS0/P02 VSS R8431 2.2K;5%;0201 VIO18_PMU [2,3,4,6,8,10,13,15,17,32,37,39,40,43,44,45,47,48,58,61,62,67,70]
C8446 SAR_IC_PIN7 7 4
C0201_NC CS7/P01 VDDEXT
SAR_IC_PIN4 R8477 0;0.5A;0201
6 5 VIO28_PMU [8,44]
R8489 SCL/P14 SDA/P13
[48] HB_ANT_SAR_PRI_SEM RF-A96T346DFP
560;5%;0201 C8403 C8404
1.0uF;10%;6.3V;0402
R8480 1K;5%;0201
[69] DIV_ANT_SAR_REF 0.1uF;20%;6.3V;0201
C8447
C0201_NC
R8490
[69] DIV_ANT_SAR_REF_SEM
560;5%;0201
SAR_I2C_SDA_ABOV R8495
R8494 SDA3 [4,37]
SAR_I2C_SCL_ABOV
[84] SCL3 0;0.5A;0201
0;0.5A;0201
C8436 C8438
C0201_NC C0201_NC
C C
R0201_NC
SAR_I2C_SCL_SEM
SCL3 [84]
R8493
C8437
C0201_NC
[84] SAR_NIRQ_SEM
SEM SAR IC
R8433
C8440 SDA3 [4,37]
B C0201_NC
10
U8402
NIRQ SCL
1
SAR_I2C_SDA_SEM
C8430
C0201_NC
0;0.5A;0201
B
9 2
[69] DIV_ANT_SAR_REF_SEM CSIO4 SDA
8 3
[48] HB_ANT_SAR_PRI_SEM CSIO3 CSIO2 ANT_SAR_DIV_SEM [69]
7 4 R8496 0;0.5A;0201
[48] LMB_ANT_SAR_REF_SEM CSIO0 VDD VIO28_PMU [8,44]
6 5
[48] LMB_ANT_SAR_PRI_SEM CSIO1 GND C8442
C8441
RF-SX9331_1 0.1uF;20%;6.3V;0201 1.0uF;10%;6.3V;0402
A A
Title REV: V10

Reserved
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title REV: V10

Reserved
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title REV: V10

Reserved
5 4 3 2 1

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5 4 3 2 1

C103 22uF;20%;6.3V;0603 MT6771-SBS C104 22uF;20%;6.3V;0603

C115 1.0UF;20%;6.3V;0201 C116 1.0UF;20%;6.3V;0201

[8] DVDD_SRAM_CORE [8] DVDD_SRAM_PROC_B

[7,8,17,18] EMI_VDD2 C143 22uF;20%;6.3V;0603

C148 1.0UF;20%;6.3V;0201 C149 1.0UF;20%;6.3V;0201

C150 1.0UF;20%;6.3V;0201 C151 1.0UF;20%;6.3V;0201

C152 1.0UF;20%;6.3V;0201 C153 1.0UF;20%;6.3V;0201

VDDQ VPROC2 SRAM

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Thursday, May 30, 2019 Sheet 3 of 65

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Thursday, May 30, 2019 Sheet 4 of 65

VIO18_PMU U101A U101B

LO HI DAT0/DAT1/DAT2 LO HI LPDDR4X(Ext x 2 EN)

Schematic design notice of "13_BB_2" page.

Title 04_BB_2_MIPI&GPIO REV: V10

DOCUMENT NO.: Design Name Size D

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Thursday, May 30, 2019 Sheet 6 of 65

EMI1_CA5 D19 F13 EMI1_DQS1_C

Title REV: V10

Date: Thursday, May 30, 2019 Sheet 7 of 65

1. IF used for battery ID,R604 NC,R605=390K

Title REV: V10

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Thursday, May 30, 2019 Sheet 8 of 65

VCORE IN VCORE L703

H15 differential and shielding C713

DOCUMENT NO.: Design Name Size C

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Schematic design notice of "20_POWER_MT6358-Buck" page.

MT6358 Close to PMIC

DIG Power SLDO2

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

PMIC SPI TEST SD Detect pin for VMCH power off

[3] PWRAP_SPI0_CSN F13 L6

Cap close to chip

[9,13,48] VBUS R905 7.5K;1%;0201

Schematic design notice of "22_POWER_MT6358-General"

Date: Thursday, May 30, 2019 Sheet 11 of 65

MT6358 HW trapping for DRAM U701D R1099 0;0.5A;0201

MT6358 R1098 0;0.5A;0201

-AU_HPL and AU_HPR should be routed as single end signal

Schematic design notice of "23_POWER_MT6358-Audio"

HW GPIO configuration Trapping Option VDRAM2 Power source

0 0 1.125V 0.6V LP4X VDRAM1

1 0 1.225V OFF LP3 VDRAM1 Title REV: V10

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Thursday, May 30, 2019 Sheet 12 of 65

N1 XTAL1 3mil trace width AVSS18_AUXADC

P1 XTAL2 3mil trace width

L7 P4 XO_SOC R1102 0;0.5A;0201

P3 XO_WCN R1104 0;0.5A;0201

C1103 C1104 C1105

VRTC28 2.8V 2mA U701H

Title REV: V10

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Thursday, May 30, 2019 Sheet 13 of 65

Title REV: V10

DEPARTMENT: WINGTECH-SH DESIGNER: LIUFENGLEI

Date: Thursday, May 30, 2019 Sheet 14 of 65

Title 13_POWER_MT6370-Charger + PP REV: V10