Int. J. Electron. Commun.

(AEÜ) 142 (2021) 153985

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International Journal of Electronics and Communications

journal homepage: www.elsevier.com/locate/aeue

Regular paper

Design framework for inverter cascode transimpedance amplifier using

Gm/ID based PSO applying design equations
Motaz M. Elbadry a, Mostafa Y. Makkey a, Mohamed Atef a, b, *
a
Electrical Engineering Department, Assiut University 71515 Assiut, Egypt
b
Electrical and Communications Engineering Department, United Arab Emirates University, 15551 Al Ain, Abu Dhabi, United Arab Emirates

A R T I C L E I N F O A B S T R A C T

Keywords: This paper presents a framework for the design of the inverter cascode (InvCas) transimpedance (TIA) for the
Particle swarm optimization optical receiver’s front-end. The framework combines the particle swarm optimization (PSO) evolutionary al­
Transimpedance Amplifier gorithm with the gm/ID methodology to calculate the required circuit parameters needed to obtain the target
Gm/ID design methodology
specifications entered by the designer. The framework relies on the derived circuit equations to define the design
Inverter based cascode
space and evaluate the performance using the parameters calculated by the gm/ID and PSO. This technique speeds
Design automation
Analog integrated circuits up the design process by avoiding the need for Spice simulation to assess the fitness of each particle during the
Optical Receivers optimization process. The proposed framework is implemented in a Matlab program utilizing the framework that
Evolutionary computation takes target specifications as an input and provides the design parameters of the particle with the best circuit
performance satisfying these specifications as an output. The framework is tested using the 130 nm CMOS
technology to produce three different designs each targeting a different bandwidth and gain for different optical
communications data rates while optimizing the power and noise performance of each design. All the evaluated
designs achieved the required specifications and show superior performance compared with TIA state-of-the-art.

1. Introduction used in the literature as an example of the power of gm/ID methodology

The continuous decrease in the technology length of CMOS devices
proposes many challenges in designing analog integrated circuits. These
challenges are mainly due to the higher effects of second-order phe­
nomena in devices (i.e., channel length modulation and drain-induced
barrier lowering) [1,2]. The conventional square law model does not
account for these effects which lead to inaccurate relation between the
sizing of the transistors and the final required parameters, often forcing
the designer to use repetitive iterations to reach the required design
specification.
New methodologies have since been proposed to solve this problem
and give a more accurate description of the relation between the size and
parameters of the transistors. From these techniques, the gm/ID meth­
odology has been used because of its ability to utilize charts lookup
tables generated from the parametric sweeps of device parameters
against the inversion level to the transistor (gm/ID), leading to accurate
specifications of the resulting transistor. As a result, it has been used to
design analog circuits to achieve less noise [2-8], decrease overall power
consumption [9-12]. Transimpedance amplifiers (TIA) design has been
in analog design [2,9,13-15].
The charts generated in the gm/ID methodology are usually repre­
sented as lookup tables which are used to retrieve the resulting pa­
rameters of a certain sizing of the devices. The idea of using lookup
tables in the gm/ID methodology is associated with writing a computer
program to find the desired design parameters reaching the needed
specification. Hence, it is much easier to find the optimum value from
the numerous design points in these tables [2,14]. By finding the
equations from circuit analyses describing the relation between tran­
sistor parameters and the resulting specifications, our problem reduces
to finding the optimum point in terms of the correct sizing of the devices.
However, most topologies have a certain degree of trade-off between
their specifications which results in a compromise of one specification in
the favor of another making the design problem has an optimization
nature that relies on the designer’s decision regarding this trade-off.
The use of optimization algorithms has been proposed in the litera­
ture [16-34] to solve this problem because of the wide design space of
the problem along with the complicated relationship between the sizing
of the transistor, their parameters, and the final circuit specifications.

* Corresponding author at: Electrical and Communications Engineering Department, United Arab Emirates University, 15551 Al Ain, Abu Dhabi, United Arab
Emirates.
E-mail addresses: elbadrymotaz@aun.edu.eg (M.M. Elbadry), mymakkey@aun.edu.eg (M.Y. Makkey), moh_atef@uaeu.ac.ae (M. Atef).

https://doi.org/10.1016/j.aeue.2021.153985
Received 6 June 2021; Accepted 24 September 2021
Available online 30 September 2021
1434-8411/© 2021 Elsevier GmbH. All rights reserved.
M.M. Elbadry et al. AEUE - International Journal of Electronics and Communications 142 (2021) 153985

The particle swarm algorithm (PSO) is one of the metaheuristic opti­

mization algorithms. These algorithms are known for trying to simulate
different natural processes to find the solution of a problem. The PSO has
been shown in the literature to obtain better results compared to other
algorithms as the genetic algorithm (GA), ant colony optimization
(ACO), local search (LS), and simulated annealing (SA) [19,23,24]. For
instance, these algorithms require a lot of calculations in comparison
with PSO while being very sensitive to various parameter values and
very dependent on the problem complexity and design space. PSO has a
simple mathematical representation along with the advantage of fast
convergence and being highly immune to the problem formulation in
reaching the solution.
PSO has been implemented extensively in the literature to solve the
analog design problem. The frameworks presented in the literature
mostly use the PSO algorithm, or another hybrid form, with square-law
method [17,19-22,27,29,32,33,30,28]. This suffers from inaccuracy
with respect to the final design specifications. Another technique is to
use the integration between PSO algorithms and circuit simulators such Fig. 1. The testbench for generating charts. (a) NMOS and (b) PMOS.
as Spice to reach the optimum performance [23-26,31,34,18]. But these
methods lead the frameworks to suffer in solving time and computa­
tional requirements.
Optical receivers are one of the most important blocks in analog
design for their countless application in different areas [35,36]. The TIA
is a crucial part of the optical receiver as it has the highest effect on the
resulting specifications by elevating the undesired limitations presented
by the large photodiode capacitance present at the front end of the
circuit [2,36,37]. Hence, finding an optimum point to achieve the bal­
ance between different design specifications is crucial to elevate these
limitations according to the targeted application leading to the imple­
mentation of the gm/ID methodology to achieve this goal [2,9,13-15].
According to our knowledge, PSO has not been used with the gm/ID
methodology to formulate a framework for the design of a TIA for op­
tical sensors or formulate a simulation-free framework that relies on the
design equations and the gm/ID methodology to evaluate the fitness of
each particle during the optimization process. Even the framework
presented in [38] was using the gm/ID methodology with the hybrid PSO
algorithm, the framework still needs Spice simulations to calculate the
final specification instead of using design equations which consequently
leads to more computations.
In this paper, we present a new design framework for the inverter
Fig. 2. The transconductance efficiency (gm/ID) as a function of gate-source
cascode (InvCas) TIA by using the gm/ID methodology and the PSO al­
voltage (VGS) for different inversion levels at VDS = 0.6 V and W = 1 µm. (a)
gorithm. Having the lookup tables from the gm/ID methodology, we can NMOS and (b) PMOS.
test the validity of the design by finding the parameters of the devices for
any given sizing, then calculate the final specifications of the design by
substituting these values in the equations obtained from the circuit an­
alyses. The framework is implemented on a 130 nm CMOS technology, a
MATLAB function is written where the designer enters different design
specifications (i.e., gain, bandwidth, power dissipation, photodiode
capacitance, output capacitance, supply voltage, and input-referred
noise) and the function uses the proposed framework to find the
required parameters of circuit elements. For evaluating the framework,
three designs are produced, each targeting a different application
depending on the resulting bandwidth of the system.
An explanation of the gm/ID is presented in Section 2. The InvCas
circuit is presented in Section 3 where the results of different circuit
analyses are shown. Section 4 presents a review of the PSO optimization
algorithm. The proposed framework is explained in Section 5. The
resulting designs from our framework are presented in Section 6 with
the results of different simulations and comparisons to other works in
the literature. Finally, the conclusion of this paper is presented in Sec­
tion 7.

2. gm/ID methodology

The gm/ID methodology uses tables generated from parametric Fig. 3. The Transit frequency (fT) and intrinsic gain (gm/gds) product as a
function of gm/ID. (a) NMOS and (b) PMOS.
sweeps of different transistor parameters (i.e., transit frequency (fT),

2
M.M. Elbadry et al. AEUE - International Journal of Electronics and Communications 142 (2021) 153985

Fig. 4. The current density (ID/W) as a function of gm/ID. (a) NMOS and (b) PMOS.

intrinsic gain (gm/gds), current density (ID/W), and the intrinsic capaci­
tances of the transistor) versus the gm/ID value of the transistor. The
different values of gm/ID correspond to different inversion levels of the
transistor and the resulting charts are generated from the provided Spice
model for 130 nm CMOS technology. The charts remove the gap be­
tween the equations describing the circuit and the parameters needed to
produce a certain specification.
The gm/ID charts are generated by parametric sweeping the testbench
circuits presented in Fig. 1 along with VDS, VGS, and L. then tabulating
the results against the gm/ID values of the transistor. The device-width
(W) is ignored since the parameters scale almost linearly with respect
to it.
Fig. 2 presents the gm/ID values as a function of different VGS values of
the transistor at a constant VDS and W, while Fig. 3 shows the product of
the gain and transit frequency of the transistor at different gm/ID values
and Fig. 4 shows the log scale of the current density as a function of the
gm/ID values of the transistor.
The gm/ID values typically range between 3 and 30 S/A at different
values of VGS for NMOS and PMOS transistors in submicron technolo­
gies. Higher values of gm/ID correspond to weaker inversion levels and
lower magnitudes of VGS while higher magnitudes and inversion levels
lead to lower values.

Fig. 5. The InvCas circuit. (a) schematic diagram, (b) simplified small-signal model, (c) complete small-signal model, and (d) noise model.

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M.M. Elbadry et al. AEUE - International Journal of Electronics and Communications 142 (2021) 153985

Fig. 2, Fig. 3, and Fig. 4 indicate that biasing the transistors at weak photodiode capacitance is typically very large compared to the load
inversion exhibit a higher gain, a low power consumption, and a higher capacitance and parasitic capacitances of the transistor and the pole
voltage swing but a larger size and a slower speed. When biased at strong resulting from the combination of the photodiode capacitance and the
inversion the transistor obtains a higher speed, a smaller size, a lower input resistance of the InvCas circuit dominate over other poles and
gain, and a decreased voltage swing [1]. This can be explained since, at determine the overall bandwidth of the topology.
higher gm/ID values corresponding to weak inversion, the transistor has a Examining the circuit in Fig. 5(b) we can derive the transimpedance
higher transconductance (gm) and a higher intrinsic (channel) resistance gain of the InvCas as:
leading to a higher gain. At the same time, investigating Fig. 4, this leads
(1 − Gm Rf )r0
to a lower ID/W value which requires a wider transistor to obtain a ZTIA (s) = (3)
sCPD (Rf + r0 ) + Gm r0 + 1
certain drain current (ID) value leading to a higher capacitance and a
slower speed.
where CPD is the photodiode capacitance, Rf is the feedback resistor, and
Gm and r0 can be described by:
3. Modeling of InvCas circuit
Gm = gmn1 + gmp1
The InvCas TIA has been proved in the literature to achieve a great r0 = r0n ‖r0p
(4)
balance between different trade-offs present in the design [39-41]. r0n = gmn2 r0n1 r0n2 + r0n1 + r0n2
Achieving better results than both the common source (CS TIA) and r0p = gmp2 r0p1 r0p2 + r0p1 + r0p2
conventional inverter (Inv TIA), having a higher gain due to the inverter
where gmn1, gmp1, gmn2, and gmp2 are the transconductances of transistors
structure gives it an advantage over the former, and using cascode
Mn1, Mp1, Mn1, and Mp2 respectively and r0n1, r0p1, r0n2, and r0p2 are the
structure to suppress the Miller effect of parasitic capacitances provides
drain to source resistance of transistors Mn1, Mp1, Mn1, and Mp2
a better bandwidth than the latter. It has been implemented in the
respectively.
literature for both biomedical applications for its good noise perfor­
The DC transimpedance gain of the circuit becomes:
mance and high gain [40] as well as optical communications applica­
tions for its good gain-bandwidth product (GBW) [41]. r0 − Gm Rf r0
ZTIA (0) = ≃ − Rf (5)
The InvCas circuit diagram is shown in Fig. 5 (a), the two transistors Gm r0 + 1
Mn1 and Mp1 act as the input transistors, while transistors Mn2 and Mp2
the zero-input resistance is:
are added to provide the cascode structure to the circuit. Adding tran­
sistors Mn2 and Mp2 increases the output impedance of the circuit Rf + r 0
Zin (0) = (6)
achieving higher transimpedance. Moreover, transistors Mn1 and Mp1 Gm r0 + 1
see a resistance of 1/gmn2 and 1/gmp2 which greatly reduces the Miller
from (6), we can derive the approximate bandwidth of the circuit as:
effect and results in a higher bandwidth compared to the Inv TIA [39-
41]. 1 Gm r0 + 1
BWapprox = = (7)
2πZin (0)CPD 2πCPD (Rf + r0 )
A) DC Analysis:
The circuit shown in Fig. 5(c) shows the small-signal model of the
InvCas topology with all parasitics between different nodes considered,
Investigating the circuit diagram present in Fig. 5(a) the power
these parasitics can be described by:
dissipation can be described by:
C1 = CPD + Cgsn1 + Cgsp1
PDiss = VDD ID (1)
C2 = Cgdn2 + Cgdp2 + CL
C3 = Cgsn2 + Cdbn1
where VDD the voltage of the power supply, and ID is the drain current of C4 = Cgsp2 + Cdbp1
transistors Mn1, Mp1, Mn2, and Mp2. (8)
C1,3 = Cgdn1
The equations governing the different voltage values in the circuit C1,4 = Cgdp1
are presented by: C2,3 = Cdbn2
C2,4 = Cdbp2
VGSn1 − VGSp1 = VDD
VGSn2 + VDSn1 = VB
where Cgsn1, Cgsp1, Cgsn2, and Cgsp2 are the gate to source capacitance of
VGSp2 + VDSp1 = − VDD (2)
VGSn1 = VDSn1 + VDSn2 transistors Mn1, Mp1, Mn1, and Mp2 respectively, Cgdn1, Cgdp1, Cgdn2, and
VGSp1 = VDSp1 + VDSp2 Cgdp2 are the gate to drain capacitance of transistors Mn1, Mp1, Mn1, and
Mp2 respectively, CL is the load capacitance, and Cdbn1, Cdbp1, Cdbn2, and
where VGSn1, VGSp1, VGSn2, and VGSp2 are the gate to source voltages of Cdbp2 are the drain to bulk capacitance of transistors Mn1, Mp1, Mn1, and
transistors Mn1, Mp1, Mn2, and Mp2 respectively, and VDSn1, VDSp1, VDSn2, Mp2 respectively.
and VDSp2 are the drain to source voltages of transistors Mn1, Mp1, Mn2, The transfer function of the circuit in Fig. 5(c) was calculated using
and Mp2 respectively and VB is the bias voltage connected to the gate of the symbolic circuit solver SapWin [42], it has four poles and three
transistor Mn2. zeros. The complete symbolic transfer function f(C1,C13,C14,C2,C23,C24,
C3,C4,gmn1,gmn2,gmp1,gmp2,r0n1,r0n2,r0p1,r0p2,Rf) is not written here being
B) AC analysis: too long and having numerous symbols.

The low-frequency small-signal model of the InvCas circuit is shown C) Noise Analysis:
in Fig. 5(b) where different parasitic capacitances are ignored and only
the large photodiode capacitance is considered. This model is eligible for The input referred noise spectral density of the InvCas circuit can be
low bandwidth applications as biomedical applications where the derived from Fig. 5(d):

4
M.M. Elbadry et al. AEUE - International Journal of Electronics and Communications 142 (2021) 153985

⎡ ( ) ⎤
G2m + (2π fCPD )2 Rf ⎧ ( )
⎪ t− 1
⎨ Xpbest(i) t
if f X(i) t− 1
> Xpbest(i)
⎢ ( ⎥
⎢ + (2πfC R )2 + 1)( g γ + g γ ) ⎥ t
Xpbest(i) = ( ) (13)
⎢ PD f mn1 n1 mp1 p1 ⎥ ⎪
⎢ ⎥ ⎩ X(i) t t
if f X(i) t− 1
⩽Xpbest(i)
⎢ ⎥
⎢ 2
(2πfCPD Rf ) + 1 ⎥
4k T ⎢ ⎥
i2n,in = ⎢
2⎢
+ r0n1 gmn2 γ n2 ⎥
⎥ (9) while the global best position Xgbest is given by:
(1 − Gm Rf ) ⎢ (gmn2 r0n1 + + 1)2 ⎥
⎢ r 0n2 ⎥ ( ) { ( )}
⎢
⎢
⎥
⎥
t
Xgbest = Xpbest(k) t
, where f Xpbest(k) t
= min f Xpbest(i) (14)
⎢
⎣ (2πfCPD Rf )2 + 1 ⎥
⎦
+ r0p1 gmp2 γp2
(gmp2 r0p1 + + 1)2 The velocity updating equation consists of three terms:
r0p2
t
1) The wV(i) term is the inertia component which contains the memory
where k is Boltzmann’s constant, T is the temperature, and γ n2, γ p1, γn2,
and γ p2 are the noise factors of transistors Mn1, Mp1, Mn1, and Mp2 of the previous direction related to the immediate past. This
respectively. component prevents any extreme change in the direction of the
The root mean squared (rms) input-referred noise current is defined particle from one iteration to another.
( )
as the square root of the result from integrating Eq. (9): 2) The c1 r1 Xt pbest(i) − X(i) t +c2 term is the cognitive component which
assess the performance of each particle in the swarm in relation to its
⎡ ⎛ ⎞ ⎤ 12
previous performance. This component resembles a memory of the
( )
⎢
⎢
⎜
⎜ 2 4 2 2 2
⎟⎥
⎟⎥ best position visited by the particle. It provides an inclination of the
G + π BW C
n PD Rf
⎢
⎢
⎜
⎜
m
3 ⎟⎥
⎟⎥ updated velocity towards the best individual position of the particle.
⎢ ⎜ ( ⎟⎥ ( )
⎢ ⎜ )( ⎟⎥ 3) The c2 r2 Xgbest − X(i) t term is the social component which assess the
⎢ ⎜ 4 ⎟⎥
⎢
⎢
⎜ + 1 + π2 BWn2 CPD
⎜
2
gmn1 γ n1 + gmp1 γ p1 ) ⎟⎥
⎟⎥ perfomance of each particle in relation to the best position found by
3
⎢ 4K T BW ⎜
⎢ n ⎜
⎟⎥
⎟⎥ any particle in the entire swarm. This component has the effect of
In,in,rms =⎢ ⎜ ⎟⎥ moving particles towards the best overall position discovered by the
⎢(1 − Gm Rf )2 ⎜ 1 + 43π 2 BWn2 CPD2
⎟⎥
⎢ ⎜ + gmn2 γn2 ⎟⎥
⎢ ⎜ (g r + r0n1
+ 1)2 ⎟⎥ swarm at any iteration.
⎢ ⎜ mn2 0n1 r0n2 ⎟⎥
⎢ ⎜ ⎟⎥
⎢ ⎜ ⎟⎥
⎢
⎢
⎜
⎜ 1 + 43π2 BWn2 CPD 2 ⎟⎥
⎟⎥ Optimum values for each of the three coefficients w, c1, and c2 are
+ gmp2 γ p2
⎢
⎣
⎜
⎝
r0p1
(gmp2 r0p1 + r0p2 + 1)2
⎟⎥
⎠⎦ found empirically and can change depending on the nature of the
optimization problem [43,44]. Albeit it is often recommended that w ∈
]0, 1[ while c1 andc2 ∈ ]0, 1.5].
(10)
The position and velocity of each particle are randomly initialized
where BWn is the equivalent noise bandwidth = 1.5 times the overall across the entire space then the fitness of each particle is calculated
bandwidth of the circuit. according to the cost function and the Xpbest and Xgbest are determined
while the velocity and position of each particle are updated according to
4. The PSO algorithm Eqs. (11) and (12), finally the optimization procedure reaches its end
when one of the stopping criteria is achieved and the particle with the
The PSO is one of the metaheuristic optimization algorithms, these best fitness is returned as the solution.
algorithms aim to reach the optimum solution which minimizes a cost
function of an optimization problem by simulating different phenomena 5. The proposed framework
presented in nature. The PSO is simulating the movements of bird flocks
and fish schools in their search for food, this is represented by a swarm The purpose of our framework is to integrate the PSO algorithm and
or population of particles. Each particle in the PSO is defined by its the gm/ID methodology to solve the analog circuit design problem. The
position and its velocity. The position and velocity are vectors in a framework is applied on InvCas-TIA to calculate its circuit parameters.
multidimensional space defined by the number of input variables of the As discussed before the gm/ID methodology allows us to achieve accuracy
optimization problem f where f : Rn →R. The position of the ith particle in between the transistor sizing in the circuit, the resulting parameters, and
the swarm, i ∈ [1, ⋯, P] where P is the size of the swarm and P > 1, is the final specification of our designs without compromising the com­
described as X(i) = [x1(i) , x2(i) , ..., xn(i) ] where n is the number of di­ putations and calculation time needed, while the PSO algorithm is
implemented to find the required solution in the design space.
mensions of the optimization problem and the velocity of each particle is
First, we must define the design space of our problem which means
V(i) = [v1(i) , v2(i) , ..., vn(i) ]. The position and velocity are then updated
finding the set of independent variables that are sufficient to give a
after each iteration according to the following equations:
unique circuit design. Investigating the InvCas-TIA circuit, we need to
t+1
V(i) t
= wV(i) t
+ c1 r1 (Xpbest(i) t
− X(i) t
) + c2 r2 (Xgbest − X(i) ) (11) find the dimensions of the four transistors, the value of Rf, ID, and VB.
Since we are using the 130 nm CMOS technology and the fact that the
t+1
X(i) t
= X(i) t+1
+ V(i) (12) smallest length of transistors will lead to the best parameters, we chose
the length of the four transistors to be 130 nm. According to the con­
where w is the inertia weight which controls the effect of the particle’s ventional procedure of the gm/ID methodology, we need to determine the
own velocity on the next iteration, c1 and c2 are the learning factors for ID and the gm/ID of each transistor and obtain the transistor parameters
the particle’s own performance and the performance of the swarm, r1 using the generated tables then using the design equations derived in
and r2 are random uniformly distributed numbers between [0,1], Xpbest is section III, we evaluate the final specifications of the design. Using this
the best position found by the particle, and Xgbest is the global best po­ procedure, seven variables are defining the design space being (gm/ID)n1,
sition found by the entire swarm. (gm/ID)p1, (gm/ID)n2, (gm/ID)p2, ID, Rf, and VB. However by examining Eq.
t
The personal best position Xpbest(i) of each individual particle i at any (2), we can reduce the number of variables to six. Since the tables
time step t, t ∈ [1, ⋯, N] where N is the maximum number of iterations, generated for the gm/ID methodology are produced by the sweeping VDS
can be calculated by: and VGS of the testbench circuit in Fig. 1, we obtain the gm/ID of the
transistors indirectly and carry out the same procedure. This provides
the advantage of reducing the number of dimensions of the design space

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M.M. Elbadry et al. AEUE - International Journal of Electronics and Communications 142 (2021) 153985

Table 1
Parameters Values of PSO Algorithm.
Swarm Size w c1 c2

60 0.7 0.7 0.7

minimum value to be equal to the required transimpedance gain of the

circuit and the maximum to double this value.
A cost function is required to check the validity of the design asso­
ciated with each particle according to different required performance
parameters of the circuit (i.e., gain, bandwidth, power dissipation, and
input-referred noise). The cost function of our framework is defined by:
∑k ⃒ ⃒
1 ⃒Pcalc,j (Xi ) − Preq,j ⃒
CF = ∑k wj ⃒⃒ ⃒
⃒ (15)
j=1 wj j=1
Preq,j

where k is the number of performance parameters, wj is the weighting

factor of each performance parameter function, Pcalc,j(Xi) is the resulting
value of a performance parameter of particle Xi, and Preq,j is the required
value of a specific performance parameter.
The error function term in Eq. (15) is used in the absolute form with
the transimpedance gain (ZTIA(0)) equation (5) and the bandwidth (BW)
Eq. (7), while it is used without the absolute sign for the input-referred
noise (In,in,rms) Eq. (10) and power dissipation (PDiss) Eq. (1). This deci­
sion can be explained as the optimum design is the one that achieves the
required gain and the bandwidth while trying to minimize both the
input-referred noise and the power dissipation. Finally, a flowchart
presenting our framework is shown in Fig. 6 and can be explained as
follows:

1) Input parameters from the designer: VDD, CPD, CL, BWreq, Gainreq,
Noisereq, and PDiss,req.
2) Define the boundaries of the design space for each dimension: VGSn1,
VDSn1, VDSp1, ID, Rf, and VB.
3) Random initialization of swarm.
4) Determine remaining circuit parameters (gm, r0, and parasitic ca­
pacitances) using gm/ID and calculate the fitness of each particle.
5) Determine Xpbest and Xgbest.
6) Until stopping criteria are reached (minimum value of CF does not
change over n consecutive iterations or maximum number of itera­
tions reached):
a) Update position and velocity of each particle
b) Update remaining circuit parameters using gm/ID and calculate
the fitness of each particle.
c) Update Xpbest and Xgbest.
7) Output parameters of the particle with the best fitness: Wn1, Wp1,
Wn2, Wp2, Rf, and VB.

6. Simulation results and discussion

Fig. 6. Flowchart of the proposed framework. A) Results of the proposed Framework:

Our framework is implemented in Matlab where the designer enters

and decreasing the complexity of our design problem. Additionally,
the required circuit specifications and fixed parameters, then this data is
avoiding the possibility of the resulting particle position in the swarm
fed to the PSO algorithm which tries to find the optimum solution. The
being located in the infeasible region of the design space violating Eq.
fitness of each particle is decided by calculating the remaining circuit
(2), thus leading to better convergence of the algorithm. The position of
[ parameters from the stored lookup tables generated previously. The
each particle in the swarm becomes X(i) = VGSn1(i) , VDSn1(i) , VDSp1(i) ,
] final specifications of each particle are calculated by the design equa­
ID(i) , Rf(i) , VB(i) . tions presented in Section III and its fitness is evaluated, once one of the
We must define the boundaries of the design space so that each stopping criteria is reached, the program is stops and the parameters of
generated particle becomes in the feasible region and does not violate the design associated with the best particle are returned as an output. All
any circuit constraints. The voltage dimensions VGSn1, VDSn1, VDSp1, and optimizations are carried out on a core i7-3630QM 2.4 GHz processor
VB have a minimum value of zero and a maximum value of VDD, the with 16 GB of RAM where the average time of execution of the opti­
current ID has a minimum of zero and we can define its maximum value mization process is 8 m and 35 s.
from (1), becoming the maximum allowable power dissipation divided The values of different PSO parameters used in our program are
by VDD. As for the resistor Rf, using equation (5) we can define the presented in Table 1. These values are determined empirically which we

6
M.M. Elbadry et al. AEUE - International Journal of Electronics and Communications 142 (2021) 153985

Table 2 for 10 Gb/s applications, used the fascinating 40 nm CMOS technology

The different input specifications corresponding to each design. to reach that good FoM, but our design still showing the best perfor­
Spec. 10 Gbit/s 5 Gbit/s 125 Mbit/s mance. The low noise and power consumption achieved by our designs,
as shown in Tables 6 and 7, respectively, are the reason for that high
Gain 60 dBΩ 65 dBΩ 80 dBΩ
Bandwidth 7 GHz 4 GHz 100 MHz FoM. Comparing these designs with other works in literature they pro­
DC Power 5 mW 1 mW 500 µW duce respectable values according to FoM, proving that the proposed
Integrated Noise 1 µArms 0.5 µArms 50 nArms framework is not only able to reach the target specifications but also can
CPD 200 fF 200 fF 2 pF produce great results compared to state-of-the-art.
A higher value of FoM indicate a better overall performance of a TIA.
found gives the best results to our problem and are generally dependent BW(GHz) × Gain(Ω) × CPD (pF)
on the design problem. The framework is used to obtain three different FoM = √̅̅̅̅̅̅ (16)
PDC (mW) × In,in,ref (pA/ Hz)
designs intended for high-speed optical communications. The different
input specifications corresponding to each of the three designs are where FoM is the figure of merit for the designs targeted for optical
shown in Table 2. The optical communications design specifications are communications applications, Iin,n,ref is the input referred noise.
chosen for 10 Gb/s, 5 Gb/s, and 125 Mbit/s communications. The supply
voltage of all designs is set to 1.5 V and the load capacitance is set to 20 7. Conclusion
fF.
The value of the cost function versus the number of iterations for the This work presents a novel framework for the design of InvCas TIA
three designs is shown in Fig. 7, all optimizations are concluded in less integrating the PSO evolutionary algorithm and the gm/ID methodology.
than 100 iterations and the maximum number of iterations recorded by The design space of the problem is defined by the constraints provided
the three designs is 87 iterations. The resulting design parameters by design equations and at the same time relating the specifications with
returned by the MATLAB code for each design are presented in Table 3. the device sizing using the gm/ID methodology to calculate the final
specifications. The cost function is formalized using numerous perfor­
B) Validations: mance parameters which are of concern, thus enabling the framework to
find the design which achieves the bandwidth and gain required as well
For the proposed framework accuracy evaluation, simulation results as optimizing the DC power dissipation and the input-referred noise. The
for the different designs are conducted using CADENCE Spectre and PSO algorithm is used to search the design space for the required design
comparisons between the input specifications to the framework, final and the resulting circuit specification are validated using the Spectre
circuit performance calculated by the framework and the simulated simulator.
circuit performance using Spectre are presented in Table 4. The use of design equations in the framework enables us to decrease
Investigating Table 4, it is evident that there is a nearly complete the number of dimensions of the design space as well as elevating the
agreement between the input specifications reached (same gain and need to use Spice simulations to determine the specification of each
bandwidth) using the proposed framework calculated using MATLAB, particle during the optimization process. As a result, reduces the
and the specifications validated by the Cadence (Spectre) simulations. complexity of the design problem leading to faster convergence to the
The three designs achieved the required input gain and bandwidth required design. The integration between the PSO and gm/ID
specifications while having minimal power and noise performance.
Therefore, proving the accuracy of the framework and as explained,
removes the need to use Spice simulations for finding the fitness of each Table 3
particle during the optimization process. Consequently, less computa­ Resulting Parameters of Different Designs.
tion and time are required for the execution of the optimization process. Param. 10 Gbit/s 5 Gbit/s 125 Mbit/s
The frequency response of each design is presented in Fig. 8. Wn1 (µm) 29.34 20.96 9.295
Tables 5, 6, and 7 present performance comparisons between our Wp1 (µm) 20.74 5.415 1
three designs, and other works in the literature with comparable Wn2 (µm) 19.885 5.88 1.65
bandwidths. A figure of merit (FoM) equation is defined which takes all Wp2 (µm) 13.28 4.89 1.14
Rf (KΩ) 1.087 1.958 10.845
TIAs performance parameters into account to compare between VB (V) 1.067 1.068 1.302
different works [2,40], and [41]. The design in [41], included in Table 5

Fig. 7. Cost function vs number of iterations. (a) 10 Gbit/s, (b) 5 Gbit/s, and (c) 125 Mbit/s.

7
M.M. Elbadry et al. AEUE - International Journal of Electronics and Communications 142 (2021) 153985

Table 4
Comparison between Input Specifications, Measured Specifications by The Framework and Final Specifications by Simulations.
Spec. 10 Gbit/s 5 Gbit/s 125 Mbit/s

Input spec. Calc. Sim. Input spec. Calc. Sim. Input spec. Calc. Sim.

Gain 60 dBΩ 60 dBΩ 60 dBΩ 65 dBΩ 65 dBΩ 65 dBΩ 80 dBΩ 80 dBΩ 79.99 dBΩ
Bandwidth 7 GHz 6.99 GHz 6.84 GHz 4 GHz 4.2 GHz 4.18 GHz 100 MHz 100 MHz 103.18 MHz
DC Power 5 mW 2.78 mW 2.98 mW 1 mW 0.93 mW 0.98 mW 500 µW 199 µW 200.44 µW
Integrated Noise 1 µArms 578 nArms 705 nArms 0.5 µArms 373 nArms 393 nArms 50 nArms 23 nArms 24 nArms

Table 7
Performance Comparisons with Other Works in 125 Mbit/s Applications.
Ref. [49]* [50] [51]* This
Work

Gain (dBΩ) 100 101 93.4 79.99

Bandwidth (MHz) 110 102 99 103.18
DC Power (mW) 8 10 3.6 0.2
Input Referred Noise (pA/ 2.21 2 3.62 1.9
√Hz)
CPD (pF) 2 2 0.5 2
Supply Voltage (V) 3.3 5 3.3 1.5
Technology 180 nm 350 nm SiGe 180 130 nm
BiCMOS nm
Topology CGCMA CC/CE/CC CA InvCas
FoM 2054.5 1244.4 177.7 5424.3

CGCMA: common-gate input current mirror amplifier.

CC/CE/CC: three-stage common collector, common emitter, and common col­
lector with a shunt-shunt local feedback resistor.
CA: common gate and common source current with RGC input stage.
*
results were obtained experimentally.

methodology achieves the speed of convergence and robustness of the

PSO evident in the cost function minimization needing less than 87 it­
erations and eventually finding a design obtaining the required speci­
Fig. 8. Simulated frequency response of different designs using Spectre. (a) 10
fications concluded in less than 9 min, along with the accuracy in the
Gbit/s, (b) 5 Gbit/s, and (c) 125 Mbit/s.
sizing of transistors by gm/ID methodology evident by the comparison
between the resulting specification calculated by the framework and the
Table 5
final specification validated by the simulations.
Performance Comparisons with Other Works in 10 Gbit/s Applications.
The framework implementation in Matlab is used to produce three
Ref. [41] [45]* [46] This different designs targeted for optical receiver applications. The three
Work
designs achieved the required specifications while having minimal
Gain (dBΩ) 55.3 50.1 48 60 power and noise performance. Moreover, comparing these designs with
Bandwidth (GHz) 8 7 7 6.84 other works in literature they produce respectable values, according to
DC Power (mW) 3.01 7.5 10 2.98
Input Referred Noise (pA/ 12.3 31.3 25.1 6.96
our FoM, proving that this framework is not only able to produce the
√Hz) target specifications but also can reach better results in other perfor­
CPD (pF) 0.45 0.25 0.2 0.2 mance parameters.
Supply Voltage (V) 1.2 1.5 0.8 1.5
Technology 40 nm 130 nm 90 nm 130 nm
Topology InvCas MIC RGC w/ InvCas Declaration of Competing Interest
RGC WSC
FoM 56.6 2.4 1.4 66.1
The authors declare that they have no known competing financial
MIC RGC: modified immittance converter regulated cascode. interests or personal relationships that could have appeared to influence
RGC w/ WSC: regulated cascode with wide-swing cascode. the work reported in this paper.
*
results were obtained experimentally.

Acknowledgment
Table 6
Performance Comparisons with Other Works in 5 Gbit/s Applications.
This work was partially supported by United Arab Emirates Uni­
Ref. [39] [47] [48]* This Work versity, Arab Emirates, under grant G00003441.
Gain (dBΩ) 53.5 40.6 61.4 65
Bandwidth (GHz) 3.5 4 2.9 4.18 References
DC Power (mW) 1.28 0.274 4.9 0.98
Input Referred Noise (pA/√Hz) 163.8 13.2 26.8 4.966 [1] Jespers P. The gm/ID Methodology, a sizing tool for low-voltage analog CMOS
CPD (pF) 0.2 0.0.2 1 0.2 Circuits: The semi-empirical and compact model approaches. Springer Science &
Supply Voltage (V) 1 1 1.3 1.5 Business Media, 2009.
Technology 90 nm 90 nm 180 nm 130 nm [2] Elbadry MM, Makkey MY, Abdelgawad M, Atef M. Design technique for regulated
Topology InvCas RGC RGC InvCas cascode transimpedance amplifier using Gm/ID methodology. Microelectron J
FoM 15.4 23.7 25.1 305.5 2020;95:104676.
[3] Akbari M, Hashemipour O. Design and analysis of folded cascode OTAs using Gm/
RGC: regulated cascode amplifier. Id methodology based on flicker noise reduction. Analog Integr Circ Sig Process
*
: results were obtained experimentally. Jun. 2015;83(3):343–52. https://doi.org/10.1007/s10470-015-0535-x.

8
M.M. Elbadry et al.
[4] Ou J, Ferreira PM. A gm/ID-Based Noise Optimization for CMOS Folded-Cascode
Operational Amplifier. IEEE Trans Circuits Syst II 2014;61(10):783–7. https://doi.
org/10.1109/TCSII.2014.2345297.
[5] Ou J, Ferreira PM, Lee J-C. Experimental demonstration of Gm/Id based noise
analysis. Circuits Syst 2014;5(04):69.
[6] Ou J. Gm/ID based noise analysis for CMOS analog circuits. In: 2011 IEEE 54th
International Midwest Symposium on Circuits and Systems (MWSCAS), Seoul,
Korea (South), Aug. 2011, pp. 1–4. doi: 10.1109/MWSCAS.2011.6026580.
[7] Manghisoni M, Ratti L, Re V, Speziali V, Traversi G. Noise Characterization of 130
nm and 90 nm CMOS Technologies for Analog Front-end Electronics. In: 2006 IEEE
Nuclear Science Symposium Conference Record, San Diego, CA, USA, 2006, pp.
214–18. doi: 10.1109/NSSMIC.2006.356142.
[8] Akbari M, Shokouhifar M, Hashemipour O, Jalali A, Hassanzadeh A. Systematic
design of analog integrated circuits using ant colony algorithm based on noise
optimization. Analog Integr Circ Sig Process 2016;86(2):327–39.
[9] Piccinni G, Avitabile G, Coviello G, Talarico C. A novel design optimization
framework for regulated cascode transimpedance amplifiers. In: 2017 European
Conference on Circuit Theory and Design (ECCTD), 2017, pp. 1–4.
[10] Shameli A, Heydari P. A novel power optimization technique for ultra-low power
RFICs. In: Proceedings of the 2006 international symposium on Low power
electronics and design - ISLPED ’06, Tegernsee, Bavaria, Germany, 2006, p. 274.
doi: 10.1145/1165573.1165639.
[11] Shameli A, Heydari P. A Novel Ultra-Low Power (ULP) Low Noise Amplifier using
Differential Inductor Feedback. In: 2006 Proceedings of the 32nd European Solid-
State Circuits Conference, Montreux, Sep. 2006, pp. 352–55. doi: 10.1109/
ESSCIR.2006.307603.
[12] Girardi A, Bampi S. Power constrained design optimization of analog circuits based
on physical gm/ID characteristics. In: Proceedings of the 19th annual symposium
on Integrated circuits and systems design - SBCCI ’06, Ouro Preto, MG, Brazil,
2006, p. 89. doi: 10.1145/1150343.1150370.
[13] Goswami S, et al. A 14mW 5Gb/s CMOS TIA with gain-reuse regulated cascode
compensation for parallel optical interconnects. In: 2009 IEEE International Solid-
State Circuits Conference - Digest of Technical Papers, San Francisco, CA, Feb.
2009, pp. 100-101,101a. doi: 10.1109/ISSCC.2009.4977327.
[14] Talarico C, D’Amato G, Avitabile G, Piccinni G, Coviello G. A Systematic Design
Approach for Nanoscale Inductor-less Regulated Cascode Stages. In: Proceedings of
the 29th Symposium on Integrated Circuits and Systems Design: Chip on the
Mountains, Piscataway, NJ, USA, 2017, p. 21:1-21:5. [Online]. Available: http://
dl.acm.org/citation.cfm?id=3145862.3145883.
[15] Kamarudin NB, Karim J. Design and simulation single stage CMOS TIA for 1.4
GHz,-27 dB MEMS SAW resonator. In: 2017 IEEE Regional Symposium on Micro
and Nanoelectronics (RSM), Batu Ferringhi, Penang, Malaysia, Aug. 2017, pp.
163–6. doi: 10.1109/RSM.2017.8069162.
[16] Barros MF, Guilherme JM, Horta NC. Analog circuits and systems optimization
based on evolutionary computation techniques. Springer; 2010.
[17] De BP, Kar R, Mandal D, Ghoshal SP. An efficient design of CMOS comparator and
folded cascode op-amp circuits using particle swarm optimization with an aging
leader and challengers algorithm. Int J Mach Learn Cybern 2016;7(2):325–44.
[18] Barari M, Karimi HR, Razaghian F. Analog circuit design optimization based on
evolutionary algorithms. Math Problems Eng 2014;2014:1–12.
[19] Fakhfakh M, Cooren Y, Sallem A, Loulou M, Siarry P. Analog circuit design
optimization through the particle swarm optimization technique. Analog Integr
Circ Sig Process 2010;63(1):71–82.
[20] Vural RA, Yildirim T. Analog circuit sizing via swarm intelligence. AEU-Int J
Electron Commun 2012;66(9):732–40.
[21] Singh CL, Baishnab K, Anandini C. Analysis and optimization of noises of an analog
circuit via PSO algorithms. Microsyst Technol 2019;25(5):1793–807.
[22] De BP, Maji K, Kar R, Mandal D, Ghoshal S. “Application of improved PSO for
optimal design of CMOS two-stage op-amp using nulling resistor compensation
circuit. Devices for Integrated Circuit (DevIC) 2017;2017:110–5.
[23] Ben Y, Shi G. Applying design equations in particle swarm optimization for auto-
sizing of multi-stage opamps: an experimental study. Analog Integr Circ Sig Process
2020;103(1):117–30.
[24] Kotti M, et al. “Comparison between PSO and ACO techniques for analog circuit
performance optimization. ICM Proceeding 2011;2011:1–6.
[25] Hosseini SA, Hajipour A, Tavakoli H. Design and optimization of a CMOS power
amplifier using innovative fractional-order particle swarm optimization. Appl Soft
Comput 2019;85:105831.
[26] Thakker RA, Baghini MS, Patil MB. Low-power low-voltage analog circuit design
using hierarchical particle swarm optimization. In: in 2009 22nd international
conference on VLSI design; 2009. p. 427–32.
AEUE - International Journal of Electronics and Communications 142 (2021) 153985
[27] Sasikumar A, Muthaiah R. Operational amplifier circuit sizing based on nsga-ii and
particle swarm optimization. In: International Conference on Networks & Advances
in Computational Technologies (NetACT); 2017. p. 64–8.
[28] Ghosh S, De BP, Kar R, Mandal D, Mal AK. Optimal design of complementary
metal-oxide-semiconductor analogue circuits: An evolutionary approach. Comput
Electr Eng 2019;80:106485.
[29] Mallick S, Kar R, Ghoshal SP, Mandal D. Optimal sizing and design of CMOS
analogue amplifier circuits using craziness-based particle swarm optimization. Int J
Numer Model Electron Networks Devices Fields 2016;29(5):943–66.
[30] Mallick S, Kar R, Mandal D, Ghoshal SP. Optimal sizing of CMOS analog circuits
using gravitational search algorithm with particle swarm optimization. Int J Mach
Learn Cybern 2017;8(1):309–31.
[31] Joshi D, et al. Optimization of 2.4 GHz CMOS low noise amplifier using hybrid
particle swarm optimization with Lévy flight. In: in 2017 30th International
Conference on VLSI Design and 2017 16th International Conference on Embedded
Systems (VLSID); 2017. p. 181–6.
[32] Kumar M, Deolia VK. Performance analysis of low power LNA using particle swarm
optimization for wide band application. AEU-Int J Electron Commun 2019;111:
152897.
[33] Vural RA, Yildirim T. Swarm intelligence based sizing methodology for CMOS
operational amplifier. In: in 2011 IEEE 12th International Symposium on
Computational Intelligence and Informatics (CINTI); 2011. p. 525–8.
[34] Prajapati PP, Shah MV. Two stage CMOS operational amplifier design using
particle swarm optimization algorithm. In: IEEE UP Section Conference on
Electrical Computer and Electronics (UPCON); 2015. p. 1–5.
[35] Atef M, Zimmermann H. Optoelectronic circuits in nanometer CMOS technology.
In: Optoelectronic circuits in nanometer CMOS technology, Springer, 2016, pp.
217–240.
[36] Razavi B. Design of integrated circuits for optical communications. 2nd ed.,. John
Wiley & Sons; 2012. p. 62–9.
[37] Atef M, Zimmermann H. Transimpedance Amplifiers. In: Optoelectronic Circuits in
Nanometer CMOS Technology, Cham: Springer International Publishing, 2016, pp.
105–161. doi: 10.1007/978-3-319-27338-9_6.
[38] Zhang G, Xiao X, Xu J, Nie K, Gao Z. Particle swarm optimization design of low-
power multistage amplifier using gm/ID methodology. J Circuits, Syst Comput
2016;25(09):1650104.
[39] Zohoori S, Dolatshahi M. A CMOS Low-power optical front-end for 5 Gbps
applications. Fiber Integr Opt 2018;37(1):37–56.
[40] Atef A, Atef M, Khaled EEM, Abbas M. CMOS Transimpedance Amplifiers for
Biomedical Applications: A Comparative Study. IEEE Circuits Syst Mag 2020;20(1):
12–31.
[41] Atef M, Chen H, Zimmermann H. 10Gb/s inverter based cascode transimpedance
amplifier in 40nm CMOS technology. In: in 2013 IEEE 16th International
Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS);
2013. p. 72–5.
[42] SapWin, site: “http://cirlab.det.unifi.it/SapWin4”. [Online]. Available: ’http://
cirlab.det.unifi.it/SapWin4’.
[43] Kennedy J, Eberhart R. Particle swarm optimization. In: Proceedings of ICNN’95 -
International Conference on Neural Networks, 1995, vol. 4, pp. 1942–48 vol.4. doi:
10.1109/ICNN.1995.488968.
[44] Talukder S. Mathematicle modelling and applications of particle swarm
optimization. 2011.
[45] Taghavi MH, Belostotski L, Haslett JW, Ahmadi P. 10-Gb/s 0.13-μm CMOS
Inductorless Modified-RGC Transimpedance Amplifier. IEEE Trans Circuits Syst I
Regul Pap 2015;62(8):1971–80.
[46] Zohoori S, Dolatsahi M. “An inductor-less, 10Gbps trans-impedance amplifier
operating at low supply-voltage. Iranian Conf. Electrical Eng. (ICEE) 2017;2017:
145–8.
[47] Zohoori S, Shafiei T, Dolatshahi M. A 274μW, Inductor-less, Active RGC-Based
Transimpedance Amplifier Operating at 5Gbps. In: in 2019 27th Iranian Conference
on Electrical Engineering (ICEE); 2019. p. 1–4.
[48] Lu T-T, Lee H-C, Wang C-S, Wang C-K. A 4.9-mW 4-Gb/s single-to-differential TIA
with current-amplifying regulated cascode. In: in Proceedings of technical program of
2012 VLSI design, automation and test; 2012. p. 1–4.
[49] Ma R, Liu M, Zheng H, Zhu Z. A 66-dB Linear Dynamic Range, 100-dB Ω
Transimpedance Gain TIA With High-Speed PDSH for LiDAR. IEEE Trans Instrum
Meas 2019;69(4):1020–8.
[50] Mičušik D, Zimmermann H. Transimpedance amplifier with 120 dB dynamic range.
Electron Lett 2007;43(3):159–60.
[51] Chen RY, Yang Z-Y. CMOS transimpedance amplifier for visible light
communications. IEEE Trans. Very Large sScale Integration (VLSI) Syst. 2014;23
(11):2738–42.