PBL Topics

VII Sem ‘A’ Sec

SL USN NAME OF THE STUDENT PROJECT BASED LEARNING TOPIC

NO
1 Design and Implementation of Hamming
1DT20EC001 ABHISHEK R Code using Verilog.
ADITHYA
1DT20EC002
BALASUBRAMANYA
1DT20EC003 ADITI JAISWAL
1DT20EC004 ADITI MITRA
2 1DT20EC005 AKSHAY KALASH Power Efficient Clock Pulsed D Flip Flop
1DT20EC006 ANANDHA KRISHNAN Using Transmission Gate
1DT20EC007 ANEESHVAR R GUNARI
1DT20EC008 ANUSHA KUMARI
3 1DT20EC009 APOORVA N Design of Flash ADC using Improved
1DT20EC010 APPAIAH U N Comparator Scheme
1DT20EC011 BHAVANA G M
1DT20EC012 DAMINI KASHYAP
4 1DT20EC013 DIKSHA KUMARI A Design Technique for Faster Dadda
1DT20EC014 G SRIVARDHAN REDDY Multiplier
1DT20EC015 GOWRAV B K
5 1DT20EC016 HEMANTH KUMAR L Low Power High Performance Double Tail
1DT20EC017 IMPANA B Comparator
1DT20EC018 JAYANTH R
1DT20EC019 K M HEMANTH CHOWDARY
6 1DT20EC020 K VAMSHI High Speed 16×16-bit Low-Latency
KALLURU DURGA PRASAD Pipelined Booth Multiplier
1DT20EC021
REDDY
1DT20EC022 KAVYA MOHAN NAIK
7 1DT20EC023 KAVYA N PUJARI Design and Performance analysis of CMOS
based D Flip – Flop using Low power
1DT20EC024 KIRAN S
Techniques
8 1DT20EC025
KORITALA GOPI Low power CMOS counter using clock
CHOWDARY gated flip – flop
1DT20EC026 LAKSHMI N
1DT20EC027 LAKSHMISH T G
1DT20EC028 MANASA S
9 1DT20EC029 MANJUNATH DOLLA High Speed Multiplier Using Spurious
1DT20EC030 MANJUNATH S Power Suppression
1DT20EC031 MANJUNATHA G L
10 1DT20EC032 MOHAMED MADNI 32bit Floating Point Arithmetic Unit
1DT20EC033 MOHAMMED SHUAIB
1DT20EC034 MOHIT PRAKASH
11 1DT20EC035 NAVANEETH S Design Of Parallel Multiplier Based on
1DT20EC036 NAVATEJA B N Radix-2 Modified Booth Algorithm
1DT20EC037 NEHA B H
1DT20EC038 NIDHI D
12 1DT20EC039 NISARGA K C VLSI Systolic Array Multiplier for signal
1DT20EC040 NITHYA G processing Applications
1DT20EC041 P S SACHIN
1DT20EC042 PAGADAM DHANUSH
 KUMAR BABU
13 1DT20EC043
PRAGATI RAJENDRA Low Power Comparator Design Using
MUSALE Reversible Logic Gates
1DT21EC400 ABHISHEK M N
1DT21EC401 AKASH R
14 DT21EC409 SUDARSHAN A high-speed design of 16-bit Vedic
1DT21EC411 TEJAS KUMAR G M Multiplier

PBL Topics
VII Sem ‘B’ Sec

SL USN NAME OF THE STUDENT PROJECT BASED LEARNING TOPIC

NO
1 1DT20EC044 PRAJITH SA Low power Wallace Tree Multiplier
1DT20EC045 PRAJWAL G KOPPA using Modified Full Adder
1DT20EC046 PRAJWAL R ARADHYA
1DT20EC047 PRATHYUSHA TVN
2 1DT20EC048 PREMSAGAR J High-speed VLSI architectures for the
1DT20EC049 PUNITH B S AES algorithm
1DT20EC050 RAGHURAM K S
1DT20EC051 RAKIBUL ISLAM SARKAR
3 1DT20EC052
RASIREDDY VISWABHARGAV Implementation of LFSR by Using
REDDY Gray Code Converter
1DT20EC053 RESHIKA N
1DT20EC054 ROHAN S SAVADAKAR
1DT20EC055 ROHITH Y
4 1DT20EC056 S KRISHNA MAANAS REDDY Design of 4:2 Compressor based
1DT20EC057 SAI KRISHNA REDDY Approximate Booth multiplier
1DT20EC058 SAILESH SINGH
1DT20EC059 SANJAY M
5 1DT20EC060 SANNIDHI K S Design of Optimized proposed 9T
1DT20EC061 SHAN SINHA SRAM Cell
1DT20EC062 SHASHANK S G
1DT20EC063 SHRAVYA R
6 1DT20EC064 SHREYAS BM Design of Low Power and High-Speed
1DT20EC065 SHUBHANGI BHARTI Dynamic Latch Comparator using 180
1DT20EC066 SIBBALA BHARIHISH SAI nm Technology
1DT20EC067 SRINIVAS R
7 1DT20EC069 SUDHAKAR U Design of Low Power and Enhance
1DT20EC070 SURAJ K R Speed Multiplier and Accumulator
1DT20EC071 SUSHMITHA D With SPST Adder in Verilog
1DT20EC073 TANIYA FATIMA
8 1DT20EC074 TARUN D Adder design using Low Power Digital
1DT20EC075 THARUN M design Techniques
1DT20EC077 VARSHA M CHAKRASALI
1DT20EC078 VIDYA BANKAPUR
9 1DT20EC079 VIGNESH H Clock gating aware low power ALU
1DT20EC080 VILAS YADAV U design and implementation on FPGA
1DT20EC081 VINAY M
1DT20EC082 VIVEKA KRISHNA GOND
1DT20EC083 YASHWITH K V
10 1DT20EC084 YELLA AJAY KUMAR REDDY Design of A six transistors full adder
1DT20EC085 YOGESH S GOWDA
1DT21EC402 B R SRIVIDYA
11 1DT21EC403 DARSHAN H Design of OTA Based comparator
1DT21EC404 KALAVATHI K P using 180nm technology
1DT21EC405 PRAVEEN B
1DT21EC406 SOUNDARYA A