Phases of Design Flow

• Phase 1: Design Planning

– From application requirements to specifications

Overview of Digital IC Design Flow • Phase 2: Design Implementation and Verification

– From SPEC to layout (GDSII)
• Phase 3: Design Review and Tape-out
Qiuzhong Wu – Function, timing etc.

Phase 1 Tasks Phase 2 Tasks

• Define Specifications Based on the Application • Design Implementation and Verification
Requirements – Logic design and verification
• HW/SW Partition – Physical design and verification
• Algorithm Design • Timing Closure
• Architecture Design • Power Optimization
• Design Partition (Clock, Power etc) • Area Refinement
• Define the SPEC of Sub-blocks
• Effort Estimation and Resources Allocation
3 4
 Phase 3 Tasks
• Design Review
• ECO (Engineering Change Order)
• Tape-out
Phase 1: Design Planning

Flow chart of Phase 1 Specifications

• Function Specification
• IO Specification
• Interface Protocol Specification
• Characteristics Specification
– Speed
– Power
– Area

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 Algorithm Design Architecture Design
• Model the system in high-level language • Computation Architecture
– MATLAB • Data Path Architecture
– C/C++ • Control Path Architecture
– SystemC
• Operation Reuse
– SystemVerilog
• Clock and Reset Strategy
• Purposes
– Understanding of the system
– Algorithm design and comparison
– Test-Bench and golden files generation
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Design Partition Module SPEC Definition

• Function Partition
• Clock Domain Partition
• Power Domain Partition
• Full custom design versus standard cell
based design
• After design partition, the system is divided into
separate modules with determinate functions.
• Define specification of each module
– To carry out implementation in parallel
– Design and verification should be done module by
module
– Easy to implement and debug

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 Flow Chart of Phase 2

Phase 2: Design Implementation

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RTL Design RTL Coding

• RTL: Register Transfer Level
• Verilog-HDL/VHDL (Hardware Description Language)
are the two mainstream hardware description languages
• Behavior Description VS. Architecture Description

module mux_beh(out, a, b, sel) module mux_str(out, a, b, sel)

output outp output outp
input a, b, sel, input a, b, sel,
assign out=(sel==0)?a:b; not gate1(net1,sel);
endmodule and gate2(net2, a, net1);
and gate3(net3, b, sel);
or gate4(out, net2, net3);
15 endmodule 16
 RTL Purification RTL Simulation
• Find out code defects in RTL level
• Make the code more readable and predictable
• For function verification RTL Code
• Assure compatibility with most tools
(No timing Information)
• Find out some possible timing problems in RTL level – Check points Debug Simulation Test Benches
– Compare the simulation No
RTL Code result with golden Pass
behavior model Yes

Code Revising Coding Rules Checking

• Debug Coverage Analysis
Coding Rules
• Coverage No
– Function coverage Meet
Yes
violation Yes
– Code coverage
No To Next Step
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To Next Step

FPGA Verification Logic Synthesis

• FPGA: Field-Programmable Gate Array • Logic synthesis is the process of converting a high
• Basic FPGA verification Flow level description of design into an optimized gate
– Design Input (HDL, Schematic etc.) level representation
– Compile and Synthesis • Logic synthesis uses standard cell libraries which
– Place and Route have simple cells, such as basic logic gates like and,
– Function Checking
or, and nor, or macro cells, such as adder, mux,
memory, and special flip-flops.
• Advantages:
• The designer would first understand the architectural
– Easy to implement (Comparing to manufacturing) description. Then he/she would consider design
– Easy to verify (Comparing to Simulation) constraints such as timing, area, testability, and
• Disadvantages: power
– Can’t cover timing issue 19 20
 Formal Verification in Design Flow
Formal Verification
• Formal verification is the use of mathematical
techniques to ensure that a design conforms to some
precisely expressed notion of functional correctness.
• A particular formal verification problem of great
interest in EDA is equivalence checking.
• Why “Formal Verification”
– Find more bugs
– Find bugs faster
– Find bugs earlier

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DFT Synthesis Manufacturing Defects and Modeling

• DFT • Manufacturing defects
– Design For Testability – Power or ground shorts
– Assures high-quality integrated circuits by screening out
devices with manufacturing defects – Open interconnect on the die caused by dust
particles
• Function Testing VS. Manufacturing Testing
– Functional testing verifies that your circuit performs as it
– Short-circuited source or drain on the transistor
is intended to perform. caused by metal spike-through
– Manufacturing testing verifies that your circuit does not • Modeling of manufacturing defects
have manufacturing defects by focusing on circuit
structure rather than functional behavior.
– Stuck-at Fault Models
– State Table Models

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 Scan Design Techniques Scan Insertion
• Internal Scan Design
– Scan Cell
– Scan Chain
The modified sequential cells are chained together to
form one or more large shift registers. These shift registers
are called scan chains or scan paths. The sequential cells
connected in a scan chain are scan controllable and scan
observable.

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Place and Route

Static Timing Analysis
• STA
– Static Timing Analysis is a method of validating the
timing performance of a design by checking all possible
paths for timing violations.
• STA VS Dynamic Simulation
– Static timing analysis is much faster
– Static timing analysis is also more thorough
– static timing analysis can only check the timing, not the
functionality

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 Timing Paths (1) Timing Paths (2)
• The first step of timing analysis is to break the
design down into a set of timing paths. Each path
has a startpoint and an endpoint.
• The startpoint of a path is a clock pin of a
sequential element, or possibly an input port of the
design (because the input data can be launched
from some external source). The endpoint of a
path is a data input pin of a sequential element, or
possibly an output port of the design

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Special Timing Paths (1) Special Timing Paths (2)

• Special timing paths
– Clock path (a path from a clock input port or cell pin,
through one or more buffers or inverters, to the clock
pin of a sequential element) for data setup and hold
checks
– Clock-gating path (a path from an input port to a clock-
gating element) for clock-gating setup and hold checks
– Asynchronous path (a path from an input port to an
asynchronous set or clear pin of a sequential element)
for recovery and removal checks

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 Delay Calculation Setup and Hold Checking for Flip-Flops
• SDF
– The Standard Delay Format (SDF) file stores the timing data generated
by EDA tools for use at any stage in the design process. The data in the
SDF file is represented in a tool-independent way and can include
Delays, Timing checks and Timing constraints etc.
• Cell delay
– the amount of delay from input to output of a logic gate in a path.
(CELL
(CELLTYPE "HDAND3D1")
(INSTANCE I_BMI_PACKET/U321)
(DELAY
(ABSOLUTE
(IOPATH A1 Z (0.1015:0.1015:0.1015) (0.0979:0.0979:0.0979))
(IOPATH A2 Z (0.0982:0.0982:0.0982) (0.1063:0.1063:0.1063))
(IOPATH A3 Z (0.1195:0.1195:0.1195) (0.1371:0.1371:0.1371))
)
)
)
)
)

• Net delay
– amount of delay from the output of a cell to the input of the next cell in a
timing path.
(INTERCONNECT I_BMI_PACKET/U493/Z I_BMI_PACKET/U34/A1 (0.021:0.021:0.021) (0.0204:0.0204:0.0204))
34
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Setup and Hold Checking for Latches Timing Exceptions

• False path – A path that is never sensitized due to the logic
configuration, expected data sequence, or operating mode.
• Multicycle path – A path designed to take more than one
clock cycle from launch to capture.
• Minimum/maximum delay path – A path that must meet a
delay constraint that you specify explicitly as a time value.

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 STA Flow Post-layout Simulation
Read the design data

• Post-layout simulation—simulate the netlist

after place and route with the delay timing
Constrain the design
information (SDF), use the same test-benches
for RTL simulation.
Specify the environment
and analysis conditions
• Purpose
– Function checking
Check the design and
– Timing checking
analysis setup
• Post-layout simulation is slow compared to
RTL simulation.
Perform a full analysis and
examine the results
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Design Review
• After the P&R, review the whole design to
make sure
Phase 3: Design Review and Tape-out – Function
– Timing
– Area
– Power
– ….

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 ECO Example
Engineering Change Order
Module ABC(); Module ABC();
…. ….
• In chip design, ECO is the process of inserting a Y=A&&B; Y=A||B;
…… ……
logic change directly into the Netlist/Layout after endmodule endmodule

they have already been processed by an automatic

Module ABC(); Module ABC();
tool. …. ….
NAND2X1 gate1(Y,A,B); NOR2X1 gate1(Y,A,B);
• Before the chip masks are made, ECOs are usually …… ……
endmodule endmodule
done to save time by avoiding to run the whole
design procedure.
• After masks have been made, ECOs may be done
to save money by changing the layers as least as
possible.
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Tape Out Design Abstract (1)

• The process of transmitting the data to a foundry
who will build your device is called “tape-out”…
you are sending your magnetic tape out.
• Standard format is GDSII (“Gerber Data Stream
Information Interchange”). It includes information
on the layers of your design and the 2D geometries.
• Other file formats:
– CIF (Caltech Interchange Format)
– DXF (Drawing Exchange Format…AutoCAD)
– …

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 Design Abstract (2)
EDA Tools Grouped by Functions
Functions Tools
HDL Simulation Modelsim, NCSIM, VCS
HDL Purification nLint
Code Coverage Analyses ICT, Covermeter
Logic Synthesis Design Compiler, Encounter RTL
Compiler, Synplify
Power Analysis PrimePower, VoltageStorm, Blast
Rail
DFT and ATPG Tools Fastscan, Flextest, Tetramax
Static Timing Analysis PrimeTime, Encounter Timing
Dynamic Timing Analysis Nanosim, Mach TA
IC Layout Virtuoso, ADS
IC Layout Verification Calibre, Diva/Assura, Hercules
RC Extraction Calibre, Diva, Star-RCXT
IC Auto Place/Route Encounter, Astro, Blast Fusion
Signal Integrity Analysis Celtic, Blast Noise, PrimeTime
Formal Verification Formality
Design Abstract (3)
Vendors
Mentor, Cadence, Synopsys
Novas
Cadence, Synopsys
Synopsys, Cadence, Synplicity
Synopsys, Cadence, Magma
Mentor, Mentor, Synopsys
Synopsys, Cadence
Synopsys, Mentor
Cadence, Agilent
Mentor, Cadence, Synopsys
Mentor, Cadence, Synopsys
Cadence, Synopsys, Magma
Cadence, Magma, Synopsys
Synopsys