#2 Integration, the VLSI Journal xxx (xxxx) xxx

Contents lists available at ScienceDirect

Integration, the VLSI Journal

journal homepage: www.elsevier.com/locate/vlsi

Design of a low-power CMOS transceiver for semi-passive wireless sensor

network application
Fadi R. Shahroury
Princess Sumaya University for Technology, Department of Electrical Eng., Amman, Jordan

A R T I C L E I N F O A B S T R A C T

Keywords: A 50 kbps/ISM band (902 − 926 MHz) low power transceiver for short-range wireless sensor networks (WSN) has
Voltage controlled oscillator been designed in 0.18 𝜇m 1-poly-6 metal CMOS technology and occupy 950 𝜇m × 800 𝜇m. The proposed WSN
Differential encoding modulator
transceiver designed based on an improved version of the Amplitude-Shift Keying communication scheme has a
900 MHz ISM band
better continuous RF modulated carrier waveform as well as does not require complex modulator/demodulator
Push-pull power amplifier
Wireless sensor network
circuits. In addition, to reduce power dissipation and increase power efficiency many circuit techniques have
been adopted. The power dissipation and the power efficiency of the proposed WSN transceivers are 1.58 mW
and 21%, respectively.

1. Introduction

Wireless sensor networks (WSN) field is regarded as an evolution-

ary information technology since it has many applications in the areas
of agriculture, industrial monitoring and biomedical systems [1–6]. As
illustrated in Fig. 1, WSN systems consist mainly from the sensor nodes
and a base station where the sensor nodes have full ability to monitor
and collect physical information from the surrounding as well as com-
municate among themselves to transmit the collected data to the base
station [7–9]. The application of WSNs has been heavily hindered by
the limited of their energy source; cost-wise, it is not ecient to replace
the energy source or change a single sensor node after the sensor nodes
network is deployed.
A typical WSN architecture is illustrated in Fig. 2. The sensing sub-
system can be divided into three parts. The first part is sensors and dig-
ital control circuits that include basic sensing devices, Analog-Digital
Converter (ADC), clock generator, multiplexer (MUX), and digital cir-
cuit control. The second part is a communication system responsible
for transmitting and receiving data frames between WSNs and base sta-
tion. The third part is a harvesting system which harvests the required
energy for WSN from the electromagnetic field of a radio communica-
tion signals that radiated through a base station or radiating source via Fig. 1. Wireless sensor network [8].
the air [10,11].
The WSN transceiver can divide into two architectures: passive
transceiver and semi-passive transceiver. In a passive transceiver, the the WSN transceiver has a built-in battery that can be recharged by the
WSN transceiver has no battery. Whereas, in a semi-passive transceiver, harvested energy. The inclusion of a battery in semi-passive transceivers

E-mail address: fadi@psut.edu.jo.

https://doi.org/10.1016/j.vlsi.2019.11.010
Received 19 June 2019; Received in revised form 4 September 2019; Accepted 18 November 2019
Available online XXX
0167-9260/© 2019 Elsevier B.V. All rights reserved.

Please cite this article as: F.R. Shahroury, Design of a low-power CMOS transceiver for semi-passive wireless sensor network application,
Integration, the VLSI Journal, https://doi.org/10.1016/j.vlsi.2019.11.010
F.R. Shahroury
Fig. 2. The semi-passive wireless sensor node system block diagram.
Fig. 3. Waveform of the proposed simplified ASK, ASK, and OOK binary modulated bit stream.
allows prolonging the limited lifetime of WSN while achieving high-
efficiency because they provide the largest percentage from the har-
vested energy to sensor devices in the sensor node [12–15].
The low power transceiver architectures and circuit techniques have
been an active research topic [16–26]. It is to be noted that the modu-
lation scheme did not get as much attention from the researchers as the
architecture of the transceiver circuitries. Further, it is worth mention-
ing that the modulation scheme is a crucial element in transceivers that
are based on energy harvesting from the RF signal. To maximize the
harvested energy, the modulation scheme should support the continu-
ous waveform. In addition, the modulator and demodulator circuitries
for this modulation scheme should be simple and consume low power.
As noted earlier, in principle all the transceiver circuitries and
design techniques depend on the modulation scheme. As an exam-
ple, Phase-Shift Keying (PSK) [18] and Frequency-Shift Keying [20]
have continuous modulated output waveform, which increases the har-
vesting energy. However, FSK/PSK data extraction circuitries consume
large power, due to the complexity of their modulator/demodulator
circuitries. Although both On-Off Keying (OOK) and Amplitude-Shift
2
Integration, the VLSI Journal xxx (xxxx) xxx
Keying (ASK) [16,17,19,21,24–26] modulator/demodulator circuitries
are less complex compared to PSK/FSK, their modulated output wave-
forms are not continuous. Thus, ASK and OOK are not well-suited for
the semi-passive transceiver. In an attempt to achieve continuity in the
output waveform, ASK with a limited modulation index is utilized [22].
However, the main drawback of this attempt is that the amount of har-
vested energy is highly dependent on the sent data. Especially, if the
data contains a long series of zero patterns. Another attempt is asym-
metric communication link transceiver [23], with the aim of achiev-
ing a fair trade-off between maximizing the required harvested energy
and simplifying the demodulator circuitries. In Ref. [23], a continuous
modulated output waveform (FSK) is utilized in the downlink while a
simple demodulator scheme is employed in the uplink (OOK). Though,
this attempt results in the necessity to equip the transceiver with two
antennas; one for uplink and another for downlink, which affects the
complexity, cost, and size of the transceiver.
In this work, a symmetric high-efficiency semi-passive transceiver
suitable for WSNs is proposed. The proposed WSN transceiver designed
based on a communication scheme has continuous modulated output
F.R. Shahroury
waveform as well as does not require complex modulator/demodulator
circuitries. The architecture of the semi-passive wireless sensor node
is depicted in Fig. 2 with the designed work is marked. The WSN
transceiver covers ISM band (902 − 926 MHz) channels with output
Fig. 4. Differential encoding and decoding example for bit stream data of
“1011000101”.
Fig. 5. a) Transmitter block diagram, b) waveform at each node.
3
Integration, the VLSI Journal xxx (xxxx) xxx
power − 6 dBm. The phase noise of the proposed WSN transceiver is
better than −117 dBc/Hz at 1 MHz offset frequency and the received
energy-per-bit is 9 nJ/Bit, while the total power dissipation is 1.58 mW.
This paper is organized as follows: Section 2 presents the principle
of the modulation scheme used in this work, Section 3 discusses the cir-
cuit implementation of all building blocks, Section 4 shows simulation
results, and Section 5 concludes this paper.
2. Modulation scheme
Modulation and demodulation processes are used to transfer digital
data between wireless sensor nodes and base station through the wire-
less channel while ensuring a high degree of fidelity. This is done by
converting digital data to a sinusoidal carrier, where frequency, phase
or amplitude of the sinusoidal carrier is determined by the value of dig-
ital data. If the amplitude of the sinusoidal carrier changes with digital
data, the modulation is known as ASK. If the phase of the sinusoidal
carrier varies with digital data, the modulation is referred to as PSK. If
the frequency of the sinusoidal carrier alters with digital data, the mod-
ulation is termed as FSK. To enhance bit-error-rate and data rate, sev-
eral digital modulation schemes such as minimum shift-keying, quadra-
ture amplitude shift keying, quadrature shift phase keying, etc, have
been used. All of them built upon FSK, PSK and ASK. But the modula-
F.R. Shahroury Integration, the VLSI Journal xxx (xxxx) xxx

tion schemes for the semi-passive system is limited due to constraints

imposed on the carrier frequency and the limited power resource of
semi-passive sensor nodes.
In this work, a simplified version of ASK modulation is used [27,28].
In this modulation, the amplitude of an RF carrier signal varies with
the transition logic level rather than the bit value (as the case in con-
ventional ASK) of the transmitted digital data, as shown graphically in
Fig. 3. This modulation scheme preserves the continuity of the RF car-
rier signal by limiting the amplitude disturbance of the RF modulated
carrier signal which increases the harvesting energy of the semi-passive
sensor node. In addition, this modulation scheme does not require a
complex modulator/demodulator circuitry as will be seen in section 3.
However, this modulation scheme suffers from the deterministic issue
because both of 1 and 0 are transmitted by RF carrier signal with full
power while only a transition logic level is transmitted by RF carrier
signal with zero power. Thus, to demodulate received data, the initial
bit should be known by the receiver.
To solve the deterministic issue without knowing the initially trans-
mitted bit, the differential encoding/decoding technique is used [29]. In

Fig. 6. Positive-edge delay (PED) circuitry.

Fig. 8. Block diagram of the receiver.

Fig. 7. VCO with a push-pull power amplifier circuit.

4
F.R. Shahroury Integration, the VLSI Journal xxx (xxxx) xxx

differential encoding, each digital data bit (Bcurrent (K)) is differentially of digital data is depicted mathematically using
encoded with a previous encoded bit (Bencoded (K − 1)) before modula-
tion. This requires an initial bit with an arbitrary value. The encoding Bencoded (K ) = Bencoded (K − 1) ⊕ Bcurrent (K ), (1)

where ⊕ represents exclusive-OR operation.

In differential decoding, each received bit (Breceived (K)) is differen-
tially encoded with a previously received bit (Breceived (K − 1)) after
demodulation. The encoding of digital data is depicted mathematically
using

Bdecoded (K ) = Breceived (K − 1) ⊕ Breceived (K ). (2)

The example of differential encoding and decoding for digital data is

shown in Fig. 4.

Fig. 9. LNA circuit. Fig. 11. Block diagram of the differential decoder.

Fig. 10. Demodulator circuit.

5
F.R. Shahroury Integration, the VLSI Journal xxx (xxxx) xxx

3. System architecture and circuit design

3.1. Transmitter block diagram

The overall system architecture of the proposed transmitter along

with the waveform at each node is shown in Fig. 5. The proposed trans-
mitter has two main blocks: differential encoding with transition logic
level detector and voltage controlled oscillator (VCO) with a push-pull
power amplifier output stage. The detailed design for these blocks is
given in the following subsection.

3.1.1. Differential encoding and transition logic level detector circuitry

The objective of this block is to differentially encoded transmitted
digital data to resolve the deterministic issue in the receiver part. In
addition, this block will generate an enable pulse whenever the tran-
sition logic level occurs at encoded digital data. In the design of this
block, we should consider two main issues: the duration of the enable
signal (ENB) and power consumption. The duration of ENB should be
chosen as small as possible to minimize amplitude disturbance of RF
Fig. 12. Chip layout of the proposed WSN transceiver.
modulated carrier. The circuit design complexity needs to be reduced
to lower power consumption. To simplify the design complexity Eq. (1)

Fig. 13. Transient simulations of the proposed WSN transceiver.

Fig. 14. VCO output transient simulation.

6
F.R. Shahroury
can be rewritten as follows
{ Fig. 6 shows the positive-edge delay circuitry [30]. This circuit con-
Bencoded (K − 1), if Bcurrent (K ) = 0
Bencoded (K ) = . (3)
Bencoded (K − 1), if Bcurrent (K ) = 1
From the above equation, the transition logic level at encoded digital
data will occur only if logic “one” appears in the current bit (Bcurrent )
of digital data. Thus, the ENB signal should be generated when logic
“high” popped up in digital data. Besides, the pulse width of the ENB
signal should be small to minimize the amplitude disturbance of RF
modulated carrier. This is achieved using the circuit in Fig. 5(a). In this
circuit, positive edge delay (PED) and exclusive-OR gate (G1) are used
to minimize the duty cycle of the data clock signal (CLK) from 50% to
0.15%. The AND gate (G2) detects when a digital data signal (Data)
is one. The duration of the result ENB signal equals the duration of
the signal at node 2, which is 0.15%. The waveform at each node is
Fig. 15. VCO tuning carve simulation.
Fig. 16. VCO phase noise simulation.
7
Integration, the VLSI Journal xxx (xxxx) xxx
illustrated in Fig. 5(b).
sists of three CMOS inverters: MN1 and MP1 represent the first inverter,
MN2 and MP2 represent the second inverter and MN3 and MP3 repre-
sent the third inverter. MN4 controls the discharging rate of the first
inverter. This means that there will be a time delay between vin and vout
when vin rises from low to high. This time delay (Δ) is controlled by C1 ,
C2 and I D4 . Notice that, it should be no time delay between vin and vout
when vin changes from high to low. However, a tiny delay appears due
to the disability of MP1 and MP3 devices to instantaneously discharge
C1 and C2 , respectively. This tiny delay is insignificant and not affect
the circuit operation as will be seen in the simulation section. The (Δ)
is obtained from:
(C1 + C2 )(VDD − Vth )
Δ= . (4)
ID4
From Eq. (4), it is interesting to note that a large capacitor size is
required to minimize the CLK duty cycle into 0.15%. Thus, G1 is added
between the CLK and node 1 to reduce the required capacitor size.
3.1.2. VCO with a push-pull power amplifier circuitry
The function of VCO with a push-pull power amplifier is to gener-
ate an on-chip RF carrier signal to be used to create an RF modulated
carrier signal. The power consumption of the transceiver is dominant
by this circuit. Thus, to minimize the power consumption current-reuse
technique is used. The circuit implementation of VCO with a push-pull
power amplifier is illustrated in Fig. 7. The VCO consists of two cross-
coupled inverters: MN5 and MP5 represent the first inverter and MN6
and MP6 represent the second inverter. The resonant LC-tank is con-
structed by a bonding wire inductor (L1) modeled with a quality fac-
tor of 30 [31], a capacitor (C3) and two PMOS varactors capacitance
(MPC1 & MPC2).
The push-pull power amplifier includes push transistors MN7 and
MN8 and pull-transistors MN9 and M10. In the VCO positive cycle, the
push-transistors push the current toward antenna, while in the VCO
negative cycle the pull-transistors pull the current from the antenna.
Capacitor C12 provides an ac ground at node X so as C9 and C11 at
nodes Y and Z, respectively. In contrast to ac coupling techniques, the
F.R. Shahroury Integration, the VLSI Journal xxx (xxxx) xxx

above approach incurs no signal loss, but it consumes some voltage

headroom. Interestingly, I biase serves as the current source for both VCO

130 nm CMOS
and push-pull power amplifier circuits. To overcome the drawback of

Fabrication
904.5 MHz
the voltage headroom, the bulk terminal of each cross-coupled inverter

−16 dBm

−20 dBm
52 pJ/Bit
402 MHz

228 𝜇 W
transistor connects to the output of another cross-coupled inverter. This

OOK

20.7
[26]

N/S
reducing the threshold voltage of the cross-coupled inverter transistors

67
as well as increasing voltage swing of the push-pull power amplifier.
180 nm CMOS

3.2. Receiver block diagram

Fabrication
457.5 MHz

−22 dBm

−10 dBm
915 MHz

12.4 𝜇 W
7 pJ/Bit
OOK

61.5
30.7
[25]

Fig. 8 shows the architecture of the proposed receiver. The RF mod-

N/S
ulated carrier signal received by the antenna passes through the SAW
filter to reject out-of-band interfering signals. A low noise amplifier
2.405 ~ 2.475 GHz

(LNA) amplifies the received RF signal, while the demodulator extracts

902 ~ 928 MHz

the original encoded digital data. The differential encoder decodes the
−103 dBc/Hz
90 nm CMOS

Fabrication
−12.5 dBm

−17.1 dBm

extracted digital data as depicted earlier in Eq. (2). The detailed design
FSK/OOK

96 pJ/Bit

860 𝜇 W

for these blocks is given in the following subsection.

50.3
21.7
[23]

3.2.1. LNA
The LNA is used to maximize the sensitivity of the receiver, which,
413 ~ 419 MHz
413 ~ 419 MHz

9.2 ~ 42 nJ/Bit

2.84 ~ 5.7 mW
180 nm CMOS

along with the output power of the transmitter, dictates the maximum
Fabrication

range at which nodes can communicate. Aiming at low power and small
−4 dBm

79 dBm

chip size, a self-biased CMOS inverter that does not require additional
122.8
OOK

21.5
[24]

N/S

off-chip inductor is used as depicted in Fig. 9. The LNA circuit consists

of CMOS inverter Mn1 & Mp1 and feedback resistors R1. Capacitor C1
provides an ac ground at the source of Mp1, and Cout represents the
130 nm CMOS

parasitic capacitance at the output node. The gain of the LNA (GLNA ) is
+1.43 dBm

Fabrication
36.6 nJ/Bit
OOK/BPSK

−62 dBm
19.2 mW
3.2 GHz
2.6 GHz

given as:
104.6
18.9
[18]

N/S

GLNA = (gmn + gmp )Zout ‖R1‖ron ‖rop , (5)

Where g mn and g mp are the transconductance of NMOS and PMOS
In the sensitivity calculation, a SAW filter with a 3 dB bandwidth of 25 MHz and 3.5 dB loss is assumed.
2.12 GHz (fixed)
2.12 GHz (fixed)

devices,r on and r op are the output impedance of NMOS and PMOS

35 ~ 44.6 mW
130 nm CMOS

−126 dBc/Hz

devices, and Zout is the impedance of Cout . At operating frequency

Fabrication
460 nJ/Bit
−90 dBm

R1∥r on ∥r op ≫ Zout .Thus, GLNA can be approximated as:

+1 dBm

106.4
20.2
[20]

FSK

(gmn + gmp)
GLNA = (gmn + gmp )Zout = . (6)
𝜔Cout
Where 𝜔 is the operating angular frequency.
−124 dBc/Hz
90 nm CMOS

OOK/2-tone

Fabrication
12.1 nJ/Bit
−83 dBm
915 MHz
915 MHz

−3 dBm

1.9 mW

3.2.2. Demodulator circuit design

122.2
25.3
[17]

Fig. 10 gives a block diagram of the demodulator. The function

of the demodulator is to extract original encoded data. The envelop
detector receives the LNA output signal and provides two outputs: the
−11.4 ~−2.2 dBm
916.5 MHz (fixed)
916.5 MHz (fixed)

6.3 ~ 11.6 mW

envelope (V env ) and it’s average (V ref ). The compare and toggle circuit
−114.3 dBc/Hz
180 nm CMOS

detects amplitude disturbance in RF modulated carrier received signal

Fabrication
2.5 nJ/Bit
−65 dBm

using V env and V ref as inputs. In the envelope, MN1-MN4 are diode-
OOK

18.2
[19]

wired NMOS devices, C1 − C3 are small size charging capacitors and C4

91

is coupling capacitor. MN5 and MN6 provide a path to discharge C1 dur-

ing the presence of an amplitude disturbance in RF modulated carrier
modified version of ASK

received signal. V env follows the peak of the RF received signal when
902 MHz ~ 926 MHz
902 MHz ~ 926 MHz

no amplitude disturbance occurs. If amplitude disturbance appears in

RF received signal, C1 will discharge through MN5. Thus, the voltage
180 nm CMOS

−117 dBc/Hz

across C1 (V env ) will drop for an amount of time that corresponds to

Simulation
This Work

1.58 mW
−80 dBa

amplitude disturbance duration. Meanwhile, MN4 will act as an open

−6 dBm

9 nJ/Bit

113.5

circuit. Hence C2 will discharge slower than C1 and V env will be faster
23.5

tracing the input RF received signal changes than V ref .

Comparison with prior arts.

Compare and toggle circuit consists of a comparator amplifier and

Simulation/Fabrication

a D type flip-flop (D-FF). The function of this circuit is to toggle the

Phase noise @ 1 MHz
Transmit power Pout

output digital bit of D-FF when an amplitude disturbance appears in

Transceiver power

the RF received signal. If an amplitude disturbance appears in the RF

RX energy/bit
RX frequency
TX frequency

Sensitivities
Technology

Modulation

received signal, V ref will be higher than V env . Thus, the comparator
output will be high as well as D-FF will toggle its output digital bit.
Table 1

FoM RX
FoM TX

3.2.3. Differential decoder circuitry

This block is intended to encode the received digital data depicted
in Eq. (2). The detailed circuit for this block is shown in Fig. 11. D-

8
F.R. Shahroury
FF1 and D-FF2 are used to store a current (Breceived (k)) and a previous
(Breceived (k − 1)) encoded received bit, respectively. Exclusive-OR oper-
ation between Breceived (k) and Breceived (k − 1) is done by (G1).
4. Simulation and results
In this section, the post-layout with the extracted parasitic RC netlist
simulation results will be presented. The proposed WSN transceiver has
been designed, verified and simulated in CADENCE custom IC tools.
Shown in Fig. 12 is a photograph layout of the proposed designed
in 0.18 𝜇 m 1-poly-6 metal CMOS technology. The chip layout size is
950 𝜇 m × 800 𝜇 m.
The timing diagram results of the proposed WSN transceiver illus-
trated in Fig. 13. In Fig. 13, the RF the transmitted a digital data is
modulated by an RF carrier of 915 MHz with an amplitude disturbance
duration width of 30 ns, and a digital data rate of 50 kbps. As has been
mentioned in subsection 3, PED should not delay the negative edge of
the CLK. However, due to the disability of the PMOS device to instan-
taneously discharge internal capacitors (C1 &C2 ) of PED glitches appear
at the negative edges of CLK. As seen in Fig. 13, these glitches do not
affect transceiver operation because they are too short to be detected
by the demodulator circuit.
The simulated the RF modulated carrier voltage is 155 mV rms result-
ing in −6 dBm output power from 100 Ω antenna. The total power
dissipation of the proposed WSN transceiver is 1.58 mW from a 1.8 V
power supply. The calculated power efficiency (Epower ) of the proposed
WSN transceiver is 21%, where the power efficiency is given as:
output power
Epower = × 100%. (7)
total power dissipation
Fig. 14 and Fig. 15 show the VCO voltage swing and tuning range,
respectively. The VCO has a voltage swing of 0.5 V and a tuning range
of 24 MHz (902 MHz to 926 MHz). The tuning range of VCO is limited
by the fact that the large parasitic capacitors of the power amplifier
transistors (M7 − M10) appear in parallel to the capacitor (C3) of the
LC tank circuit. The phase noise performance of the VCO is shown in
Fig. 16. The phase noise is −117 dBc/Hz at an offset of 1 MHz.
Table 1 shows the proposed WSN transceiver performance compar-
ison with state-of-the-art designs. The post-layout with the extracted
parasitic RC netlist simulation results of the proposed WSN transceiver
are listed in Table 1. The operation frequency of the proposed WSN
transceiver covers the ISM band (902 ~ 926 MHz) which is less than
2.5% of the unity-gain frequency of 180 nm CMOS device.
To compare the performance of the proposed WSN transceiver, two
figures of merit FoM RX and FoM TX previously presented in Ref. [32]
have been considered herein, which are given by:
FoMRX = −Sensitivity (dBm) − 10 × log(RXpower (W)), (8)
FoMTX = Pout (dBm) − 10 × log(TXpower (W)). (9)
Based on Table 1, it is clear that the proposed WSN transceiver shows
its competitiveness for FoM RX and FoM TX . This has been achieved with-
out sacrificing energy-per-bit, carrier tuning range performances and
phase noise, which demonstrates the effectiveness of the modulation
scheme in enhancing transceiver performance. It is important to men-
tion that, the transceivers in Refs. [23,25,26] have achieved low energy-
per-bit with a good FoM TX as a result of the asymmetric communication
link architecture. In these architectures, the effort and the focus of the
design are redirected from the transceiver circuitries side to the anten-
nas side. In addition, the asymmetric communication link transceivers
require to equip the transceiver with two antennas; one for uplink and
another for downlink, which affects the complexity, cost, and size of
the transceiver.
9
Integration, the VLSI Journal xxx (xxxx) xxx
5. Conclusion
This work describes a low power, high-efficiency transceiver
appropriate for semi-passive WSNs. The proposed WSN transceiver
is designed, simulated, and verified using in 0.18 𝜇 m 1-poly-6
metal CMOS technology. It combines the major building blocks of a
transceiver such as the LNA, VCO, modulator and demodulator circuits,
and power amplifier into one block to enhance the system integrity and
minimize the power consumption. In addition, the proposed modula-
tion scheme helps to simplify the modulator and demodulator circuits
which are positively reected on the size and the power dissipation of
the WSN.
The proposed WSN transceiver covers the (902 − 926 MHz) ISM
band with a 50 kbps data rate. The transmitter output power is −6 dBm.
The phase noise of the implemented VCO is −117dBc/Hz at 1 MHz off-
set. The total power consumption of the proposed WSN transceiver is
1.58 mW. This low power has been achieved without sacrificing trans-
mit output power, energy-per-bit, carrier tuning range performances,
and phase noise. Future research on the design of PLL will be explored
to improve the PVT tolerance of VCO.
Acknowledgments
The author would like to thank EUROPRACTICE for their kind sup-
port by providing the Cadence Spectre Circuit Simulator and the tech-
nology files.
References
[1] F.R. Shahroury, A.A. Mohammad, Design of a passive CMOS implantable
continuous monitoring biosensors transponder front-end, Microelectron. J. 90
(Aug. 2019) 141–153.
[2] M. Sylvain, F. Lehoux, S. Morency, F. Faucher, E. Bharucha, D. Tremblay, F.
Raymond, S. Moineau, M. Allard, J. Corbeil, Y. Messaddeq, B. Gosselin, The
EcoChip: a wireless multi-sensor platform for comprehensive environmental
monitoring, in: 2018 IEEE International Symposium on Circuits and Systems
(ISCAS), IEEE, May 2018.
[3] S. Kisseleff, I.F. Akyildiz, W.H. Gerstacker, Survey on advances in magnetic
induction-based wireless underground sensor networks, IEEE Internet of Things
Journal 5 (6) (Dec. 2018) 4843–4856.
[4] S. Ullo, M. Gallo, G. Palmieri, P. Amenta, M. Russo, G. Romano, M. Ferrucci, A.
Ferrara, M.D. Angelis, Application of wireless sensor networks to environmental
monitoring for sustainable mobility, in: 2018 IEEE International Conference on
Environmental Engineering (EE), IEEE, Mar. 2018.
[5] V. Markevicius, D. Navikas, D. Andriukaitis, M. Cepenas, A. Valinevicius, M. Zilys,
R. Malekian, A. Janeliauskas, W. Walendziuk, A. Idzkowski, Two thermocouples
low power wireless sensors network, AEU - International Journal of Electronics
and Communications 84 (Feb. 2018) 242–250.
[6] H. Bhamra, J.-W. Tsai, Y.-W. Huang, Q. Yuan, J.V. Shah, P. Irazoqui, A subcubic
millimeter wireless implantable intraocular pressure monitor microsystem, IEEE
Transactions on Biomedical Circuits and Systems 11 (6) (Dec 2017) 1204–1215.
[7] R.W.L. Coutinho, A. Boukerche, L.F.M. Vieira, A.A.F. Loureiro, Underwater
wireless sensor networks, ACM Comput. Surv. 51 (1) (Jan 2018) 1–36.
[8] I. Akyildiz, W. Su, Y. Sankarasubramaniam, E. Cayirci, A survey on sensor
networks, IEEE Commun. Mag. 40 (8) (Aug. 2002) 102–114.
[9] T.S. Panag, J. Dhillon, Dual head static clustering algorithm for wireless sensor
networks, AEU - International Journal of Electronics and Communications 88 (May
2018) 148–156.
[10] S.-M. Yu, P. Feng, N.-J. Wu, Passive and semi-passive wireless temperature and
humidity sensors based on EPC generation-2 UHF protocol, IEEE Sens. J. 15 (4)
(Apr. 2015) 2403–2411.
[11] R. Badia-Melis, J. Garcia-Hierro, L. Ruiz-Garcia, T. Jimnez-Ariza, J.I.R. Villalba, P.
Barreiro, Assessing the dynamic behavior of WSN motes and RFID semi-passive
tags for temperature monitoring, Comput. Electron. Agric. 103 (Apr. 2014) 11–16.
[12] J. Pandey, B.P. Otis, A sub-100 W MICS/ISM band transmitter based on
injection-locking and frequency multiplication, IEEE J. Solid State Circuits 46 (5)
(May 2011) 1049–1058.
[13] N.M. Pletcher, S. Gambini, J. Rabaey, A 52 W wake-up receiver with 72 dBm
sensitivity using an uncertain-IF architecture, IEEE J. Solid State Circuits 44 (1)
(Jan 2009) 269–280.
[14] I. Abdo, M. Odeh, F.R. Shahroury, A low-power and high-data rate passive RFID
transceiver using 28-nm CMOS technology, Microelectron. J. 46 (12) (Dec. 2015)
1426–1433.
[15] B. Otis, Y. Chee, J. Rabaey, A 400W-RX, 1.6mW-TX superregenerative transceiver
for wireless sensor networks, in: ISSCC. 2005 IEEE International Digest of
Technical Papers. Solid-State Circuits Conference, 2005, IEEE, Feb. 2005.
F.R. Shahroury
[16] M. Vidojkovic, X. Huang, P. Harpe, S. Rampu, C. Zhou, L. Huang, J. van de
Molengraft, K. Imamura, B. Busze, F. Bouwens, M. Konijnenburg, J. Santana, A.
Breeschoten, J. Huisken, K. Philips, G. Dolmans, H. de Groot, A 2.4 GHz ULP OOK
single-chip transceiver for healthcare applications, IEEE Transactions on
Biomedical Circuits and Systems 5 (6) (Dec. 2011) 523–534.
[17] X. Huang, A. Ba, P. Harpe, G. Dolmans, H. de Groot, J.R. Long, A 915 MHz,
ultra-low power 2-tone transceiver with enhanced interference resilience, IEEE J.
Solid State Circuits 47 (12) (Dec. 2012) 3197–3207.
[18] J.H. Jang, D.F. Berdy, J. Lee, D. Peroulis, B. Jung, A wireless sensor node for
condition monitoring powered by a vibration energy harvester, in: 2011 IEEE
Custom Integrated Circuits Conference (CICC), IEEE, Sep. 2011.
[19] D. Daly, A. Chandrakasan, An energy efficient OOsK transceiver for wireless sensor
networks, in: IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006,
IEEE, June 2006.
[20] M. Flatscher, M. Dielacher, T. Herndl, T. Lentsch, R. Matischek, J. Prainsack, W.
Pribyl, H. Theuss, W. Weber, A bulk acoustic wave (BAW) based transceiver for an
in-tire-pressure monitoring sensor node, IEEE J. Solid State Circuits 45 (1) (Jan
2010) 167–177.
[21] H. Zong, J. Shen, S. Liu, M. Jiang, Q. Ban, L. Tang, F. Meng, X. Wang, An ultra low
power ASK demodulator for passive UHF RFID tag, in: 2011 9th IEEE International
Conference on ASIC, IEEE, Oct. 2011.
[22] D.-M. Wang, J.-G. Hu, J. Wu, An HF passive RFID tag IC with low modulation
index ASK demodulator, IEEE Trans. Ind. Electron. 66 (3) (Mar. 2019) 2164–2173.
[23] G. Papotto, F. Carrara, A. Finocchiaro, G. Palmisano, A 90-nm CMOS 5-Mbps
crystal-less RF-powered transceiver for wireless sensor network nodes, IEEE J.
Solid State Circuits 49 (2) (Feb. 2014) 335–346.
[24] M.-C. Lee, A. Karimi-Bidhendi, O. Malekzadeh-Arasteh, P.T. Wang, A.H. Do, Z.
Nenadic, P. Heydari, A CMOS MedRadio transceiver with supply-modulated power
saving technique for an implantable brainmachine interface system, IEEE J. Solid
State Circuits 54 (6) (Jun 2019) 1541–1552.
10
Integration, the VLSI Journal xxx (xxxx) xxx
[25] H. Bhamra, Y.-J. Kim, J. Joseph, J. Lynch, O.Z. Gall, H. Mei, C. Meng, J.-W. Tsai,
P. Irazoqui, A 24 W, batteryless, crystal-free, multinode synchronized SoC bionode
for wireless prosthesis control, IEEE J. Solid State Circuits 50 (11) (Nov. 2015)
2714–2727.
[26] L. Xia, J. Cheng, N.E. Glover, P. Chiang, 0.56 v, 20 dBm RF-powered, multi-node
wireless body area network system-on-a-chip with harvesting-efficiency tracking
loop, IEEE J. Solid State Circuits 49 (6) (Jun 2014) 1345–1355.
[27] I. Abdo, M. Odeh, F.R. Shahroury, A new modulation scheme for low power
consumption and small size passive RFID tags, in: 2013 IEEE Conference on
Wireless Sensor (ICWISE), IEEE, Dec. 2013.
[28] M. Odeh, I. Abdo, F.R. Shahroury, A low power and high efficiency CMOS
transmitter for wireless sensor network application, in: 2014 UKSim-AMSS 16th
International Conference on Computer Modelling and Simulation, IEEE, Mar.
2014.
[29] B. Razavi, RF Microelectronics, second ed., Prentice Hall, 2011 (Prentice Hall
Communications Engineering and Emerging Technologies Series from Ted
Rappaport).
[30] Z. Li, W. Zhen-hua, L. Yong-ming, Z. Chun, W. Zhi-hua, C. Hong-yi, Clock
generator and OOK modulator for RFID application, J. Zhejiang Univ. Sci. 6 (10)
(Oct. 2005) 1051–1054.
[31] Y.E. Papananos, Radio-Frequency Microelectronic Circuits for Telecommunication
Applications, Springer, 2013.
[32] T. Sano, M. Mizokami, H. Matsui, K. Ueda, K. Shibata, K. Toyota, T. Saitou, H.
Sato, K. Yahagi, Y. Hayashi, 13.4 a 6.3mw BLE transceiver embedded RX
image-rejection filter and TX harmonic-suppression filter reusing on-chip matching
network, in: 2015 IEEE International Solid-State Circuits Conference - (ISSCC)
Digest of Technical Papers, Feb. 2015.