‫ﺗرﺟﻣﺔ اھم ﻣﺎﺟﺎء ﻓﻰ اﻟداﺗﺎﺷﯾت‬

UC1842, UC2842, UC3842, UC1843, UC2843, UC3843

UC1844, UC2844, UC3844, UC1845, UC2845, UC3845
SLUS223E – APRIL 1997 – REVISED JANUARY 2017

UCx84x Current-Mode PWM Controllers

1

1 Features
• Optimized for Off-Line and DC-to-DC Converters The UCx84x family offers a variety of package
• Low Start-Up Current (< 1 mA) options, temperature range options, choice of
maximum duty cycle, and choice of turnon and turnoff
• Automatic Feedforward Compensation thresholds and hysteresis ranges. Devices with
• Pulse-by-Pulse Current Limiting higher turnon or turnoff hysteresis are ideal choices
• Enhanced Load-Response Characteristics for off-line power supplies, while the devices with a
narrower hysteresis range are suited for DC-DC
• Undervoltage Lockout With Hysteresis
applications. The UC184x devices are specified for
• Double-Pulse Suppression operation from –55°C to 125°C, the UC284x series is

/‫م‬
• High-Current Totem-Pole Output specified for operation from –40°C to 85°C, and the
• Internally Trimmed Bandgap Reference UC384x series is specified for operation from 0°C to
70°C.
• Up to 500-kHz Operation
• Error Amplifier With Low Output Resistance Device Information(1)

‫ا‬
PART NUMBER PACKAGE (PIN) BODY SIZE (NOM)

‫ﺣﻣ‬
2 Applications CDIP (8) 9.60 mm × 6.67 mm
• Switching Regulators of Any Polarity UC184x LCCC (20) 8.89 mm × 8.89 mm
• Transformer-Coupled DC-DC Converters CFP (8) 9.21 mm × 5.97 mm

3 Description
The UCx84x series of control integrated circuits
provide the features that are necessary to implement
‫دﯾ‬ UC284x
SOIC (8)
SOIC (14)
PDIP (8)
SOIC (8)
4.90 mm × 3.91 mm
8.65 mm × 3.91 mm
9.81 mm × 6.35 mm
4.90 mm × 3.91 mm
‫وﺳ‬
off-line or DC-to-DC fixed-frequency current-mode
SOIC (14) 8.65 mm × 3.91 mm
control schemes, with a minimum number of external UC384x
components. The internally implemented circuits PDIP (8) 9.81 mm × 6.35 mm
include an undervoltage lockout (UVLO), featuring a CFP (8) 9.21 mm × 5.97 mm
start-up current of less than 1 mA, and a precision
‫ف‬

(1) For all available packages, see the orderable addendum at

reference trimmed for accuracy at the error amplifier the end of the datasheet.
input. Other internal circuits include logic to ensure
latched operation, a pulse-width modulation (PWM)
comparator that also provides current-limit control,
and a totem-pole output stage that is designed to
‫اﻟﻣ‬

source or sink high-peak current. The output stage,

suitable for driving N-channel MOSFETs, is low when
it is in the off state.
‫ﺻ‬

Simplified Application
VIN
‫رى‬

VCC OUTPUT

VREF ISENSE

UC2843

VFB
RT/CT

GROUND COMP

Copyright © 2016, Texas Instruments Incorporated

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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5 Device Comparison Table

UVLO
TURNON AT 16 V TURNON AT 8.4 V
TURNOFF AT 10 V TURNOFF AT 7.6 V TEMPERATURE RANGE MAX DUTY CYCLE
SUITABLE FOR OFF-LINE SUITABLE FOR DC-DC
APPLICATIONS APPLICATIONS
UC1842 UC1843 –55°C to 125°C
UC2842 UC2843 –40°C to 85°C Up to 100%
UC3842 UC3843 0°C to 70°C
UC1844 UC1845 –55°C to 125°C

‫م‬
UC2844 UC2845 –40°C to 85°C Up to 50%
UC3844 UC3845 0°C to 70°C

‫ھﻧﺎك ﺛﻼث ﻣودﯾﻼت ﻣﺧﺗﻠﻔﺔ ﻟﻼﯾﺳﻰ ﻛﻣﺎ ﻓﻰ اﻟﺷﻛل‬

/
6 Pin Configuration and Functions

‫اﺣ‬
D, JG, and P Packages
8-Pin SOIC, CDIP, and PDIP D and W Packages
Top View 14-Pin SOIC and CFP

‫ﻣد‬
Top View

COMP 1 8 VREF COMP 1 14 VREF

NC 2 13 NC
VFB 2 7 VCC
‫ﯾ‬ VFB 3 12 VCC
ISENSE 3 6 OUTPUT
‫وﺳ‬
NC 4 11 VC
RT/CT 4 5 GROUND
ISENSE 5 10 OUTPUT

NC 6 9 GROUND

7 8 PWRGND
‫ف‬

RT/CT

FK Package
20-Pin LCCC
Top View
‫اﻟﻣ‬
COMP

VREF
NC

NC

NC

3 2 1 20 19
‫ﺻ‬

NC 4 18 VCC
VFB 5 17 VC
‫رى‬

NC 6 16 NC
ISENSE 7 15 OUTPUT
NC 8 14 NC
9 10 11 12 13
NC
RT/CT
NC
PWRGND
GROUND

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Pin Functions
PIN
SOIC,
SOIC, TYPE DESCRIPTION
CDIP, LCCC
NAME CFP
PDIP (20)
(14)
(8)

COMP 1 1 2 O ‫ﺧرج ﻣﻘﺎرن اﻟﺧطﺎ‬

‫ارﺿﻰ‬ Analog ground. For device packages without PWRGND, GROUND

GROUND 5 9 13 G
functions as both power ground and analog ground.

PWRGND ‫ﺑﺎﻟﻛﺑﯾرة‬
— ‫ﺧﺎص‬ 8 12 G
Power ground. For device packages without PWRGND, GROUND

‫م‬
functions as both power ground and analog ground

ISENSE 3 5 7 I ‫ﺗﺣﺳس ﺗﯾﺎر اﻟﻣوﺳﻔت‬

/
1, 3, 4, 6,

‫اﺣ‬
NC — 2, 4, 6, 13 8, 9, 11, — Do not connect ‫ﻓﺎرغ‬
14, 16, 19

‫ اﻣﺑﯾر‬1 ‫ﺗﺷﻐﯾل ﺑواﺑﺔ اﻟﻣوﺳﻔت وﯾﻌطﻰ ﺗﯾﺎر اﻟﻰ‬

‫ﻣد‬
OUTPUT 6 10 15 O

‫ﯾ‬ ‫ﯾﺗم ﺣﺳﺎب ﺗردد اﻻﯾﺳﻰ ﺑﺎﻟﻘﺎﻧون اﻟﺗﺎﻟﻰ ﺣﯾث اﻟﺗردد ﯾﻘﺎس ﺑﺎﻟﮭﯾرﺗز واﻟﻣﻘﺎوﻣﺔ ﺑﺎﻻوم‬
‫واﻟﻣﻛﺛف ﺑﺎﻟﻔﺎراد‬
‫وﺳ‬
1.72
fOSC = (1)
RRT × CCT
‫ ﻛﯾﻠو اوم‬5 ‫ﻻﺗﻘم ﺑﺎﺳﺗﺧدام ﻣﻘﺎوﻣﺔ ﻟﻠﺗردد اﻗل ﻣن‬
RT/CT 4 7 10 I/O
‫ف‬

‫ و‬3842 ‫ﺗردد اﻟﺗﻘطﯾﻊ او ﺗﺷﻐﯾل اﻟﻣوﺳﻔت ھو ﻧﻔﺳﮫ ﺗردد اﻟﻣذﺑذب اﻟداﺧﻠﻰ ﻟﻼﯾﺳﻰ ﻣودﯾل‬
‫ ﺗردد اﻟﺗﻘطﯾﻊ ھو ﻧﺻف ﺗردد اﻟﻣذﺑذب اﻟداﺧﻠﻰ‬3845‫ و‬3844 ‫ ﺑﯾﻧﻣﺎ ﻟﻼﯾﺳﯾﮭﺎت‬- 3843
%50 ‫ﻟﻼﯾﺳﻰ ﻋﻧد دﯾوﺗﻰ ﺳﯾﻛل‬
‫اﻟﻣ‬

Bias supply input for the output gate drive. For PWM controllers that
‫ﺧﺎص ﺑﺎﻻﯾﺳﻰ اﻟﻛﺑﯾرة‬ do not have this pin, the gate driver is biased from the VCC pin. VC
‫ﺻ‬

VC — 11 17 I
must have a bypass capacitor at least 10 times greater than the gate
capacitance of the main switching FET used in the design.

‫ ﺗﯾﺎر ﺑواﺑﺔ اﻟﻣوﺳﻔت‬+ ‫ﺟﮭد اﻟﺗﻐذﯾﺔ ﻟﻼﯾﺳﻰ وھو ﯾﻐذى اﻻﯾﺳﻰ ﺑﺎﻟﺗﯾﺎر اﻟﻼزم ﻟﻠﺗﺷﯾﻐل‬
‫رى‬

I = Q g × fSW
‫واﻟﺳورس ﻣن‬OUTPUT
‫اﻟﻣﻛﺛف ﺑﯾن اﻟﺑواﺑﺔ‬ ‫ﯾﻣﻛن ﺣﺳﺎب ﺗﯾﺎر ﺑواﺑﺔ اﻟﻣوﺳﻔت وھو ﺗﯾﺎر ﺷﺣن‬
: ‫ﺧﻼل ﻣﻌرﻓﺔ ﺗردد اﻻﯾﺳﻰ وﺷﺣﻧﺔ ﻣﻛﺛف اﻟﺑواﺑﺔ ﻣن اﻟﻌﻼﻗﺔ اﻟﺗﺎﻟﯾﺔ‬

VCC 7 12 18 I ‫ﺗﯾﺎر اﻟﺑواﺑﺔ‬ (2)

VFB 2 3 5 I ‫ﻣدﺧل اﻟﻔﯾدﺑﺎك‬

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Pin Functions (continued)

PIN
SOIC,
SOIC, TYPE DESCRIPTION
CDIP, LCCC
NAME CFP
PDIP (20)
(14)
(8)

‫ ﻓوﻟت ﻣن داﺧل اﻻﯾﺳﻰ ﻟﺗﻐذﯾﺔ داﺋرة ﻣﻛﺛف اﻟﺗردد ﯾﻔﺿل رﺑط‬5 ‫ﺟﮭد ﻣرﺟﻌﻰ ﻗﯾﻣﺗﮫ‬
VREF 8 14 20 O ‫ ﻣﯾﻛرو ﻓﺎراد ﻋﻠﻰ ھذا اﻟﻣدﺧل‬0.1 ‫ﻣﻛﺛف‬

/ ‫م‬
‫اﺣ‬
‫ﯾ‬ ‫ﻣد‬
‫وﺳ‬
‫ف‬
‫اﻟﻣ‬
‫ﺻ‬
‫رى‬

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7 Specifications
7.1 Absolute Maximum Ratings ‫اﻗﺻﻰ ﻗﯾم ﻟﻼﯾﺳﻰ‬

over operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNIT
‫ﺟﮭد اﻟﺷﺗﻐﯾل‬ Low impedance source 30 V
VVCC
IVCC < 30 mA ‫ ﻣﯾﻠﻠﻰ اﻣﺑﯾر‬30 ‫ﺗﯾﺎر اﻟﺷﺣن اﻗل ﻣن‬ Self Limiting
VVFB and VISENSE Analog input voltage ‫ﺟﮭد ﻣدﺧل ﺗﺣﺳس اﻟﺗﯾﺎر وﻣدﺧل اﻟﻔﯾدﺑﺎك‬ –0.3 6.3 V
VVC ‫ ﺟﮭد اﻟدﺧل‬Input Voltage, Q and D Package only ‫ﻟﻼﯾﺳﯾﮭﺎت اﻟﻛﺑﯾرة‬ 30 V
IOUTPUT Output drive current ‫ﺗﯾﺎر ﻣدﺧل ﺗﺷﻐﯾل اﻟﺑواﺑﺔ‬ ±1 A
ICOMP Error amplifier output sink current ‫ﺗﯾﺎر اﻟﺳﺣب ﻟﺧرج ﻣﻘﺎرن اﻟﺧطﺎ‬ 10 mA

‫م‬
EOUTPUT Output energy (capacitive load) 5 µJ
TJ Junction temperature 150 °C

/
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

‫اﺣ‬
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

‫ﻣد‬
VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±3000
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±3000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
‫ﯾ‬
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
‫وﺳ‬
7.3 Recommended Operating Conditions ‫ظروف اﻟﺗﺷﻐﯾل اﻟﻣوﺻﻰ ﺑﮭﺎ‬
over operating free-air temperature range (unless otherwise noted) ‫اﻗل‬ ‫اﻟﻌﺎدى‬ ‫اﻗﺻﻰ‬
MIN TYP MAX UNIT
‫ف‬

VVCC and VVC (1)

Supply voltage ‫ﺟﮭد اﻟﺷﺗﻐﯾل‬ 12 28 V
VVFB Input voltage ‫ﺟﮭد ﻣدﺧل اﻟﻔﯾدﺑﺎك‬ 2.5 V
VISENSE Input voltage ‫ﺟﮭد ﻣدﺧل ﺗﺣﺳس ﺗﯾﺎر اﻟﻣوﺳﻔت‬ 1 V
IVCC Supply current, externally limited ‫ﺗﯾﺎر ﺗﺷﻐﯾل اﻻﯾﺳﻰ‬ 25 mA
‫اﻟﻣ‬

IOUTPUT Average output current ‫ﻣﻌدل ﺗﯾﺎر اﻟﻣﺧرج‬ 200 mA

IVREF Reference output current –20 mA
fOSC Oscillator frequency ‫ﺗردد اﻟﺗﺷﻐﯾل‬ ‫ اﻟﻌﺎدى‬100 500 kHz
‫ﺻ‬

UC184x –55 125

TA Operating free-air temperature UC284x –40 85 °C
UC384x 0 70
‫رى‬

(1) These recommended voltages for VC and POWER GROUND apply only to the D package.

7.4 Thermal Information

UCx84x
THERMAL METRIC (1) D (SOIC) D (SOIC) P (PDIP) FK (LCCC) UNIT
8 PINS 14 PINS 8 PINS 20 PINS
RθJA Junction-to-ambient thermal resistance 104.8 78.2 53.7 — °C/W
RθJC(top) Junction-to-case (top) thermal resistance 47.3 37.1 46.7 36.2 °C/W
RθJB Junction-to-board thermal resistance 45.9 32.6 31 35.4 °C/W
ψJT Junction-to-top characterization parameter 8.2 7.3 17.1 — °C/W
ψJB Junction-to-bottom characterization parameter 45.2 32.4 30.9 — °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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Thermal Information (continued)

UCx84x
THERMAL METRIC (1) D (SOIC) D (SOIC) P (PDIP) FK (LCCC) UNIT
8 PINS 14 PINS 8 PINS 20 PINS
RθJC(bottom) Junction-to-case (bottom) thermal resistance — — — 4.1 °C/W

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) –55°C ≤ TA ≤ 125°C for the UC184x; –40°C ≤ TA ≤ 85°C
for the UC284x, 0°C ≤ TA ≤ 70°C for the UC384x, VVCC = 15 V (1); 0.1 µF capacitor from VCC to GROUND, 0.1 µF capacitor
from VREF to GROUND, RRT = 10 kΩ; CCT = 3.3 nF, TJ = TA.

‫م‬
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE SECTION ‫اﻟﺟزء اﻟﺧﺎص ﺑﺎﻟﺟﮭد اﻟﻣرﺟﻌﻰ‬
‫اﻟﺟﮭد اﻟﻣرﺟﻌﻰ‬ UC184x

/
and 4.95 5 5.05
VVREF Reference voltage IVREF = 1 mA, TJ = 25°C UC284x V
UC384x 4.9 5 5.1

‫اﺣ‬
Line regulation 12 ≤ VCC ≤ 25 V 6 20 mV
Load regulation 1 ≤ IVREF ≤ 20 mA 6 25 mV
(2) (3)

‫ﻣد‬
Temperature stability See 0.2 0.4 mV/°C
UC184x
(2)
and 4.9 5.1
Total output variation Line, load, temperature UC284x V
UC384x 4.82 5.18
Output noise voltage
‫ﯾ‬ 10 Hz ≤ fOSC ≤ 10 kHz, (2)
TJ = 25°C 50 μV
‫وﺳ‬
(2)
Long term stability TA = 125°C, 1000 Hrs 5 25 mV
Output short circuit –30 –100 –180 mA
OSCILLATOR SECTION ‫ﺗردد اﻻﯾﺳﻰ‬
fOSC Initial accuracy TJ = 25°C (4) 47 52 57 kHz
‫ف‬

Voltage stability 12 ≤ VCC ≤ 25 V 0.2% 1%

(2)
Temperature stability TMIN ≤ TA ≤ TMAX 5%
(2)
VRT/CT Amplitude Peak-to-peak 1.7 V
ERROR AMPLIFIER SECTION ‫ﻣﻘﺎرن اﻟﺧطﺎ‬
‫اﻟﻣ‬

UC184x
2.5V = ‫ﻋﻧد ﺟﮭد ﺧرج ﻟﻠﻣﻘﺎرن‬ and 2.45 2.5 2.55
VVFB Input voltage ‫ﺟﮭد دﺧل اﻟﻔﯾدﺑﺎك‬ UC284x V
UC384x 2.42 2.5 2.58
‫ﺻ‬

‫ﺗﯾﺎر ﻣدﺧل اﻟﻔﯾدﺑﺎك‬ UC184x

and –1
IVFB Input bias current UC284x µA
‫رى‬

UC384x –2
AVOL 2 ≤ VCOMP ≤ 4 V 65 90 dB
(2)
Unity gain bandwidth TJ = 25°C 0.7 1 MHz
PSRR Power supply rejection ratio 12 ≤ VCC ≤ 25 V 60 70 dB
I(snk) COMP sink current VVFB = 2.7 V, VCOMP = 1.1 V 2 6
mA
I(src) COMP source current VVFB = 2.3 V, VCOMP = 5 V –0.5 –0.8

(1) Adjust VCC above the start threshold before setting at 15 V

(2) Specified by design. Not production tested.
(3) Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:
VREF:max ; F VREF:min ;
Temp Stability =
TJ:max ; F TJ:min ; VREFmin and VREFmax are the maximum and minimum reference voltages
measured over the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in
temperature.
(4) OUTPUT switching frequency, fSW, equals the oscillator frequency, fOSC, for the UCx842 and UCx843. OUTPUT switching frequency,
fSW, is one half oscillator frequency, fOSC, for the UCx844 and UCx845.
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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted) –55°C ≤ TA ≤ 125°C for the UC184x; –40°C ≤ TA ≤ 85°C
for the UC284x, 0°C ≤ TA ≤ 70°C for the UC384x, VVCC = 15 V(1); 0.1 µF capacitor from VCC to GROUND, 0.1 µF capacitor
from VREF to GROUND, RRT = 10 kΩ; CCT = 3.3 nF, TJ = TA.
‫اﻟﻌﻧﺻر‬ ‫ظروف اﻟﺗﺷﻐﯾل‬ ‫اﻗل ﻗﯾﻣﺔ‬ ‫اﻟﻌﺎدى‬ ‫اﻻﻋﻠﻰ‬ UNIT
VCOMP ‫ﺟﮭد ﺧرج اﻟﻣﻘﺎرن ﻋﻧدﻣﺎ ﯾﻛون ﻋﺎﻟﻰ‬
High-level output voltage VVFB = 2.3 V, RL = 15-kΩ COMP to GROUND 5 6
High
‫ﺟﮭد ﺧرج ﻣﻘﺎرن اﻟﺧطﺎ ﻋﻧدﻣﺎ ﯾﻛون ﻣﻧﺧﻔض‬ V
VCOMP
Low-level output voltage VVFB = 2.7 V, RL = 15-kΩ COMP to VREF 0.7 1.1
Low
CURRENT SENSE SECTION ‫اﻟﺟزء اﻟﺧﺎص ﺑﺗﺣﺳس ﺗﯾﺎر اﻟﻣوﺳﻔت‬
ACS Gain ‫اﻟﻛﺳب‬ See (5) (6)
2.85 3 3.15 V/V

‫م‬
(5)
VISENSE ‫اﻗﺻﻰ ﻗﯾﻣﺔ ﻻﺷﺎرة اﻟدﺧل ﻟﻠﻣﻘﺎرن‬ VCOMP = 5 V ‫ ﻓوﻟت‬5 ‫ﻋﻧد ﺧرج ﻣﻘﺎرن اﻟﺧطﺎ‬ 0.9 1 1.1 V
(2) (5)
PSRR Power supply rejection ratio 12 V ≤ VVCC ≤ 25 V 70 dB
Input bias current ‫ﺗﯾﺎر اﻟﺗﻐذﯾﺔ اﻟداﺧﻠﻰ‬

/
IISENSE –2 –10 µA
(2)
tDLY Delay to output VISENSE stepped from 0 V to 2 V 150 300 ns
OUTPUT SECTION ‫اﻟﺟزء اﻟﺧﺎص ﺑﺧرج اﻻﯾﺳﻰ ﻟﻠﺑواﺑﺔ‬

‫اﺣ‬
‫ﺟﮭد ﻣدﺧل اﻟﺧرج ﻟﻼﯾﺳﻰ اﻟﻣﻧﺧﻔض‬ ISINK = 20 mA 0.1 0.4
VOUT Low Low-level OUTPUT voltage V
ISINK = 200 mA 1.5 2.2
‫ﺟﮭد اﻟﺧرج اﻟﻌﺎﻟﻰ وھو ﺟﮭد ﺗﺷﻐﯾل ﺑواﺑﺔ اﻟﻣوﺳﻔت‬

‫ﻣد‬
ISOURCE = 20 mA 13 13.5
VOUT High High-level OUTPUT voltage V
ISOURCE = 200 mA 12 13.5
(2)
tRISE Rise time COUTPUT = 1 nF, TJ = 25°C 50 150 ns
(2)
tFALL Fall time COUTPUT = 1 nF, TJ = 25°C, 50 150 ns
UNDERVOLTAGE LOCKOUT (UVLO) ‫اﻟﺟزء اﻟﺧﺎص ﺑﺎﻟﺣﻣﺎﯾﺔ ﻣن اﻧﺧﻔﺎض ﺟﮭد اﻟﺗﺷﻐﯾل‬
‫ﯾ‬
‫وﺳ‬
UC184x
‫ﺟﮭد ﺗﺷﻐﯾل اﻻﯾﺳﻰ او اﻟذى ﺗﺑدا ﻋﻧده اﻻﯾﺳﻰ اﻟﻌﻣل‬ UCx842/4 and 15 16 17
‫ ﻓوﻟت‬10 ‫ وﺗﻘف ﻋﻧد‬16 ‫ﺗﺷﺗﻐل ﻋﻧد‬ UC284x
VCCON Enable threshold V
UCx843/5 UC384x 14.5 16 17.5
UCx843/5 7.6 ‫ وﺗﻘف ﻋﻧد‬8.4 ‫ﺗﺷﺗﻐل ﻋﻧد‬ 7.8 8.4 9
‫ف‬

‫اﻟﺟﮭد اﻟﻣﻧﺧﻔض اﻟذى ﺗﻘف ﻋﻧده اﻻﯾﺳﻰ ﻋن اﻟﻌﻣل‬ UC184x

UCx842/4 and 9 10 11
UC284x
VCCOFF UVLO off threshold V
UCx843/5 UC384x 8.5 10 11.5
‫اﻟﻣ‬

UCx843/5 7 7.6 8.2

PWM ‫اﻟدﯾوﺗﻰ ﺳﯾﻛل‬
UCx842/3 95% 97% 100%
UC184x
‫ﺻ‬

DMAX Maximum duty cycle and 46% 48% 50%

UCx844/5 UC284x
UC384x 47% 48% 50%
‫رى‬

DMIN Minimum duty cycle 0%

TOTAL STANDBY CURRENT ‫ﺗﯾﺎر اﻻﻧﺗظﺎر‬
IVCC Start-up current ‫ﺗﯾﺎر ﺑدء اﻟﺗﺷﻐﯾل‬ 0.5 1
mA
IVCC Operating supply current VVFB = VISENSE= 0 V ‫ﺗﯾﺎر اﻟﺗﺷﻐﯾل‬ 11 17
VCC Zener voltage ‫ زﯾﻧر اﻟﺣﻣﺎﯾﺔ‬IVCC = 25 mA 30 34 V

(5) Parameter measured at trip point of latch with VFB = 0 V.

(6) Gain defined as: A = ΔVCOMP/ΔVISENSE, 0 V ≤ VISENSE ≤ 0.8 V.

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8 Detailed Description

8.1 Overview
The UCx84x series of control integrated circuits provide the features necessary to implement AC-DC or DC-to-
DC fixed-frequency current-mode control schemes with a minimum number of external components. Protection
circuitry includes undervoltage lockout (UVLO) and current limiting. Internally implemented circuits include a
start-up current of less than 1 mA, a precision reference trimmed for accuracy at the error amplifier input, logic to
ensure latched operation, a pulse-width modulation (PWM) comparator that also provides current-limit control,
and a totem-pole output stage designed to source or sink high-peak current. The output stage, suitable for driving
N-channel MOSFETs, is low when it is in the off-state.
Major differences between members of these series are the UVLO thresholds, acceptable ambient temperature

‫م‬
range, and maximum duty-cycle. Typical UVLO thresholds of 16 V (ON) and 10 V (OFF) on the UCx842 and
UCx844 devices make them ideally suited to off-line AC-DC applications. The corresponding typical thresholds
for the UCx843 and UCx845 devices are 8.4 V (ON) and 7.6 V (OFF), making them ideal for use with regulated

/
input voltages used in DC-DC applications. The UCx842 and UCx843 devices operate to duty cycles
approaching 100%. The UCx844 and UCx845 obtain a duty-cycle range of 0% to 50% by the addition of an
internal toggle flip-flop, which blanks the output off every other clock cycle.

‫اﺣ‬
The UC184x-series devices are characterized for operation from –55°C to 125°C. UC284x-series devices are
characterized for operation from −40°C to 85°C. The UC384x devices are characterized for operation from 0°C to

‫ﻣد‬
70°C.

8.2 Functional Block Diagrams

‫ﯾ‬
‫وﺳ‬
VCC
UVLO
34 V EN 5-V
Reference VREF
GROUND
‫ف‬

Internal
Bias VC
2.5 V
VREF Good
Logic
‫اﻟﻣ‬

RT/CT Osc OUTPUT

‫ﺻ‬

S
+ 2R PWRGND
E/A PWM
VFB R Latch
R 1V
‫رى‬

PWM
COMP Comparator

ISENSE
UCx842
UCx843

Copyright © 2016, Texas Instruments Incorporated

Figure 11. UCx842 and UCx843 Block Diagram, No Toggle

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Functional Block Diagrams (continued)

VCC
UVLO
34 V EN 5-V
Reference VREF
GROUND
Internal
Bias VC
2.5 V
VREF Good
Logic

‫م‬
RT/CT Osc OUTPUT
T

/
S
2R

‫اﺣ‬
+ PWRGND
E/A PWM
VFB R Latch
R 1V
PWM

‫ﻣد‬
COMP Comparator

ISENSE
UCx844
‫ﯾ‬ UCx845
‫وﺳ‬
Copyright © 2016, Texas Instruments Incorporated

Figure 12. UCx844 and UCx845 Block Diagram, Toggle

‫ف‬

8.3 Feature Description

8.3.1 Detailed Pin Description

8.3.1.1 COMP ‫ﺧرج ﻣﻘﺎرن اﻟﺧطﺄ‬

‫اﻟﻣ‬

The error amplifier in the UCx84x family is an open collector in parallel with a current source, with a unity-gain
bandwidth of 1 MHz. The COMP terminal can both source and sink current. The error amplifier is internally
current-limited, so that one can command zero duty cycle by externally forcing COMP to GROUND.
‫ﺻ‬

8.3.1.2 VFB ‫ﻣدﺧل اﻟﻔﯾدﺑﺎك‬

VFB is the inverting input of the error amplifier. VFB is used to control the power converter voltage-feedback loop
‫رى‬

for stability. For best stability, keep VFB lead length as short as possible and VFB stray capacitance as small as
possible.

8.3.1.3 ISENSE ‫ﺗﺣﺳس ﺗﯾﺎر اﻟﻣوﺳﻔت‬

The UCx84x current sense input connects to the PWM comparator. Connect ISENSE to the MOSFET source
current sense resistor. The PWM uses this signal to terminate the OUTPUT switch conduction. A voltage ramp
can be applied to this pin to run the device with a voltage mode control configuration or to add slope
compensation. To prevent false triggering due to leading edge noises, an RC current sense filter may be
required. The gain of the current sense amplifier is typically 3 V/V.

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Feature Description (continued)

8.3.1.4 RT/CT ‫ﻣﻘﺎوﻣﺔ وﻣﻛﺛف ﺗﺣدﯾد ﺗردد اﻻﯾﺳﻰ‬
RT/CT is the oscillator timing pin. For fixed frequency operation, set the timing capacitor charging current by
connecting a resistor from VREF to RT/CT. Set the frequency by connecting timing capacitor from RT/CT to
GROUND. For the best performance, keep the timing capacitor lead to GROUND as short and direct as possible.
If possible, use separate ground traces for the timing capacitor and all other functions.
1.72
The UCx84x’s oscillator allows
fOSCfor
= operation to 500 kHz. The device uses an external resistor to set the charging
Rhich×deter
C RT CT
current for the external capacitor, w mines the oscillator frequency. The recommended range of timing

‫م‬
resistor values is between 5 kΩ and 100 kΩ; the recommended range of timing capacitor values is between 1 nF
and 100 nF.
(3)

/
In this equation, the switching frequency, fSW is in Hz, RRT is in Ω, and CCT is in Farads.

8.3.1.5 GROUND ‫ارﺿﻰ‬

‫اﺣ‬
GROUND is the signal and power returning ground. TI recommends separating the signal return path and the
high current gate driver path so that the signal is not affected by the switching current.

‫ﻣد‬
8.3.1.6 OUTPUT ‫ﺗﺷﻐﯾل اﻟﺑواﺑﺔ ﻟﻠﻣوﺳﻔت‬
The high-current bipolar totem-pole output of the UCx84x devices sinks or sources up to 1-A peak of current.
The OUTPUT pin can directly drive a MOSFET. The OUTPUT of the UCx842 and UCx843 devices switches at
the same frequency as the oscillator and can operate near 100% duty cycle. In the UCx844 and UCx845
‫ﯾ‬
devices, the switching frequency of OUTPUT is one-half that of the oscillator due to an internal T flipflop. This
‫وﺳ‬
limits the maximum duty cycle in the UCx844 and UCx845 to < 50%. Schottky diodes may be necessary on the
OUTPUT pin to prevent overshoot and undershoot due to high impedance to the supply rail and to ground,
respectively. A bleeder resistor, placed between the gate and the source of the MOSFET, should be used to
prevent activating the power switch with extraneous leakage currents during undervoltage lockout. An external
‫ف‬

clamp circuit may be necessary to prevent overvoltage stress on the MOSFET gate when VCC exceeds the gate
voltage rating.
‫واﻟﺗﯾﺎر اﻟﻛﻠﻰ اﻟﻣﺳﺗﮭﻠك = ﺗﯾﺎر اﻟﺗﻐذﯾﺔ‬ ‫ ﻣﻠﻠﻰ اﻣﺑﯾر‬0.5 = ‫اﻟﺗﯾﺎر اﻟذى ﺗﺳﺗﮭﻠﻛﮫ اﻻﯾﺳﻰ ﻓﻰ ﺗﻐذﯾﺔ دواﺋرھﺎ اﻟداﺧﻠﯾﺔ‬
8.3.1.7 VCC
‫ اﻟﺗﯾﺎر اﻟﺧﺎرج ﻟﻠﺑواﺑﺔ‬+
‫اﻟﻣ‬

IOUTPUT = Q g × fSW ‫اﻟﺗﯾﺎر اﻟﺧﺎرج ﻟﺷﺣن ﻣﻛﺛف اﻟﺑواﺑﺔ واﻟﺳورس = ﺷﺣﻧﺔ اﻟﺑواﺑﺔ * ﺗردد اﻟﺗﺷﻐﯾل‬
‫ﺻ‬

‫ﯾﺗم ﻣﻌرﻓﺔ ﺷﺣﻧﺔ اﻟﺑواﺑﺔ ﻣن اﻟداﺗﺎﺷﯾت ﻟﻠﻣوﺳﻔت وھﻰ ﺗﺣﺳب ﺑﺎﻟﻛوﻟوم‬

(4)
The UCx84x has a VCC supply voltage clamp of 34 V typical, but the absolute maximum value for VCC from a
‫رى‬

low-impedance source is 30 V. For applications that have a higher input voltage than the recommended VCC
voltage, place a resistor in series with VCC to increase the source impedance. The maximum value of this
resistor is calculated with Equation 5.
VIN :min ; F VVCC :max ;
R VCC :max ; =
IVCC + kQ g × fSW o (5)
In Equation 5, VIN(min) is the minimum voltage that is used to supply VCC, VVCC(max) is the maximum VCC clamp
voltage and IVCC is the IC supply current without considering the gate driver current and Qg is the external power
MOSFET gate charge and fSW is the switching frequency.
The turnon and turnoff thresholds for the UCx84x family are significantly different: 16 V and 10 V for the UCx842
and UCx844; 8.4 V and 7.6 V for the UCx843 and UCx855. To ensure against noise related problems, filter VCC
with an electrolytic and bypass with a ceramic capacitor to ground. Keep the capacitors close to the IC pins.

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Feature Description (continued)

8.3.1.8 VREF ‫ ﻓوﻟت‬5 = ‫ﺟﮭد اﻟﻣرﺟﻊ‬
VREF is the voltage reference for the error amplifier and also for many other internal circuits in the IC. The high-
speed switching logic uses VREF as the logic power supply. The 5-V reference tolerance is ±2% for the UCx84x
family. The output short-circuit current is 30 mA. For reference stability and to prevent noise problems with high-
speed switching transients, bypass VREF to ground with a ceramic capacitor close to the IC package. A
minimum of 0.1-µF ceramic capacitor is required. Additional VREF bypassing is required for external loads on the
reference. An electrolytic capacitor may also be used in addition to the ceramic capacitor.
When VCC is greater than 1 V and less than the UVLO threshold, a 5-kΩ resistor pulls VREF to ground. VREF
can be used as a logic output indicating power-system status because when VCC is lower than the UVLO
threshold, VREF is held low.

‫م‬
8.3.2 Pulse-by-Pulse Current Limiting ‫ﺗﺣدﯾد ﺗﯾﺎر اﻟﻣوﺳﻔت ﻧﺑﺿﺔ ﺑﻧﺑﺿﺔ‬

/
Pulse-by-pulse limiting is inherent in the current mode control scheme. An upper limit on the peak current can be
established by simply clamping the error voltage. Accurate current limiting allows optimization of magnetic and
power semiconductor elements while ensuring reliable supply operation.

‫اﺣ‬
8.3.3 Current-Sense ‫ﺗﺣﺳس ﺗﯾﺎر اﻟﻣوﺳﻔت‬
An external series resistor, RCS, senses the current and converts this current into a voltage that becomes the

‫ﻣد‬
input to the ISENSE pin. The ISENSE pin is the noninverting input to the PWM comparator. The ISENSE input is
compared to a signal proportional to the error amplifier output voltage; the gain of the current sense amplifier is
typically 3 V/V. The peak ISENSE current is determined by Equation 6:
VISENSE
ISENSE = ‫ﯾ‬ : ‫ﯾﺗم ﺗﺣدﯾد اﻗﺻﻰ ﺗﯾﺎر ﯾﻣر ﻓﻰ ﻣﻘﺎوﻣﺔ اﻟﺗﺣﺳس ﻣن اﻟﻌﻼﻗﺔ‬
R CS (6)
‫وﺳ‬
‫ ﻓوﻟت‬1 = ‫اﻟﻘﯾﻣﺔ اﻟﻣﺛﺎﻟﯾﺔ ﻟﺟﮭد ﻣدﺧل ﺗﺣﺳس اﻟﺗﯾﺎر‬

‫ ﻟﻣﻧﻊ اﻟﻧوﯾز واﺳﺗﻘرار ﺗﺷﻐﯾل اﻟﻣﻘﺎرن‬RC ‫ﯾﺗم وﺿﻊ ﻓﻠﺗر ﻣن ﻧوع ﻣﻘﺎوﻣﺔ وﻣﻛﺛف‬
‫ف‬

Error
Amplifier
2R
‫اﻟﻣ‬

COMP R 1V
ISENSE PWM
‫ﺻ‬

Comparator
RCSF
ISENSE
‫رى‬

RCS CCSF ‫اﻟﻘﯾﻣﺔ اﻟﻣﺛﺎﻟﯾﺔ ﻟﺟﮭد ﻣدﺧل‬

‫ﻓﻠﺗر‬ GROUND ‫ ﻓوﻟت‬1 = ‫اﻟﺗﺣﺳس‬

Copyright © 2016, Texas Instruments Incorporated

Figure 13. Current-Sense Circuit Schematic

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Feature Description (continued)

8.3.4 Error Amplifier With Low Output Resistance ‫ﻣواﺻﻔﺎت ﻣﻘﺎرن اﻟﺧطﺎ اﻟﻣﻧﺧﻔض ﻣﻘﺎوﻣﺔ اﻟﺧرج‬
The error amplifier output is an open collector in parallel with a current source. With a low output resistance,
various impedance networks may be used on the compensation pin input for error amplifier feedback. The error
amplifier output, COMP, is frequently used as a control port for secondary-side regulation by using an external
secondary-side adjustable voltage regulator, such as a TL431, to send an error signal across the secondary-to-
primary isolation boundary through an opto-isolator, in this configuration connect the COMP pin directly to the
opto-isolator feedback. On the primary side, the inverting input to the UCx48x error amplifier, VFB, should be
connected to GROUND. With VFB tied to GROUND, the error amplifier output, COMP, is forced to its high state
and sources current, typically 0.8 mA. The opto-isolator must overcome the source current capability to control
the COMP pin below the error amplifier output high level, VOH.

‫م‬
For primary-side regulation, configure the inverting input to the error amplifier, VFB, with a resistor divider to
provide a signal that is proportional to the converter output voltage being regulated. Add the voltage loop
compensation components between VFB and COMP. The internal noninverting input to the error amplifier is

/
trimmed to 2.5 V. For best stability, keep VFB lead length as short as possible and minimize the stray
capacitance on VFB.

‫اﺣ‬
The internal resistor divider on COMP is maintained at an R:2R ratio, the specific values of these internal
resistors should not be critical in any application.

‫ﻣد‬
‫ ﻓوﻟت‬2.5 ‫ﺟﮭد ﻣرﺟﻌﻰ‬ 1 : 2 ‫ﻧﺳﺑﺔ ﻣﻘﺎوﻣﺔ ﻣﺟزئ اﻟﺟﮭد‬
0.5 mA
‫ﺑواﺳطﺔ ﻣﺟزئ ﺟﮭد ﻋﻠﻰ‬
‫ ﻓوﻟت‬5 ‫اﻟﺗﻐذﯾﺔ‬ 2.5 V
+
‫ﯾ‬ 2R
‫وﺳ‬
Error
Amplifier
R 1V
‫ﻣدﺧل اﻟﻔﯾدﺑﺎك‬ PWM
ZI s Comparator
VFB
‫ف‬

ZF
COMP
‫اﻟﻣ‬

ISENSE

Error amplifier can source or sink up to 0.5 mA.

‫ﺻ‬

Figure 14. Error-Amplifier Configuration Schematic

8.3.5 Undervoltage Lockout ‫دواﺋر ﺗﺣﺳس اﻧﺧﻔﺎض ﺟﮭد اﻟﺗﺷﻐﯾل واﯾﺿﺎ اﻧﺧﻔﺎض ﺟﮭد اﻟﺗﻐذﯾﺔ اﻟﻣرﺟﻌﻰ‬
‫رى‬

The UCx84x devices feature undervoltage lockout protection circuits for controlled operation during power-up
and power-down sequences. The UVLO circuit insures that VCC is adequate to make the UCx84x fully
operational before enabling the output stage. Undervoltage lockout thresholds for the UCx842, UCx843, UCx844,
and UCx845 devices are optimized for two groups of applications: off-line power supplies and DC-DC converters.
The 6-V hysteresis in the UCx842 and UCx844 devices prevents VCC oscillations during power sequencing. This
wider VCCON to VCCOFF range, make these devices ideally suited to off-line AC input applications. The UCx843
and UCx845 controllers have a much narrower VCCON to VCCOFF hysteresis and may be used in DC to DC
applications where the input is considered regulated.
Start-up current is less than 1 mA for efficient bootstrapping from the rectified input of an off-line converter, as
illustrated by Figure 17. During normal circuit operation, VCC is developed from auxiliary winding NA with DBIAS
and CVCC. At start-up, however, CVCC must be charged to 16 V through RSTART. With a start-up current of 1 mA,
RSTART can be as large as 100 kΩ and still charge CVCC when VAC = 90 V RMS (low line). Power dissipation in
RSTART would then be less than 350 mW even under high line (VAC= 130 V RMS) conditions.

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Feature Description (continued)

During UVLO the IC draws less than 1 mA of supply current. Once crossing the turnon threshold the IC supply
current increases to a maximum of 17 mA, typically 11 mA, During undervoltage lockout, the output driver is
biased to a high impedance state and sinks minor amounts of current. A bleeder resistor, placed between the
gate and the source of the MOSFET should be used to prevent activating the power switch with extraneous
leakage currents during undervoltage lockout.

< 17 mA
VCC 7 ON/OFF Command
to rest of device

‫م‬
IVCC

/
UCx842 UCx843
UCx844 UCx845

‫اﺣ‬
< 1 mA
‫ﺟﮭد اﻟﺗﺷﻐﯾل‬ VON (V) 16 8.4
VOFF VON
‫ﺟﮭد اﻟﺗوﻗف‬ VOFF (V) 10 7.6 VVCC

‫ﻣد‬
‫ ﻣﻠﻠﻰ‬17 ‫ ﻣﻠﻠﻰ وﻋﻧد اﻟﺗﺷﻐﯾل ﯾﺻل اﻟﻰ‬1 ‫ﺗﯾﺎر اﻟﺑدء اﻛﺑر ﻣن‬

Copyright © 2016, Texas Instruments Incorporated

Figure 15. UVLO Threshold Figure 16. UVLO ON and OFF Profile
‫ﯾ‬
‫وﺳ‬
NP NS
RSTART
‫ف‬

DBIAS NA
IVCC • 1mA
VAC
CIN
VCC
‫اﻟﻣ‬

OUTPUT
CVCC 0.1 PF GROUND
‫ﺻ‬

RCS
‫رى‬

Figure 17. Providing Power to UCx84x

8.3.6 Oscillator ‫ﺗم ﺷرﺣﮫ ﺳﺎﺑﻘﺎ‬

The oscillator allows for up to 500-kHz switching frequency. The OUTPUT gate drive is the same frequency as
the oscillator in the UCx842 and UCx843 devices and can operate near 100% duty cycle. In the UCx844 and
UCx845 devices, the frequency of OUTPUT is one-half that of the oscillator due to an internal T flipflop that
blanks the output off every other clock cycle, resulting in a maximum duty cycle for these devices of < 50% of the
switching frequency. An external resistor, RRT, connected from VREF to RT/CT sets the charging current for the
timing capacitor, CCT, which is connected from RT/CT to GROUND. An RRT value greater than 5 kΩ is
recommended on RT/CT to set the positive ramp time of the internal oscillator. Using a value of 5 kΩ or greater
for RRT maintains a favorable ratio between the internal impedance and the external oscillator set resistor and
results in minimal change in frequency over temperature. Using a value of less the recommended minimum value
may result in frequency drift over temperature, part tolerances, or process variations.

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Feature Description (continued) ‫ ﻓوﻟت‬1.7 = ‫ﺟﮭد ﻣوﺟﺔ ﻣذﺑذب اﻻﯾﺳﻰ ﻣن اﻟﻘﻣﺔ اﻟﻰ اﻟﻘﻣﺔ‬

The peak-to-peak amplitude of the oscillator waveform is 1.7 V in UCx84x devices. The UCx842 and UCx843
have a maximum duty cycle of approximately 100%, whereas the UCx844 and UCx845 are clamped to 50%
maximum by an internal toggle flip flop. This duty cycle clamp is advantageous in most flyback and forward
converters. For optimum IC performance the dead-time should not exceed 15% of the oscillator clock period. The
discharge current, typically 6 mA at room temperature, sets the dead time, see Figure 9. During the discharge, or
dead time, the internal clock signal blanks the output to the low state. This limits the maximum duty cycle DMAX
to: ‫اﻟزﻣن اﻟﻣﯾت‬ ‫اﻟﺗردد‬ 43 ‫ و‬42 ‫اﻗﺻﻰ دﯾوﺗﻰ ﺳﯾﻛل ﻟﻠﻣودﯾل‬
D MAX= 1 F :t ×f ;
DEADTIME OSC (7)

‫م‬
fOSC
DMAX = 1 F lt DEADTIME × p 45 ‫ و‬44 ‫اﻗﺻﻰ دﯾوﺗﻰ ﺳﯾﻛل ﻟﻠﻣودﯾل‬
2 (8)

/
Equation 8 applies to UCx844 and UCx845 units because the OUTPUT switches at half the frequency as the
oscillator and the maximum duty cycle can be as high as 50%.

‫اﺣ‬
When the power transistor turns off, a noise spike is coupled to the oscillator RT/CT terminal. At high duty cycles,
the voltage at RT/CT is approaching its threshold level (approximately 2.7 V, established by the internal oscillator
circuit) when this spike occurs. A spike of sufficient amplitude prematurely trips the oscillator. To minimize the

‫ﻣد‬
noise spike, choose CCT as large as possible, remembering that dead time increases with CCT. It is
recommended that CCT never be less than approximately 1000 pF. Often the noise which causes this problem is
caused by the OUTPUT being pulled below ground at turnoff by external parasitics. This is particularly true when
driving MOSFETs. A Schottky diode clamp from GROUND to OUTPUT prevents such output noise from feeding
to the oscillator. ‫ﯾ‬
‫وﺳ‬
VREF
‫ف‬

RRT

RT/CT
CCT
‫اﻟﻣ‬

GROUND
1.72
fOSC =
RRT × CCT
‫ﺻ‬

Copyright © 2016, Texas Instruments Incorporated

‫رى‬

For RRT > 5 kΩ:

Figure 18. Oscillator Section Schematic

8.3.7 Synchronization ‫ﻋﻧد رﻓﻊ ﺟﮭد ﻣوﺟﺔ اﻟﻣذﺑذب ﻋن اﻟﺟﮭد اﻟداﺧﻠﻰ ﻟﻠﻣذﺑذب ﻟﺗﻐﯾﯾر ﺗردد اﻟﻣذﺑذب ﯾﺗم رﺑط اﺷﺎرة اﻟﺗزاﻣن ﻋﻠﻰ اﻟﻣدﺧل‬
‫ ﻣﻊ رﺑط ﻣﻘﺎوﻣﺔ ﺑﯾن اﻟﻣدﺧل واﻻرﺿﻰ‬19 ‫ ﻛﻣﺎ ﻓﻰ ﺷﻛل‬RT , CT
The simplest method to force synchronization uses the timing capacitor, CCT, in near standard configuration.
Rather than bring CCT to ground directly, a small resistor is placed in series with CCT to ground. This resistor
serves as the input for the sync pulse which raises the CCT voltage above the oscillator’s internal upper
threshold. The PWM is allowed to run at the frequency set by RRT and CCT until the sync pulse appears. This
scheme offers several advantages including having the local ramp available for slope compensation. The
UC3842/3/4/5 oscillator must be set to a lower frequency than the sync pulse stream, typically 20% with a 0.5-V
pulse applied across the resistor.

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Feature Description (continued)

VREF

RRT

RT/CT
CCT
SYNC
‫اﺷﺎرة اﻟﺗزاﻣن ﻟرﻓﻊ ﺟﮭد اﻟﻣذﺑذب‬

‫م‬
24 O

/
GROUND

‫اﺣ‬
Figure 19. Synchronizing the Oscillator

‫ﻣد‬
8.3.8 Shutdown Technique ‫ ﺗم ﺷرﺣﮭﺎ ﺳﺎﺑﻘﺎ‬- ‫اﻟﺗﺣﻛم ﻓﻰ وﻗف اﻻﯾﺳﻰ ﺧﺎرﺟﯾﺎ‬
The PWM controller (see Functional Block Diagrams) can be shut down by two methods: either raise the voltage
at ISENSE above 1 V or pull the COMP terminal below a voltage two diode drops above ground. Either method
‫ﯾ‬
causes the output of the PWM comparator to be high (see Functional Block Diagrams). The PWM latch is reset
‫وﺳ‬
dominant so that the output remains low until the next clock cycle after the shutdown condition at the COMP or
ISENSE terminal is removed. In one example, an externally latched shutdown can be accomplished by adding an
SCR that resets by cycling VCC below the lower UVLO threshold. At this point, the reference turns off, allowing
the SCR to reset.
‫ف‬

1 kO
VREF
COMP
SHUTDOWN
‫اﻟﻣ‬

30 O
ISENSE
500 O
SHUTDOWN
‫ﺻ‬

To Current
‫رى‬

Sense Resistor
Figure 20. Shutdown Techniques

8.3.9 Slope Compensation

A fraction of the oscillator ramp can be summed resistively with the current-sense signal to provide slope
compensation for converters requiring duty cycles over 50% (see Figure 21). Note that capacitor CCSF forms a
filter with RCSF to suppress the leading-edge switch spikes.

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UCx842
UCx843

VREF

0.1 µF RRT

RT/CT

‫م‬
CCT
RRAMP

/
RCSF ISENSE

‫اﺣ‬
ISENSE

CCSF RCS

‫ﻣد‬
Copyright © 2016, Texas Instruments Incorporated
‫ﯾ‬ Figure 21. Slope Compensation
‫وﺳ‬
8.3.10 Soft Start ‫اﻟﺑدء اﻟﻧﺎﻋم ﺑداﺋرة ﺧﺎرﺟﯾﺔ‬
Upon power up, it is desirable to gradually widen the PWM pulse width starting at zero duty cycle. The UCx84x
devices do not have internal soft-start control, but this can be easily implemented externally with three
‫ف‬

components. An R/C network is used to provide the time constant to control the error amplifier output. A
transistor is also used to isolate the components from the normal operation of either node. It also minimizes the
loading effects on the RT/CT time constant by amplification through the transistors gain.
‫اﻟﻣ‬

‫ﯾﺑدا اﻟﺗﺷﻐﯾل اﻟﻧﺎﻋم ﻣﻊ ﺷﺣن اﻟﻣﻛﺛف ﺣﯾث‬ VREF

‫ﯾﻛون اﻟﺗراﻧزﺳﺗور ﺷﻐﺎل وﯾﺗوﻗف ﺑﺎﻛﺗﻣﺎل‬
‫اﻟﺷﺣن وﺗوﻗف اﻟﺗراﻧزﺳﺗور‬
‫ﺻ‬

RSS
‫وھﻧﺎ ﺟﮭد اﻟﻣدﺧل ﻣرﺑوط ﻋﻠﻰ ﺧرج ﻣﻛﺑر اﻟﺧطﺄ‬ COMP
‫اﻟذى ﺑدوره ﻣرﺑوط ﻋﻠﻰ ﻣدﺧل ﻣﻘﺎرن ﺗﺣﺳس‬
‫اﻟﺗﯾﺎر ﺣﯾث ﯾﺗﺣﻛم ﻓﻰ ﻋرض اﻻﺗﺳﺎع ﻟﻣوﺟﺔ ﺗﺷﻐﯾل‬
‫رى‬

‫اﻟﻣوﺳﻔت‬
CSS

Figure 22. Soft-Start Circuitry

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‫ﺗﻐﯾﯾر ﻧظﺎم اﻟﻌﻣل ﻟﻼﯾﺳﻰ ﻣن اﻟﺗﺣﻛم ﺑﺎﻟﺗﯾﺎر اﻟﻰ اﻟﺗﺣﻛم ﺑﺎﻟﺟﮭد ﺑداﺋرة ﺧﺎرﺟﯾﺔ‬
8.3.11 Voltage Mode
In duty cycle control (voltage mode), pulse width modulation is attained by comparing the error amplifier output to
an artificial ramp. The oscillator timing capacitor CCT is used to generate a sawtooth waveform on both current or
voltage mode ICs. To use the UCx84x in a voltage mode configuration, this sawtooth waveform will be input to
the current sense input, ISENSE, for comparison to the error voltage at the PWM comparator. This sawtooth is
used to determine pulse width instead of the actual primary current in this method. Loop compensation is similar
to that of voltage mode controllers with subtle differences due to the low output resistance voltage amplifier in the
UCx84x as opposed to a transconductance (current) type amplifier used in traditional voltage mode controllers.
For further reference on topologies and compensation, consult Closing the Feedback Loop (SLUP068).

‫م‬
VREF

/
1N4148

‫اﺣ‬
‫ﻣد‬
2N2907
RT/CT
‫ﯾ‬
2N2222
‫وﺳ‬
2.7 k

ISENSE
‫ف‬

1k
CCT
‫اﻟﻣ‬

Figure 23. Current Mode PWM Used as a Voltage Mode PWM

‫ﺻ‬

8.4 Device Functional Modes

8.4.1 Normal Operation
‫رى‬

During normal operating mode, the IC can be used in peak current mode or voltage mode control. When the
converter is operating in peak current mode, the controller regulates the converter's peak current and duty cycle.
When the IC is used in voltage mode control, the controller regulates the power converter's duty cycle. The
regulation of the system's peak current and duty cycle can be achieved with the use of the integrated error
amplifier and external feedback circuitry.

8.4.2 UVLO Mode

During the system start-up, VCC voltage starts to rise from 0 V. Before the VCC voltage reaches its
corresponding turn on threshold, the IC is operating in UVLO mode. In this mode, the VREF pin voltage is not
generated. When VCC is above 1 V and below the turnon threshold, the VREF pin is actively pulled low through
a 5-kΩ resistor. This way, VREF can be used as a logic signal to indicate UVLO mode. If the bias voltage to VCC
drops below the UVLO-off threshold, PWM switching stops and VREF returns to 0 V. The device can be
restarted by applying a voltage greater than the UVLO-on threshold to the VCC pin.

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information ‫ﻣﻌﻠوﻣﺎت اﻟﺗطﺑﯾق‬

The UCx84x controllers are peak current mode pulse width modulators. These controllers have an onboard
amplifier and can be used in isolated and non-isolated power supply design. There is an onboard totem pole gate

‫م‬
driver capable of delivering 1 A of peak current. This is a high-speed PWM capable of operating at switching
frequencies up to 500 kHz.

/
9.1.1 Open-Loop Test Fixture ‫داﺋرة ﻓﺣص ﺧط ﻣﻔﺗوح‬
The following application is an open-loop laboratory test fixture. This circuit demonstrates the setup and use of

‫اﺣ‬
the UCx84x devices and their internal circuitry.
In the open-loop laboratory test fixture (see Figure 24), high peak currents associated with loads necessitate
careful grounding techniques. Timing and bypass capacitors should be connected close to the GROUND terminal

‫ﻣد‬
in a single-point ground. The transistor and 5-kΩ potentiometer sample the oscillator waveform and apply an
adjustable ramp to the ISENSE terminal.
VREF
‫ﯾ‬
R1
‫وﺳ‬
4.7 NŸ
UCx842
100 NŸ
1 COMP VREF 8
‫ف‬

VCC
1 NŸ
2 VFB VCC 7
E/A 1 NŸ
5 NŸ
Adjust 0.1 PF
‫اﻟﻣ‬

3 ISENSE OUTPUT 6 OUTPUT

ISENSE
0.1 PF
Adjust
‫ﺻ‬

4.7 NŸ 4 RT/CT GROUND 5

CRTCT GROUND
‫رى‬

Copyright © 2016, Texas Instruments Incorporated

Figure 24. Open-Loop Laboratory Test Fixture

9.2 Typical Application

A typical application for the UC2842 in an off-line flyback converter is shown in Figure 25. The UC2842 uses an
inner current control loop that contains a small current sense resistor which senses the primary inductor current
ramp. This current sense resistor transforms the inductor current waveform to a voltage signal that is input
directly into the primary side PWM comparator. This inner loop determines the response to input voltage
changes. An outer voltage control loop involves comparing a portion of the output voltage to a reference voltage

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Typical Application (continued)

‫داﺋرة ﺑﺎور اﻧﺗظﺎر ﻋﻣﻠﯾﺔ ﺣﯾث ﺗم رﺑط ﻣﺟﻣﻊ ﺗراﻧزﺳﺗور اﻟﻔوﺗوﻛﺎﺑﻠر اﻟﻰ ﻣدﺧل اﻟﺟﮭد اﻟﻣرﺟﻌﻰ وﺗم رﺑط اﻟﻣﺷﻊ اﻟﻰ ﻣدﺧل اﻟﻔﯾدﺑﺎك‬

‫ داﺋرة اﻟﺳﻧوﺑر‬DCLAMP
~
VIN = 85 VAC
CSNUB RSNUB
to 265 VAC DOUT
10 nF 50 k
± DBRIDGE +
CIN NS VOUT
RSTART NP
CSS 180 µF RVCC COUT 12 V,
100 k

‫م‬
~ 2200 µF
DBIAS 22 4A

CVCC
‫ﻣﻠف اﻟﺗﺷﻐﯾل‬ NA
RSS LP =1.5 mH
120 µF

/
NP:NS = 10
NP:NA = 10
UC2842

‫اﺣ‬
RCOMPp CCOMPp 1 COMP VREF 8
10 k 10 nF
2 VFB VCC 7
RG
10 ‫اﻟﻣوﺳﻔت‬
RRT 3 ISENSE OUTPUT 6

‫ﻣد‬
15.4 k QSW
4 RT/CT GROUND 5
CVCCbp CVREF RBLEEDER RCS
CCT 0.1 µF 1 µF 10 k 0.75 RLED RTLbias
CRAMP 1000 pF 1.3 k 1k
RCSF
10 nF ‫ﯾ‬
4.2 k
‫وﺳ‬
RRAMP
24.9 k OPTO- 10 V
COUPLER RFBU
RP 9.53 k
CCSF Not Populated
100 pF RFBG
4.99 k RCOMPz CCOMPz
88.7 k 0.01 µF
‫ف‬

ROPTO ‫اﻟﻔوﺗوﻛﺎﺑﻠر‬
1k
‫ ﻣﻧظم اﻟﺟﮭد‬TL431 RFBB
2.49 k
‫اﻟﻣ‬

Copyright © 2016, Texas Instruments Incorporated

Figure 25. Typical Application Design Example Schematic

‫ﺻ‬

9.2.1 Design Requirements

CCM ‫ ﻓوﻟت وﻣدﺧل ﺟﮭد اﻟﺧط ﯾوﻧﯾﻔرﺳﺎل ﺣﯾث ﯾﺷﺗﻐل اﻟﺑﺎور ﺑﻧظﺎم اﻟﻣﺗﺻل‬12 ‫ وات ﺧرج‬48 ‫ﻟﺗﺻﻣﯾم ﺑﺎور‬
‫رى‬

‫ﻣواﺻﻔﺎت اﻟﺑﺎور‬ Table 1. Performance Requirements

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
VIN Input Voltage ‫ﺟﮭد اﻟدﺧل‬ 85 115/230 265 VRMS
fLINE Line Frequency ‫ﺗردد اﻟﺧط‬ 47 50/60 63 Hz
VOUT Output Voltage IOUT(min) ≤ IOUT ≤ IOUT(max) ‫ﺟﮭد اﻟﺧرج‬ 11.75 12 12.25 V

VRIPPLE
Output Ripple ‫ﻟﻠﺧرج‬
IOUT(min) ≤ IOUT ≤ IOUT(max) ‫اﻟرﯾﺑل‬ ‫ﺟﮭد‬ 100 mVpp
Voltage
IOUT Output Current ‫ﺗﯾﺎر اﻟﺧرج‬ 0 4 A
Switching
fSW
Frequency ‫ﺗردد اﻟﺗﻘطﯾﻊ ﻟﻼﯾﺳﻰ‬ 100 kHz

η Efficiency ‫ﻛﻔﺎﺋﺔ اﻟﺑﺎور‬ 85%

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‫‪9.2.2 Detailed Design Procedure‬‬

‫‪9.2.2.1 Input Bulk Capacitor and Minimum Bulk Voltage‬‬ ‫ﺗﻌﯾﯾن ﻗﯾﻣﺔ ﻣﻛﺛف اﻟﺗﻧﻌﯾم اﻟرﺋﯾﺳﻰ ﻟﻠﺧط‬

‫ھﻧﺎ اﺳﺗﺧدم اﻟﻣﺻﻣم ﻣﻌﺎدﻻت رﯾﺎﺿﯾﺔ ﻟﺗﻌﯾﯾن ﺳﻌﺔ ﻣﻛﺛف اﻟدﺧل ﺑدﻻ ﻣن اﺳﺗﺧدام اﻟطرﯾﻘﺔ اﻟﺗﻘﻠﯾدﯾﺔ ﻟﻌﻼﻗﺔ ﺳﻌﺔ اﻟﻣﻛﺛف ﻣﻊ ﻗدرة اﻟدﺧل ‪ 2‬ﻣﯾﻛرو ﻟﻛل ‪1‬‬
‫وات ﻟﻧظﺎم اﻟﯾوﻧﯾﻔرﺳﺎل وﻟو اﺗﺑﻌﻧﺎ اﻟﻘﺎﻧون ﺳﻧﺟد ان اﻟﻣﻛﺛف = ‪ 100‬ﻣﯾﻛرو ﻋﻠﻰ اﺳﺎس ﻗدرة اﻟدﺧل ‪ 50‬وات‬

‫اﻣﺎ ﺑﺣﺳﺎب اﻟﻣﻌﺎدﻟﺔ اﻟﺳﻔﻠﯾﺔ ﺳﻧﺟد ان ﺳﻌﺔ اﻟﻣﻛﺛف ‪ 126‬ﻣﯾﻛرو واﺧﺗﺎر ھو ‪ 180‬ﻣﯾﻛرو‬

‫م‬
‫ﻗدرة اﻟدﺧل‬

‫‪2 × PIN × F0.25 +‬‬ ‫‪× arcsin F‬‬ ‫‪GG‬‬

‫‪1‬‬ ‫) ‪VBULK (min‬‬

‫‪/‬‬
‫‪N‬‬ ‫) ‪¾2 × VIN (min‬‬
‫= ‪ CIN‬ﺳﻌﺔ اﻟﻣﻛﺛف‬
‫‪k2 × VIN‬‬
‫‪2‬‬
‫) ‪(min ) F VBULK (min ) o × fLINE (min‬‬
‫‪2‬‬

‫اﺣ‬
‫اﻗل ﺗردد ﻟﻠﺧط‬
‫اﻗل ﺟﮭد دﺧل ‪ 85‬ﻓوﻟت‬ ‫اﻗل ﺟﮭد ﻟﻠﻣﻛﺛف‬
‫)‪(9‬‬

‫ﻣد‬
‫‪9.2.2.2 Transformer Turns Ratio and Maximum Duty Cycle‬‬
‫ﺗﻌﯾﯾن ﻧﺳﺑﺔ ﻋدد اﻟﻠﻔﺎت واﻗﺻﻰ دﯾوﺗﻰ ﺳﯾﻛل‬

‫ﻋﻣﻠﯾﺔ اﺧﺗﯾﺎر ﻗﯾﻣﺔ اﻟﺗردد ﻋﻠﯾﮭﺎ ﻋﺎﻣل ﻛﺑﯾر ﻓﻰ ﺗﺣدﯾد ﺣﺟم اﻟﻣﺣول وﻋدد اﻟﻠﻔﺎت واﯾﺿﺎ ﺗﺗوﻗف ﻋﻠﯾﮭﺎ ﻗﯾﻣﺔ اﻟﻣﻔﺎﻗﯾد‬
‫ﯾ‬
‫اﻣﺎ اﺧﺗﯾﺎر ﻧﺳﺑﺔ اﻟﻠﻔﺎت ﻓﯾﺗم ﺣﺳب ﺟﮭد اﻟﻣوﺳﻔت اﻟﻣﺳﺗﺧدم ﺣﯾث ﺗﺣدد ھﻰ اﻟﺟﮭد اﻟﻣرﺗد ﻋﻠﻰ اﻟﻣوﺳﻔت وﺑﺎﻟﺗﺎﻟﻰ اﻗﺻﻰ ﺟﮭد ﯾﺗﺣﻣﻠﮫ اﻟﻣوﺳﻔت‬
‫وﺳ‬
‫ﻣرﺗﺑط ﺑﮭﺎ وﻛذﻟك ﺗﺣدد اﻟﺟﮭد اﻟﻌﻛﺳﻰ ﻟداﯾود اﻟﺧرج‬

‫ﯾﺗم ﺗﺣدﯾد ﻧﺳﺑﺔ ﻋدد اﻟﻠﻔﺎت ﻣن ﺧﻼل اﻟﻌﻼﻗﺔ ﺑﯾن ﺟﮭد اﻟﺧرج واﻟﺟﮭد اﻟﻣرﺗد ﻋﻠﻰ اﻻﺑﺗداﺋﻰ اﺛﻧﺎء ﺗوﻗف اﻟﻣوﺳﻔت‪:‬‬
‫ﻋدد ﻟﻔﺎت اﻻﺑﺗداﺋﻰ‬
‫ف‬

‫اﻟﺟﮭد اﻟﻣرﺗد ﻋﻠﻰ اﻻﺑﺗداﺋﻰ‬

‫=‬ ‫ﻧﺳﺑﺔ ﻋدد اﻟﻠﻔﺎت =‬
‫ﺟﮭد اﻟﺛﺎﻧوى )اﻟﺧرج(‬ ‫ﻋدد ﻟﻔﺎت اﻟﺛﺎﻧوى‬

‫ﺟﮭد اﻟﺛﺎﻧوى = ‪ 12‬ﻓوﻟت ‪.........‬ﯾﺑﻘﻰ ﻋﻧدﻧﺎ ﻣﺟﮭول ھو ﺣﺳﺎب ﻗﯾﻣﺔ اﻟﺟﮭد اﻟﻣرﺗد ﺑﺎﻟﺧطوات اﻟﺗﺎﻟﯾﺔ‬
‫اﻟﻣ‬

‫اﻟﺟﮭد اﻟﻛﻠﻰ اﻟواﻗﻊ ﻋﻠﻰ اﻟﻣوﺳﻔت اﺛﻧﺎء اﻟﺗوﻗف = اﻗﺻﻰ ﺟﮭد دﺧل ‪ +‬ﺟﮭد اﻟﺷﺎرز ‪ +‬اﻟﺟﮭد اﻟﻣرﺗد‬
‫ﺻ‬

‫ﺳﻧﻘوم ﺑﺗﻌﯾﯾن اﻗﺻﻰ ﺟﮭد ﻣﺳﺗﻣر ﻋﻠﻰ ﻣﻛﺛف اﻟدﺧل اﻟرﺋﯾﺳﻰ اوﻻ ﻋﻠﻰ اﺳﺎس ان اﻗﺻﻰ ﺟﮭد ﻣﺗردد ھو ‪ 265‬ﻓوﻟت وﺑﺿرﺑﮫ ﻓﻰ ﺟذر ‪ 2‬ﻧﺣﺻل ﻋﻠﻰ‬
‫اﻗﺻﻰ ﺟﮭد ﻣﺳﺗﻣر ﺳوف ﯾؤﺛر ﻋﻠﻰ اﻟﻣﻛﺛف = ‪ 375‬ﻓوﻟت‬

‫اﻗﺻﻰ ﺟﮭد ﻣﺳﺗﻣر ﻟﻠدﺧل‬ ‫‪VBULK (max ) = ¾2 × VIN (max ) N 375 V‬‬
‫رى‬

‫)‪(10‬‬

‫ﻟﻠﺗوﻓﯾر ﻓﻰ ﺳﻌر اﻟﺑﺎور ﺳﯾﺗم اﺧﺗﯾﺎر ﻣوﺳﻔت ‪ 650‬ﻓوﻟت اوﻻ وﻣن ﺛم ﺳﯾﺗم ﺑﻧﺎء ﻋﻠﻰ ھذا اﻻﺧﺗﯾﺎر ﺗﺣدﯾد ﺑﺎﻗﻰ اﻟﻌﻧﺎﺻر اﻟﻣﺗرﺗﺑﺔ ﻋﻠﻰ ھذا اﻻﺧﺗﯾﺎر‬

‫ﺳﯾﺗم اﻋﺗﺑﺎر ﺟﮭد اﻟﺷﺎرز ﻟﻠﻣﺣﺎﺛﺔ اﻟﺷﺎردة = ‪ %30‬ﻣن اﻗﺻﻰ ﺟﮭد ﻣﺳﺗﻣر ﻋﻠﻰ ﻣﻛﺛف اﻟدﺧل= ‪ 112 = 30/100 * 375‬ﻓوﻟت‬

‫ﺑﺎﻟﺗﻌوﯾض ﻟﺣﺳﺎب اﻟﺟﮭد اﻟﻣرﺗد = اﻟﺟﮭد اﻟﻛﻠﻰ ﻋﻠﻰ اﻟﻣوﺳﻔت ‪ -‬اﻗﺻﻰ ﺟﮭد دﺧل ‪ -‬ﺟﮭد اﻟﺷﺎرز‬

‫= ‪ 163 = 112- 375 - 650‬ﻓوﻟت وﻟﻼﻣﺎن ﺳﻧﺣﺳب ﻓﻘط ‪ 0.8‬ﻣن ﺗﻠك اﻟﻘﯾﻣﺔ = ‪ 130‬ﻓوﻟت‬
 ‫ﻧﺳﺑﺔ اﻟﻠﻔﺎت = اﻟﺟﮭد اﻟﻣرﺗد ‪ /‬ﺟﮭد اﻟﺧرج = ‪10.85 = 12/ 130‬‬

‫ﺳﻧﺎﺧذ اﻟﻘﯾﻣﺔ اﻟﺻﺣﯾﺣﺔ اﻻﻗل = ‪10‬‬

‫‪ -‬اﺧﺗﯾﺎر ﻧﺳﺑﺔ ﻋدد اﻟﻠﻔﺎت ﺑﯾن ﻣﻠﻔﺎت اﻟﺑﺎﺗداﺋﻰ وﻣﻠﻔﺎت اﻟﺗﺷﻐﯾل ‪:‬‬

‫ﯾﺗم اﺧﺗﯾﺎر ﻋدد ﻟﻔﺎت اﻟﺗﺷﻐﯾل ﺑﺣﯾث ﯾﻛون ﺟﮭد اﻟﺗﺷﻐﯾل اﻋﻠﻰ ﻗﻠﯾﻼ ﻣن اﻗل ﺟﮭد ﻻزم ﻟﺗﺷﻐﯾل اﻻﯾﺳﻰ‬

‫ﺑﺎﻟﻧﺳﺑﺔ ﻟﻼﯾﺳﻰ ‪ 2842‬ﻓﺎن اﻗل ﺟﮭد ﺗﺷﻐﯾل ھو ‪ 10‬ﻓوﻟت ﻟذﻟك ﺳﯾﻧم اﺧﺗﯾﺎر ﺟﮭد اﻟﺗﺷﻐﯾل ﻟﻠﻔﺎت =‪ 12‬ﻓوﻟت‬

‫ﺟﮭد اﻟﺧرج‬ ‫اﻟﺟﮭد اﻟﻣرﺗد‬ ‫ﻋدد ﻟﻔﺎت اﻻﺑﺗداﺋﻰ‬

‫م‬
‫‪ X‬ﻧﺳﺑﺔ ﻟﻔﺎت اﻟﻣﺣول‬ ‫=‬ ‫=‬ ‫ﻧﺳﺑﺔ اﻟﻠﻔﺎت ﻟﻠﺗﺷﻐﯾل =‬
‫ﺟﮭد اﻟﺗﺷﻐﯾل‬ ‫ﺟﮭد اﻟﺗﺷﻐﯾل‬ ‫ﻋدد ﻟﻔﺎت اﻟﺗﺷﻐﯾل‬

‫‪/‬‬
‫‪12‬‬
‫‪10 = 10‬‬ ‫‪X‬‬ ‫=‬

‫اﺣ‬
‫‪12‬‬

‫ﻣد‬
‫ﺣﺳﺎب ﺟﮭد اﻟداﯾود اﻟﻌﻛﺳﻰ اﺛﻧﺎء ﺗﺷﻐﯾل اﻟﻣوﺳﻔت ‪:‬‬
‫ﯾ‬
‫وﺳ‬
‫اﻟﺟﮭد اﻟﻌﻛﺳﻰ اﻟواﻗﻊ ﻋﻠﻰ اﻟداﯾود اﺛﻧﺎء ﺗﺷﻐﯾل اﻟﻣوﺳﻔت = ﺟﮭد اﻟﺧرج ‪ +‬اﻗﺻﻰ ﺟﮭد ﻣرﺗد ﻣن اﻻﺑﺗداﺋﻰ‬
‫ف‬

‫‪ / 375‬ﻧﺳﺑﺔ اﻟﻠﻔﺎت = ‪ 49.5‬ﻓوﻟت‬ ‫= ‪+ 12‬‬

‫اﻟﻣ‬

‫ﻟﻼﻣﺎن ﺳﯾﺗم اﺧﺗﯾﺎر ﺷوﺗﻛﻰ داﯾود ‪ 60‬ﻓوﻟت وﺑﺟﮭد اﻣﺎﻣﻰ ‪ 0.6‬ﻓوﻟت‬

‫ﺻ‬
‫رى‬

‫ﻟﺗﺟﻧب اﻗﺻﻰ ﺗﯾﺎر ﻟﻠﻣوﺳﻔت ﻋﺎﻟﻰ ﺗم اﺧﺗﯾﺎر ﻧظﺎم اﻟﺗﺷﻐﯾل ﻟﻠﻛوﻧﻔرﺗر ﺑﺎﻟﻧظﺎم اﻟﻣﺳﺗﻣر ‪CCM‬‬

‫وﻋﻠﯾﮫ ﺳﯾﺗم ﺗﻌﯾﯾن اﻗﺻﻰ دﯾوﺗﻰ ﺳﯾﻛل ﻟﻠﻧظﺎم ‪ CCM‬ﻣن اﻟﻌﻼﻗﺔ اﻟﻣﻌروﻓﺔ ‪:‬‬

‫ﺟﮭد اﻟداﯾود‬
‫اﻗﺻﻰ دﯾوﺗﻰ ﺳﯾﻛل‬
‫ﺟﮭد اﻟﺧرج‬

‫اﻗل ﺟﮭد دﺧل ﻣﺳﺗﻣر‬

‫ﻧﺳﺑﺔ اﻟﻠﻔﺎت‬

‫اﻗﺻﻰ دﯾوﺗﻰ ﺳﯾﻛل‬

‫ﻣن ھﻧﺎ ﻧﺟد ان اﻟدﯾوﺗﻰ ﺳﯾﻛل ﺗزﯾد ﻋن ‪ 50‬ﻓﻰ اﻟﻣﯾﺔ ﻟذﻟك ﻓﺎن اﻓﺿل اﺧﺗﯾﺎر ھو اﻻﯾﺳﻰ ‪UC2842‬‬
 ‫‪UC1842, UC2842, UC3842, UC1843, UC2843, UC3843‬‬
‫‪UC1844, UC2844, UC3844, UC1845, UC2845, UC3845‬‬
‫‪SLUS223E – APRIL 1997 – REVISED JANUARY 2017‬‬ ‫‪www.ti.com‬‬

‫‪9.2.2.3 Transformer Inductance and Peak Currents‬‬ ‫‪ -‬ﺗﻌﯾﯾن ﻗﯾﻣﺔ ﻣﺣﺎﺛﺔ اﻻﺑﺗداﺋﻰ واﻗﺻﻰ ﺗﯾﺎر ‪:‬‬
‫وﻻﻧﻧﺎ ﻧﻌﻣل ﺑﻧظﺎم ‪ CCM‬ﺳﯾﺗم اﺧﺗﯾﺎر ﻗﯾﻣﺔ ﻣﺣﺎﺛﺔ اﻻﺑﺗداﺋﻰ اﻟﺗﻰ ﺗﺳﺗطﯾﻊ اﻟﺑﻘﺎء ﻓﻰ اﻟﺗﺷﻐﯾل ﺗﺣت اﻟﻧظﺎم اﻟﻣﺳﺗﻣر دون اﻟدﺧول ﻓﻰ اﻟﻧظﺎم‬
‫اﻟﻣﻧﻔﺻل ‪DCM‬وذﻟك ﺗﺣت ﺗﺷﻐﯾل ﻟﻧﺳب ﻣﺗﻔﺎوﺗﺔ ﻣن ﺟﮭد اﻟدﺧل اﻟﻌﺎﻟﯾﺔ اﻻﺧﺗﻼف‬
‫واﻟﻣﯾزة ﻓﻰ ﻧظﺎم ‪ CCM‬ﻛﻣﺎ ذﻛرﻧﺎ ﺳﺎﺑﻘﺎ ھو ﺗﻘﻠﯾل اﻟﺗﯾﺎرات وﺗﻘﻠﯾل اﻟﻣﻔﺎﻗﯾد واﯾﺿﺎ ﺗﻘﻠﯾل اﻟرﯾﺑل ﻋﻠﻰ اﻟﺧرج‬

‫ﺳﯾﺗم اﺧﺗﯾﺎر اﻟﻣﺣﺎﺛﺔ اﯾﺿﺎ ﻋﻠﻰ اﺳﺎس ان اﻟﻛوﻧﻔرﺗر ﺳﯾﻛون داﺧل ‪ CCM‬ﺣﺗﻰ ﻟو ﻗل اﻟﺣﻣل اﻟﻰ ﻧﺳﺑﺔ ‪ %10‬وﻋﻠﻰ اﺳﺎس اﻗل‬
‫ﻗﯾﻣﺔ ﻟﺟﮭد اﻟدﺧل اﻟﻣﺳﺗﻣر ﻋﻠﻰ اﻟﻣﻛﺛف‬

‫‪/‬‬ ‫م‬
‫ﻣرﺑﻊ اﻗل ﺟﮭد دﺧل ﻣﺳﺗﻣر‬ ‫ﻧﺳﺑﺔ اﻟﻠﻔﺎت‬ ‫ﺟﮭد اﻟﺧرج‬

‫اﺣ‬
‫)‪(17‬‬
‫ﻣﺣﺎﺛﺔ اﻻﺑﺗداﺋﻰ‬
‫ﺗردد اﻟﺗﻘطﯾﻊ‬

‫ﻣد‬
‫ﻗدرة اﻟدﺧل‬

‫ﯾ‬ ‫ﻓﻰ اﻟﻣﻌﺎدﻟﺔ اﻟﺳﺎﺑﻘﺔ ﯾﺗم اﯾﺟﺎد ﻗدرة اﻟدﺧل ﻣن ﻣﻌﺎدﻟﺔ ﻗدرة اﻟﺧرج وﻣﻌﺎﻣل اﻟﻛﻔﺎﺋﺔ‬
‫وﺳ‬
‫‪ -‬اﯾﺿﺎ ﯾﺗم ﺣﺳﺎب ﺗردد اﻟﺗﻘطﯾﻊ ﻋﻠﻰ اﺳﺎس = ‪ 110‬ﻛﯾﻠو ھﯾرﺗز‬
‫‪ -‬ﺑﻌد ادﺧﺎل ﺗﻠك اﻟﻘﯾم واﺟراء اﻟﺣﺳﺎﺑت ﺳﯾﻧﺗﺞ ‪ :‬ﻣﺣﺎﺛﺔ اﻻﺑﺗداﺋﻰ = ‪ 1.8‬ﻣﻠﻠﻰ ھﻧرى وﺳﯾﺗم اﻋﺗﺑﺎرھﺎ ‪ 1.5‬ﻣﻠﻠﻰ ھﻧرى‬
‫ف‬

‫‪ -‬ﺣﺳﺎب ﻗﯾﻣﺔ اﻗﺻﻰ ﺗﯾﺎر اﺑﺗداﺋﻰ ﻣن اﻟﻌﻼﻗﺔ اﻟﺗﺎﻟﯾﺔ ‪:‬‬

‫اﻟﻣ‬

‫‪NPS × VOUT‬‬
‫‪+n‬‬ ‫‪r‬‬
‫‪PIN‬‬ ‫; ‪VBULK (min ) VBULK :min ; + :NPS × VOUT‬‬
‫= ‪IPK MOSFET‬‬ ‫×‬
‫‪NPS × VOUT‬‬
‫ﺻ‬

‫× ; ‪VBULK :min‬‬ ‫‪2 × Lm‬‬ ‫‪fSW‬‬

‫; ‪VBULK :min ; + :NPS × VOUT‬‬

‫ﺑﺎﻟﺗﻌوﯾض ﻋن اﻟﻘﯾم ﻓﻰ ﺗﻠك اﻟﻣﻌﺎدﻟﺔ ﺳﯾﻧﺗﺞ اﻗﺻﻰ ﺗﯾﺎر اﺑﺗداﺋﻰ = ‪ 1.36‬اﻣﺑﯾر ‪ ----‬وﻗﯾﻣﺔ ‪) RMS‬ﻗراءة اﻻﻣﯾﺗر ( = ‪ 0.97‬اﻣﺑﯾر ﻣن‬
‫رى‬

‫اﻟﻣﻌﺎدﻟﺔ ‪19‬‬

‫¨ = ‪ IRM S MOSFET‬ﻗراءة اﻻﻣﯾﺗر ﻟﻠﺗﯾﺎر‬ ‫‪×l‬‬ ‫‪p FF‬‬ ‫‪G + kDMAX × IPK MOSFET 2 o‬‬
‫‪DMAX 3‬‬ ‫‪VBULK (min ) 2‬‬ ‫) ‪DMAX 2 × IPK MOSFET × VBULK (min‬‬ ‫‪= 0.97A‬‬
‫‪3‬‬ ‫‪LP × fSW‬‬ ‫‪LP × fSW‬‬
‫)‪(19‬‬

‫ﻟذﻟك ﺳﯾﺗم اﺧﺗﯾﺎر اﻟﻣوﺳﻔت ‪ IRFB9N65A‬ﺑﻧﺎء ﻋﻠﻰ اﻟداﺗﺎﺷﯾت ﻟﮫ ﻣن ﺣﯾث اﻗﺻﻰ ﺟﮭد واﻗﺻﻰ ﺗﯾﺎر ﻟﯾﻛون ﻣﻧﺎﺳب ﻟﮭذا اﻟﺑﺎور‬

‫ﺳﯾﺗم ﺣﺳﺎب اﻗﺻﻰ ﺗﯾﺎر ﻟداﯾود اﻟﺧرج ﺑﺿرب اﻗﺻﻰ ﺗﯾﺎر ﻟﻠﻣوﺳﻔت ﻓﻰ ﻧﺳﺑﺔ اﻟﻠﻔﺎت‬

‫‪ I PK DIODE = NPS × IPK MOSFET = 13.634 A‬ﺗﯾﺎر اﻟداﯾود‬ ‫)‪(20‬‬

‫ﺑﻧﺎء ﻋﻠﻰ اﻟﺑﯾﺎﻧﺎت ﻟﺗﯾﺎر اﻟﺧرج ‪ 4‬اﻣﺑﯾر واﻗﺻﻰ ﺗﯾﺎر ‪ 13.634‬وﺟﮭد ﻋﻛﺳﻰ ‪ 60‬ﻓوﻟت ﺳﯾﺗم اﺧﺗﯾﺎر اﻟداﯾود ‪48CTQ060-1‬‬
 ‫ﺣﺳﺎب ﻗﯾﻣﺔ ﻣﻛﺛف اﻟﺧرج‬
‫‪9.2.2.4 Output Capacitor‬‬

‫ﯾﺗم اﺧﺗﯾﺎر ﺳﻌﺔ ﻣﻛﺛف اﻟﺧرج ﺑﻧﺎء ﻋﻠﻰ ﺟﮭود اﻟرﯾﺑل ﻋﻠﻰ اﻟﺧرج وﻓﻰ ھذا اﻟﺗﺻﻣﯾم ﺳﯾﺗم اﻋﺗﺑﺎر ﺟﮭد اﻟرﯾﺑل = ‪%0.1‬ﻣن ﺟﮭد اﻟﺧرج‬

‫وﺳﻌﺔ اﻟﻣﻛﺛف ﯾﺗم ﺣﺳﺎﺑﮭﺎ ﻣن اﻟﻌﻼﻗﺔ ‪:‬‬

‫‪NPS × VOUT‬‬
‫× ‪IOUT‬‬
‫‪COUT R‬‬
‫‪VBULK :min ; + NPS × VOUT‬‬
‫‪= 1865 JF‬‬ ‫)‪(21‬‬ ‫ﻛل ﻋﻧﺎﺻر اﻟﻣﻌﺎدﻟﺔ ﻣﻌروﻓﺔ‬
‫‪0.001 × VOUT × fSW‬‬
‫ﺳﯾﺗم اﺧﺗﯾﺎر ﻣﻛﺛف ‪ 2200‬ﻣﯾﻛرو ﻓﺎراد ﻟﮭذا اﻟﺗﺻﻣﯾم‬

‫‪9.2.2.5 Current Sensing Network‬‬ ‫اﺧﺗﯾﺎر ﻋﻧﺎﺻر داﺋرة ﺗﺣﺳس ﺗﯾﺎر اﻟﻣوﺳﻔت‬

‫م‬
‫‪ -‬ﺳﯾﺗم اﺧﺗﯾﺎر ﻓﻠﺗر ﻣن اﻟﻧوع اﻟﻣﻧﺧﻔض ﻻزاﻟﺔ اى ﺷﺎرز او ارﺗﻔﺎع ﻣﻔﺎﺟﺊ ﻟﺣظﻰ ﻓﻰ اﻟﺗﯾﺎر وﺳﯾﺗم اﻋﺗﺑﺎر ﻣﻛﺛف اﻟﻔﻠﺗر = ‪ 100‬ﺑﯾﻛو ﻓﺎراد‬
‫‪ -‬ﯾﺗم اﺧﺗﯾﺎر ﻣﻘﺎوﻣﺔ ﺗﺣﺳس اﻟﺗﯾﺎر ﻟﻠﻣوﺳﻔت ﺑﻧﺎءا ﻋﻠﻰ اﻗﺻﻰ ﺗﯾﺎر ﻟﻠﻣوﺳﻔت واﻟذى ﺳﯾﺗم ﺗﺣدﯾده ﺑﻧﺎءا ﻋﻠﻰ اﻗﺻﻰ ﻗﯾﻣﺔ ﻟﺟﮭد ﻣدﺧل‬

‫‪/‬‬
‫اﻟﺗﺣﺳس ‪ Isense‬واﻟﺗﻰ ﻗﯾﻣﺗﮭﺎ ‪ 1‬ﻓوﻟت‬

‫اﺣ‬
‫ﻗﯾﻣﺔ ﻣﻘﺎوﻣﺔ اﻟﺗﺣﺳس ‪ = .RCS‬اﻗﺻﻰ ﺟﮭد ﻋﻠﻰ اﻟﻣدﺧل ‪ /‬اﻗﺻﻰ ﺗﯾﺎر ﻟﻠﻣوﺳﻔت = ‪ 0.75 = 1.36 / 1‬اوم‬

‫ﻣد‬
‫‪The high current sense threshold of ISENSE helps to provide better noise immunity to the system but also‬‬
‫‪results in higher losses in the current sense resistor. These current sense losses can be minimized by injecting‬‬
‫‪an offset voltage into the current sense signal using RP. RP and RCSF form a resistor divider network from the‬‬
‫‪current sense signal to the device’s reference voltage, VREF, which adds an offset to the current sense voltage.‬‬
‫‪This technique still achieves current mode control with cycle-by-cycle over-current protection. To calculate‬‬
‫ﯾ‬
‫‪required offset value (VOFFSET), use Equation 22.‬‬
‫وﺳ‬
‫‪R CSF‬‬
‫= ‪VOFFSET‬‬ ‫‪× VREF‬‬
‫‪R CSF + R P‬‬ ‫)‪(22‬‬
‫‪Once RP is added, adjust the current sense resistor, RCS, accordingly.‬‬
‫ف‬

‫‪9.2.2.6 Gate Drive Resistor‬‬

‫ﻟو زادت ﻣﻘﺎوﻣﺔ اﻟﺑواﺑﺔ ﺳﺗﺑطﺊ ﺳرﻋﺔ ﻗﻔل وﺗﺷﻐﯾل اﻟﻣوﺳﻔت وﻟو ﻗﻠت ﺳﺗزﯾد اﻟﺳرﻋﺔ‬
‫وﺗزﯾد اﻟﻣﻔﺎﻗﯾد وﺳﯾﺗم اﺧﺗﯾﺎر ﻗﯾﻣﺔ ﻣﺗوازﻧﺔ ﺑﯾن اﻟﻣﻔﺎﻗﯾد واﻟﺗرددات اﻟﻌﺎﻟﯾﺔ ‪EMI‬‬
‫اﺧﺗﯾﺎر ﻣﻘﺎوﻣﺔ ‪ 10‬اوم ﺗﻛون ﻣﻧﺎﺳﺑﺔ‬
‫اﻟﻣ‬
‫ﺻ‬

‫‪9.2.2.7 VREF Capacitor‬‬ ‫ﻣﻛﺛف ﻣدﺧل اﻟﺟﮭد اﻟﻣرﺟﻌﻰ ‪ -:‬ﺗم اﺧﺗﯾﺎر ﻣﻛﺛف ‪ 1‬ﻣﯾﻛروا ‪ 16‬ﻓوﻟت‬
‫رى‬

‫‪9.2.2.8 RT/CT‬‬ ‫اﺧﺗﯾﺎر ﻗﯾم ﻣﻛﺛف وﻣﻘﺎوﻣﺔ ﺗﺣدﯾد ﺗردد اﻟﺗﻘطﯾﻊ‬

‫ﯾﺗم اﺧﺗﯾﺎر ﻣﻛﺛف وﻣﻘﺎوﻣﺔ اﻟﺗردد ﻻﺧﺗﯾﺎر ﺗردد اﻟﺗﻘطﯾﻊ واﻗﺻﻰ دﯾوﺗﻰ ﺳﯾﻛل ﺣﯾث ﯾﻣﻛن اﺧﺗﯾﺎر ﻛل ﻣﻧﮭﻣﺎ ﺑﻧﺎء ﻋﻠﻰ اﻟﺷﻛل‬
‫اﻟﺗﺎﻟﻰ ﺣﯾث ﯾﺗم ﺗﺣدﯾد اﻟﻣﻘﺎوﻣﺔ ﺑﻌد ﺗﺣدﯾد ﻗﯾﻣﺔ اﻟﻣﻛﺛف ﻋﻠﻰ اﻟﻣﻧﺣﻧﻰ‬
‫ﺗم اﺧﺗﯾﺎر ﻣﻛﺛف ﻗﯾﻣﺗﮫ ‪ 1000‬ﺑﯾﻛو ﻓﺎراد وﻣﻘﺎوﻣﺔ ‪ 15.4‬ﻛﯾﻠو ﻟﮭذا اﻟﻛوﻧﻔرﺗر ﺣﯾث ﺗﻌطﯾﻧﺎ ﺗردد ‪ 110‬ﻛﯾﻠو ھﯾرﺗز‬
9.2.2.9 Start-Up Circuit ‫داﺋرة ﺑدء اﻟﺗﺷﻐﯾل‬

‫ﯾﺗم ﺗوﺻﯾل ﻣدﺧل اﻟﺗﺷﻐﯾل ﻟﻼﯾﺳﻰ اﻟﻰ ﺟﮭد اﻟﺧط اﻟﻣﺳﺗﻣر ﻋﻠﻰ اﻟﻣﻛﺛف ﻋﺑر ﻣﻘﺎوﻣﺔ ﺑدء وﻋﻧد اﺧﺗﯾﺎر ﺗﻠك اﻟﻣﻘﺎوﻣﺔ ﺳﯾﺗم اﻻﺧﺗﯾﺎر‬
‫ﺑﯾن ﺳرﻋﺔ ﺑدء اﻟﺗﺷﻐﯾل وﺑﯾن اﻟﻣﻔﺎﻗﯾد ﻋﻠﻰ اﻟﻣﻘﺎوﻣﺔ ﻻن ﻟو ﺗم اﺧﺗﯾﺎر ﻗﯾﻣﺔ ﺻﻐﯾرة ﻟﺳرﻋﺔ اﻟﺗﺷﻐﯾل ﺳﯾﻛون ﺗﯾﺎر اﻟﺑدء ﻋﺎﻟﻰ وﻟو ﺗم‬
‫ اﻣﺎ ﻣن ﻧﺎﺣﯾﺔ اﻟﺗﯾﺎر اﻟذى ﺳﯾﻣر ﻓﻰ اﻟﻣﻘﺎوﻣﺔ ﯾﺟب ان ﯾﻛون ﻗﯾﻣﺗﮫ ﻋﻧد اﻗل‬- ‫اﺧﺗﯾﺎر ﻗﯾﻣﺔ ﻛﺑﯾرة ﺳﺗﺑطﺊ ﻣن ﻋﻣﻠﯾﺔ ﺑدء اﻟﺗﺷﻐﯾل‬
‫ ﻓوﻟت‬10 ‫ﺟﮭد دﺧل اﻛﺑر ﻣن ﻗﯾﻣﺔ ﺗﯾﺎر ﺷﺣن اﻟﻣﻛﺛف اﺛﻧﺎء ﻓﺗرة اﻟﺷﺣن ﻓﻰ ﺣﺎﻟﺔ ﺟﮭد اﻟﻣﻛﺛف ﻣﻧﺧﻔض ﻋن اﻗل ﻗﯾﻣﺔ ﻟﺟﮭد اﻟﺗﺷﻐﯾل‬
‫ ﻣﻠﻠﻰ ﻋﻧد‬1 ‫ ﻛﯾﻠو ﺳﺗوﻓﻰ ﺑﺎﻟﻐرض ﺣﯾث ﺗﻌطﻰ ﺗﯾﺎر‬100 ‫ اﺧﺗﯾﺎر ﻣﻘﺎوﻣﺔ‬-‫ ﻣﻠﻠﻰ اﻣﺑﯾر ﻛﺎﻗﺻﻰ ﻗﯾﻣﺔ‬1 ‫ﺣﯾث ﻗﯾﻣﺔ ﺗﯾﺎر اﻟﺷﺣن ﺗﺳﺎوى‬
‫ ﻛﯾﻠو ﻋﻠﻰ اﻟﺗواﻟﻰ ﻟﺗﺗﺣﻣل اﻟﻘدرة‬50 ‫اﻗل ﺟﮭد دﺧل ﻣﺳﺗﻣر وﻣﻘﺎوﻣﺔ اﻟﺑدء ﻋﺑﺎرة ﻋن ﻣﻘﺎوﻣﺗﯾن‬

‫اذا ﻟم ﯾﻛن ﻣﻛﺛف اﻟﺗﺷﻐﯾل ﻛﺑﯾر اﻟﺳﻌﺔ ﺑﻣﺎ ﯾﻛﻔﻰ ﻓﺎن ﻋﻧد ﺧروج اﻻﯾﺳﻰ ﻣن ﺣﺎﻟﺔ ﺟﮭد اﻟﺗﺷﻐﯾل اﻟﻣﻧﺧﻔض ودﺧوﻟﮭﺎ اﻟﻰ ﺣﺎﻟﺔ اﻟﺗﺷﻐﯾل‬
‫ ﻣﯾﻛرو ﻓﺎراد ﻋﻠﻰ ﻣدﺧل اﻟﺗﺷﻐﯾل‬120 ‫ﻓﺳﺗﺣﺗﺎج اﻟﻰ ﺗﯾﺎر اﻋﻠﻰ ﻟﻠﺗﺷﻐﯾل ﻟذﻟك ﯾﺟب وﺿﻊ ﻣﻛﺛف‬

‫م‬
9.2.2.10 Voltage Feedback Compensation

/
Feedback compensation, also called closed-loop control, can reduce or eliminate steady state error, reduce the
sensitivity of the system to parametric changes, change the gain or phase of a system over some desired
frequency range, reduce the effects of small signal load disturbances and noise on system performance, and

‫اﺣ‬
create a stable system from an unstable system. A system is stable if its response to a perturbation is that the
perturbation eventually dies out. A peak current mode flyback uses an outer voltage feedback loop to stabilize
the converter. To adequately compensate the voltage loop, the open-loop parameters of the power stage must

‫ﻣد‬
be determined.

9.2.2.10.1 Power Stage Poles and Zeroes

The first step in compensating a fixed frequency flyback is to verify if the converter is continuous conduction
‫ﯾ‬
mode (CCM) or discontinuous conduction mode (DCM). If the primary inductance, LP, is greater than the
‫وﺳ‬
inductance for DCM/CCM boundary mode operation, called the critical inductance, or LPcrit, then the converter
operates in CCM:
LP > LPcrit , then CCM (23)
2
R OUT × :NPS ;2 VIN
×l p
‫ف‬

LPcrit =
2 × fSW VIN + VOUT × NPS (24)
For the entire input voltage range, the selected inductor has value larger than the critical inductor. Therefore, the
converter operates in CCM and the compensation loop requires design based on CCM flyback equations.
‫اﻟﻣ‬

The current-to-voltage conversion is done externally with the ground-referenced current sense resistor, RCS, and
the internal resistor divider of 2R/R which sets up the internal current sense gain, ACS = 3. Note that the exact
value of these internal resistors is not critical but the IC provides tight control of the resistor divider ratio, so
regardless of the actual resistor value variations their relative value to each other is maintained.
‫ﺻ‬

The DC open-loop gain, GO, of the fixed-frequency voltage control loop of a peak current mode control CCM
flyback converter shown in Equation 25 is approximated by first using the output load, ROUT, the primary to
secondary turns ratio, NPS, the maximum duty cycle, D, calculated in Equation 25.
‫رى‬

R OUT × NPS 1
GO = × 2
R CS × ACS :1 F D;
+ :2 × M; + 1
RL (25)
In Equation 25, D is calculated with Equation 26, τL is calculated with Equation 27, and M is calculated with
Equation 28.
NPS × VOUT
D=
VBULKmin + :NPS × VOUT ; (26)
2 × LP × fSW
RL =
R OUT × :NPS ;2 (27)
VOUT × NPS
M=
VBULKmin (28)

26 Submit Documentation Feedback Copyright © 1997–2017, Texas Instruments Incorporated

Product Folder Links: UC1842 UC2842 UC3842 UC1843 UC2843 UC3843 UC1844 UC2844 UC3844 UC1845
UC2845 UC3845
UC1842, UC2842, UC3842, UC1843, UC2843, UC3843
UC1844, UC2844, UC3844, UC1845, UC2845, UC3845
SLUS223E – APRIL 1997 – REVISED JANUARY 2017 www.ti.com

11.2 Layout Example

MOSFET Heatsink

TO-220FP Bottom View

Track To
<= %XON &DS Å RCS1
S G
6

½ PRI Winding
RCS2
Track To
Transformer =>

‫م‬
FBead
D

/ ½ PRI Winding
RSNUB

‫اﺣ‬
CSNUB
Track To
<= Bulk Cap +

‫ﻣد‬
4
22AWG
Jumper
‫ﯾ‬
TRANSFORMER
Wire
‫وﺳ‬
RCSF

CCSF
‫ف‬

CCT
Wave Solder Direction ==>

GROUND RT/CT CRAMP

RG OUTPUT ISENSE RRAMP

‫اﻟﻣ‬

UCx84x
CVCCbp VCC VFB
CVCC 2
VREF COMP
AUX Winding
‫ﺻ‬

CVREF CCOMPp Aux Cap

RRT RCOMPp
‫رى‬

RP RFBG
CVCC1
1
ROPTO

22AWG Jumper
Wires E K

OPTO-ISOLATOR

C A

PCB Bottom-side View

Copyright © 2016, Texas Instruments Incorporated

Figure 35. UCx84x Layout Example

34 Submit Documentation Feedback Copyright © 1997–2017, Texas Instruments Incorporated

Product Folder Links: UC1842 UC2842 UC3842 UC1843 UC2843 UC3843 UC1844 UC2844 UC3844 UC1845
UC2845 UC3845
‫رى‬
‫ﺻ‬
‫اﻟﻣ‬
‫ف‬
‫وﺳ‬
‫ﯾ‬ ‫ﻣد‬
‫اﺣ‬
‫‪/‬‬ ‫م‬