si Deen 109 Inretucten to MOS Tansitor Long Channel FV Characteristics # The MOS teansistors are voltage controlled device (as against the bipolar (ansistocs are current controlled device), A voliage on the gate terminal induces a charge in the channel that exists between source and drain. The charge then move from source to érain under the influence of electric field yenerated by voltage Vg applied between drain and source, The charge Induced is dependent on the gate to source voltage Vos (centealling factor), the curtent Ips is dependent on both Vox and Vg Tae relationship between these parameters can be developed. + Consider a typical structure of AMOS transistor as shown in Fig. 1.6.1 Fig. 1.61 nMOS transistor structure Expression for Transit Time : ©The drain to souree currant Ios is given by = Ge semen Part Br Tis clectron transit time # ‘The current Ipg is due to electrons flowing from source to drain. The transit time for travel of electrons or hole from source ta drain (t4a) Is given as tat 6.62) vestosegn 1-70 Intedueten to MOS Transistor whore, Luis length of channel Vis velocity of electrons 0° holes + Velocity of electrons is given as - v= WE (163) nis electron or hole mobility (susface) Ey is electric felé between drain to source + IC Vpg is voltage between drain and source By = US es) v aps (65) Putting in equation (1.62) we get, 2 (066) e The clectron and hele mobiiitice at reer temperature,+ The electron and hele mobilitics at room. temperature, Hy = 650 em?/V sec (surface) Hp = 240 cn8/¥ see (surface) EET non-saturated Region + When dovice Is operated in non saturated region, the IR drop in the channel is same tnoighout the channel and ca be taken a8 average vale ae YES. 2 where, Yon is voltage difference betwen gate and channel assuming substrate conncetcd to channel + Tn non saturated region, the offective gate voltage V, fs given by - Ve = Vos-Mt (U67) whore, V, is threshold voltage needed to invert the charge under the gate and to csisblish the channel. = The charge gets induced into the channel due to gate voltage and if E, is che overage electric field from gate to channel ‘The charge por unit area = E, Fiat 68) where, fim i relative permitivity of insulation between gate and channel (=4for siteon oxide) TECHNCHL PUBLEATONS™ Anup nat tr one Ms!Design fete Inteducton to MOS Transistor fo is permitivity of free space (885x104 F / cx) + The total induced charge forthe area of WL is given by, Q = EyenetoWL (169) + Now, ives -Ve E, [roweP] (16.10) where, Dis oxide thickness. + Putting the expression for B= Q- feet ves w= (6.11) + From equations (16.11) (1.66) and (15.) Is = Sinsol Elves w= (16.12) Ips = K Eves-vore-*F] » (16.13) where, facor k = fifo «Tate M dein he sort fe deve and can be comin wi actor K wo give, w p= Ke bs = foto Won ais ‘© The capacitance formed by gate and channel has a parallel plate geometry. eugtoWL Cpe = = (1.6.15) ‘Tren in terms of Cyc =OE EEE BeCaay 5 Wo a re 2 "TEEPINEAL PUBLICATIONS An rete MS/Desion tr Intecucton to MOS Transistor Seer tinction to MOS Transistor Gate capacitance per unit atea Cy oF Cyy is defined as : Cea WL ‘Therefore Ips ean be written as = (16.18) les = cont [ve wove “B| Ex. 1.641 Desig the circuit sown in Fig. 16.2 to establish a de. vllage of + 9.9 V at the source, At this operating point, what i effctice resistance betateen source and drain of transistor ? ov, ov Rp Fig. 1.62 Assume Vj == 1 V ent B= Lind 1Y2 Sol: From Fig. 1.62, Vis = Vp-Vs = 10-99 =01V Vos = 0 Gren Vy = -1V B= Tmayy? Drain current Ip is given by, By = BlVcs~Ve) Vos — TECHONCAL PUBLICATIONS" Ane rene MSIDesen 2 Invetction to MOS Transistor Ip = 0.095 ma Now Rp can be computed as, = Ans.+ The device enters into saturation when Vs IR drop in the chane! equals the effective gs through the channel remains faiely constant for «W Wos- Vu? fos ~ Vj, Pecause at this point the fe to channel voltage, The current any further inerease in Vp tos = x Wes 1619 = bives- vr 68) BG Jos = Mes vy? (1619) (1420) * The expression for tps hold for both, the. deplet devices. However, and enhancement mode the threshold voltage for nMOS depletion mode device is negative and denoted by Viy * ‘Typical characteristics nMOS transistors are shown Fig. 1.63 pMOS transistor ‘characteristics are similar with suitable reversal of polar y thee regions. Following expression summarizes curvent ee TECHNICAL PLRLICATONS- Anup fe bowie MSI Design fem Intetuction to MOS Transistor a_i ta OS Trait lo Vesey Cut-off vee tn= fo Yes- YB ]ves Yan Van te Fves-WF Vos? Vag Satration {) Depletion mode device Vos #08 Voo Saturation Wg > Veg MY) Vos" 05¥o9, ° 05 Vag VeeRe Delay model — del ay of lagi Jats frodvet Key R is offechve Deristenk , in wad capaciome > Mininem clevin eagth padvus Alek ay, consumphen- Dey ag fren ister is computed 2 daives ahaa and pues depends om widths leic gate baad. on gt and Alaci fence 4 ae Re madeh hee seh ere WF = Tt woies a Gills ge bransisty = k width kel 3Rete note : inverter unit nal Jusistente B55 ful mobil pMos esa widia greet ~ me 9 s Fhe oak seh => e a ak unit width he 2 Ac date mode] rents EfansistS an aulstehea in satin willy Aerts <5 Nimoy bramtr gg K Hines nif uldth fan Aerittonce. BR] and fies bransister hem geet Aviitance , thos aA A > Prpagahion delay ba is eimatel 92 RO Fime — comsterk 2h, the Aan shor Aisch angi ng dittusjen and load capaci trehe chelate wn oclel Cues inverter — fropag vtion delay ps ae ny and Mes be achieve oo width gf bran state i fall and Ate agp PER, Chet) equal pmes — width = VY equivalent Re model f Pepagstion delay Z ze ba HR. (6c) = CRO J ¥ | iy wlimated 28 AS g teeninter Hime constant the. y Atsis tr djs ch as 44 clifpusion and feat sepaciban ee a a~x< da = 6) 3 do = 6)? 9. 2 ¢/3 gv = 6 [3 p = 12] 3Scaling OE oso ‘+ VLSI fabrication processes are being nimed at achieving smaller line widths and size (cheap area) for higher packing density. ‘This scaling-down must also improve Girenit performance. Several indicators of micro circuit technology are, §) Count of gates on chip i) Minimum size of device iii) Power dissipation {v) Maximum frequency of operation ¥) Die size ‘= Scaling improves the figure of merit by shrinking the dimensions of transistors and interconnection between them. Merits of Scaling Increased chip density ie. more number of gate counts on single chip. 2. Improved chip performance i.e, increased speed and reduced power consumption. . Improved device characteris Reduced parasitic capacitance. Reduced interconnect delays between devices. Chip cost reduces considerably. ics. L 2 3. 4 & Demerits of Scaling |. Eventhough overall power consumption reduces but power consumption per unit area increases due to sealing. Henee device gets heated up during its operation. 2. Because of sealing down, cartier mobility reduces whic intum reduces gain of device. 3. Reduced conductor size decreases current carrying capacity 4. High package density increases heat generated which is to be dissipated by foreed cooling Si Design Introctcton to MOS Transistor Lambda based Design Rule = The lambda based design rule specify every dimension of a system interms of a parameter % which is subsequently assigned a value, such that the features resulting out of the design are supported by the fabrication process. The technology used decide the value of lambda, + Lambda is defined as the maximum distance by which a geometrical feature can stray from another feature with a suitable safety factor, Lambda is maximum misalignment of a feature from its intended position chip. ‘= Defining Lambda makes design independent of process therefore chip can be sealed to any ratio that means today’s design remain usable when line widths are reduced (ie. the value assigned to 7. 13 reduced) by advances in future technology. EERE Models of Scaling ‘© There are three models of scaling - 1. Constant field (constant B) scaling. 2. Constant voltage (constant V) scaling, 3. Lateral scaling ‘+ Constant field scaling says that the characteristics of devices can be maintained preserved if critical parameters of a device ‘are scaled in accordance to a given criteria. The scaled device is obtained by applying 2 dimensionless factor x to dimensions, device voltages concentration densities. ‘and the basic operational character © In Ginilent Fig. 4.11.2 (b) d and E versus substrate doping Me) TFECHNCAL PUBUCATONS Arup rao ioe Vist Design 1116 Invoducton to MOS Transistor occur and thus allowable values for d fall below the dashed line and above the V,=0 line. The maximum electric field Eq in the depiction layer as a function of Ne is shown in Fig, 111.2 (b). Any applied voltage more than V, =0 causes breakdown at lower values of Ng. EEEEG] Limitations of Miniaturization ‘+ The factors that decide the minimum possible size of a transistor are 1) The physics of the transistor. liy The technology involved in the fabrication process. = The constraints applicable to both these factors dictate the device geometry. Process capability such as alignment accuracy and the resolution of ‘Photolithographic process put the limits on miniaturization, For instance, the limit fon feature size at present is at 0.3 wu which may go further down by virtue of the dircet write E-beam technology. ‘¢ The maximum dimension pertaining to a transistor is its channel length L, which ee he aha ae= The maximum dimension pertaining to a transistor is its channel length L, which is usually used to define is size. Now with sealing of channel length, the edge of the depletion region around the source comes closer to that around the drain. Ifa certain minimum distance is not maintained between these two, punch through may take place. In order to prevent this, and ensure proper transistor action, the channel length L must be atleast 2d, where d is the depletion region width. As already discussed, value of d is dependent on substrate doping concentration Ng and supply voltage Vpp. Hence L is in tum determined by Vpp and Ng and minimum possible L can assume is 0.14 jun, The time for an electron to lravel from source to drain depends on channel length L. ‘The cartier drift velocity Vig = EM and b= 2d aes Voie EH from which transit time © Carriers move with maximum velocity under saturation. Hence maximus carrier drift velocity is vy = 1107 cm/sec. This is regardless of the supply voltage. ‘Therefore the minimum transit time corresponds to minimum size transistor for V,=0V, Transit time as a function of Np and L is given graphically in Fig, 1.13 (@) andl {b) respectively TECHCAL PUBLICATIONS. Anup mur owe ur Introduction to MOS Transistor imu + versus Ny for ham 01050 “ranet re he Pe ‘" 10” 0 0 ‘Subtate concertos fe? tg) Fig. 1.11.3 (a) Transit time x versus substrate concentrationiem? BRERA Limits of Contact Resistance and Interconnect + Interconnects also undergo scaling and the width, thickness and spacing of interconnects are each scaled by a factor of 1/a, The scaling factor for the cross-sectional areas is hence 1/4, Thus, for interconnects for short distance, the conductor length is also sealed by 1/c duc to which the resistance increases by a factor ct. In the constant field scaling model, current I is also sealed by 1/c Hence IR érop remains constant inspite of scaling, But the supply valiage Vp is also scaled by 1/4. Thus there is a higher proportion of the scaled Vpp across the scaled interconnect. This is a degradation of driving capability and noise margins.scaled interconnect. This is a degradation of driving capability and noise margins. The decreasing device dimensions result into increase in die size. Due to this, longer interconnections run from one side of the chip to the other. This has an effect of increased resistance and capacitance values of the interconnects resulting, into higher time constant values. As a consequence one would get increased Propagation delays, signal decay and clock skew. This will decrease the maximum, operating frequency, fo, even though the smaller transistors produce gates with less delay. Thus scaling of interconnects requires a careful consideration. TECHNICAL PUBLICATIONS”. Ao up atte knoe WsIDesion 18 Introduction to MOS Transistor (Mirimum transt ime «versus channel length L oj i i Eo” : é wt ws e + i. w rs 1 (Channa engh npn = Fig. 1.11.3 (b) Transit time t versus L + One cbviovs remedy to this problem is to use multilayer interconnections with thicker, wider conductors and thicker separating layers. This approach has other advantages, apart from reduction of R and C, such as reduced die size. Other possible solutions include the introduction of cascaded drivers and repeaters to reduce the effects of long interconnects. + Wherever a very high level of integration is required to be realized for high speed more advanced interconnection techniques are hamessed. This includes optical interconnection by use of optical fibres, laser diodes, optical receivers and amplifiers in the IC. The resulting performance is certainly improved, although depending on the materials used. A rough estimation of the performance with these techniques prepared to compare with that with metal interconnects. The metal interconnected is shown modelled in Fig. 1.11.4 for purpose of analysis. TECNNICAL PUBLICATIONS”. ho up ter rowedan a 1. Fig. 1.11.4 Model of metal interconnect ieserdonneet ‘+ The figure shows an interconnect between two devices. The propagation delay Ty along sueh a single aluminium interconnect is given by Ty = 23 (Rog Cy + Roe Cigt + Rie C1)* Rint Cit wwheze, Ry is the transistor ON resistance. Cine is the capacitance of the interconnect. Ruy is the resistance of the interconnect This can be approximated as Ty = Cunt (23 Ron + Rint) Lp Bot Ri = ee and Cage = Foy [2.28 (H Sox)??? 4115 W / tex where L, W and H are respectively the length, width and height (thickness) of the interconnect. p its resistivity and ty ‘the thickness of the dielectric oxide. © Consider a typical set of specifications such a8 ty =08 um, p=31Q em for aluminium, typ =34515X10- pF /um on permittivity of $02 and interconnect dimensions as L=1 em, W=3y1m and H=1 ym. The propagation delay Ty comes to (23x5x10? +01%109) x25x]0-2? =20x107 see = 29 nsec ‘+ Consider optical fibres replacing metal interconnects in critical and applications. The optical fibre arrangement is shown modelled in Fig, 1.115 where Rigs and Cy are asstumed to be zero. [TECHINCAL PUBLICATIONS. Ap hu oun si esgn tnfroaticton io MOS Transistor s optcSi moar - Fig, 1.11.5 Electro-optical interconnection ‘© The time required for the output driver to transfer a logic state fs the propagation dolay in this case and is given by Ty = tenet Hint + Maser +23 Roy CE where yg is the delay time of the receives, tig: 's the propagation delay time along the optical fiber interconnect, tase 15 the laser diode delay time and Cy is the input capacitance of the laser diode.Re Weep Eonar, in laycyrenecs Stntey are Le fie = where Lis the length of the fiber, 1 the refractive index of the optic fiber material and is the speed of light in free space = 3x108 m/sec. ‘= Laser diodes and reveivers are high speed devices having self-telays of around 100 psec. The refractive index m of commonly used material for optic fibers lies between 15 and 2 and the capacitance of a discrete laser diode is about 1 pF. Using these typical values, the propagation delay nee Tye r0- 2M 10-1 29K 5 IOP xLRIOT 17.00% 3x 108 17 nsec ‘+ Therefore the propagation delay of the optic fiber interconncet as compared to that ff the aluminium interconnect is low. Comparative propagation delays. against varying length L of interconnects are presented in Fig. 1.11.6 (a) clearly, the fibre ‘optic interconnect has an upper hand, especially: for longer interconnects. In Fig, 1-116 (b) the dependence of propagation delay on interconnect width W shown for different materials (optic fibre does not appear here obviously). It observed through experience that Ry, is the dominant factor for aluminium while Rigg is the major contribulor to delay for poly TECINCAL PUBLICATIONS". Ane Prt rire VLSI Design 4934 Introduction to MOS Transistor Interconnect wien W = 1m se 7 8 8 0 2 iW Lengm Lot interconnect (rem) —= 11.6 (a) ‘© By making the laser diodes and receivers a part of the IC itself their performance can be further improved. This integration is more facilitated by GaAs material since it can accomodate both electronic components and optical interconnections in the same chi.Pronegson diy (8) = Length efterconec: ten) = Fig, 1.11.6 (b) Interconnect delay versus width and length Limits due to Subthreshold Currents ‘+ In the process of scaling, proper consideration is required to be given to the effect fon subthreshold current, La Now fay YH AT © With the scaling of voltages, Vg —V,)/ AT reduces due to which subthreshold ‘current increases substantially. To avoid this, both Vj. and ¥; may be scaled along with Vpp by a larger factor. However this causes the electric field strength to increase and thereby lowers breakdown voltages. We derived that Emax is scaled. by @ B40) / B(c+1), Junction breakcown voltage BY is given by = 08s ent)” py = Sot Fe) TECNMCAL PUBLICATIENS. Anup eo mouse Ls! Deen sates Iirocustion to MOS Tranetcior + Thus scaling factor for BV is B/(e+1) /.a? (B+e) and will decrease with scaling. Hence estimation of breakdowa vollage BV of sealed devices should be done with due care. Limits on Supply Voltage and Logic Levels due to Noise ‘+ Scaling is accompanied by decreased inter-feature spacing and greater switching, speed which unfortunately bring in noise problems, Situations may also amplify noise and this calls for special corsidecation, The mean squared noise due to current fication in the channel is given by @) = ART Ry: Afgn where Af is the bandwidth over which Ry is the equivalent noise resistance at tbe input. ‘+ In the saturation mode of operation of a transistor, its gq docs not have a Linear relationship with the gate voltage Vp. The expression for guy i gm = VpBSa = hp where po WHC oe and Vp is the pinch off voltage which is @ monotonically decreasing function of the gate oxide thickness fy, and substrate doping Np. Similarly R, is a monotonically decreasing function of the same parameters. The thermal noise is mainly contributed by Ry Sx which are strongly and directly dependent on tay and Ng ané also somewhat on Vg. This dependence is graphically shown in Fig. 111.7. (See Fig. on next page). «In the constant field scaling, model, Vy is sealed by 1/4, Ng and Cay are sealed by @. Hence the product of Ry gq is only slightly decreased owing to the increased value of Cj, As © cesult, the zatio of logic level to. thermal noise undergoes degredation by almest the same factor. + Another type of noise is the flicker noise which is the result of fluctuations of carviers trapped in the channel by surface states. Current ffuctuations Af at the output as a result of change in the number of trapped carriers sin, due to the change in the number of induced froe eartiers dy are such that ait = Me laVe fe where = dn /4, is the surface state efficiency Lis the DC. deain current V, is the applied drain voltage {is the frequency. TECHNICAL PUBLICATIONS” Anup forbade VLSI Design 42128 Intrextuston to MOS Trensistor ‘Temmal neice = ae eas ae aS Oxi neness (gin —e Fig. 1.11.7 (a) Thermal noise versus oxide thicknossFig. 1.11.7 (b) Substrate doping Since § is a process dependent factor, the flicker noise has a scaling factor of one for constant field scaling or of .?/B? for the combined scaling model. TECHNICAL PUBLICATIONS”. An up thrust for knowledge VLSI Design 1-125 Introduction to MOS Transistor © Other noise sources than those already considered are those occurring due to mutual inductive and mutual capacitive coupling and these alone could impose constraints on the lowest usable operating voltages. There can occur a cross talk between two parallel signal lines on a chip. The crosstalk noise increases as the operating frequency is increased and t,, the rise time of the coupled signal, is reduced. The designer has to provide precautions against other noise sources due to external influences, such as radio frequency signals, unterminated signal lines and lines with non uniform impedance characteristics, voltage spikes or voltage drops on power lines or ground connections, etc. * One under serious effect of scaling down is that it enhances the effect of both internally and externally generated noise which degrades both the reliability and production yield of high density chip layouts. Limits of Scaling due to Gurrent Density * When optic fiber interconnects are not used, the most widely used material for forming interconnections in VLSI chips is high purity aluminium. Although aluminium has high conductivity, scaling down of dimensions also increases the current density in interconnects by the same factor for the constant field scaling. Hence current density through interconnects increases.