Professional Documents
Culture Documents
22-Feb-2024
23-Feb-2024
26-Feb-2024
27-Feb-2024
Week 4 28-Feb-2024 Digital Sequential Circuit II Week 5
29-Feb-2024
1-Mar-2024
26-Feb-2024
27-Feb-2024 FSM
Week 5 28-Feb-2024 Digital Week 6
29-Feb-2024
Memories
1-Mar-2024
18-Mar-2024
Introduction to Verilog HDL
19-Mar-2024
Week 6 20-Mar-2024 Verilog Week 7
Data types
21-Mar-2024
22-Mar-2024 Lab1
25-Mar-2024
26-Mar-2024
Week 7 Verilog Operators Week 8
27-Mar-2024
28-Mar-2024
4-Apr-2024
5-Apr-2024 Lab3
8-Apr-2024
Assignments
9-Apr-2024
Week 9 10-Apr-2024 Verilog Week 10
Structured Procedures
11-Apr-2024
12-Apr-2024 Lab4
8-Apr-2024
9-Apr-2024
Synthesis Coding styles
Week 10 10-Apr-2024 Verilog Week 11
11-Apr-2024
12-Apr-2024 Lab5
15-Apr-2024
16-Apr-2024
FSM
Week 11 17-Apr-2024 Verilog Week 12
18-Apr-2024
19-Apr-2024 Lab6
22-Apr-2024
23-Apr-2024
Week 12 24-Apr-2024 Project specification Specification analysis Week 13
25-Apr-2024
26-Apr-2024
29-Apr-2024
30-Apr-2024
Project
Week 13 1-May-2024 Implementation
Block level architecture Week 14
2-May-2024
3-May-2024
6-May-2024
7-May-2024 Project
Week 14 Serial clock generator (RTL/TB) Week 15
8-May-2024 Implementation
9-May-2024
16-May-2024
17-May-2024
6-May-2024
7-May-2024
Project
Week 16 8-May-2024 Implementation
SPI top module (RTL/TB) Week 17
9-May-2024
10-May-2024
Final test is scheduled for 27th May 2024