UT Austin, ECE Department

VLSI Design
6. Logical Effort

Introduction
6. Logical Effort • Chip designers face a bewildering array of
choices
• Last module: – What is the best circuit topology for a function?
– DC Response – How many stages of logic give least delay?
– How wide should the transistors be?
– Logic Levels and Noise Margins
– Transient Response
• Logical effort is one method to make these
decisions
– Delay Estimation
– Uses a simple model of delay
• This module: – Allows back-of-the-envelope calculations
– Delay in logic networks – Helps make rapid comparisons between
– Choosing the best number of stages alternatives
– Emphasizes remarkable symmetries
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Example Delay in a Logic Gate

• Express delays in process-independent unit
• Design the decoder for a register file.
τ = 3RC
A[3:0] A[3:0]
d abs
d=
32 bits

≈ 12 ps in 180 nm process
• Decoder specifications: τ 40 ps in 0.6 μm process
4:16 Decoder

16 words

d= f +p
16
Register File
– 16 word register file • Delay has two components,
– Each word is 32 bits wide • Effort delay f = gh (a.k.a. stage effort)
– Each bit presents load of 3 unit-sized transistors
g: logical effort h: electrical effort = Cout / Cin
– True and complementary address inputs A[3:0] Measures relative ability Ratio of output to input caps.
– Each input may drive 10 unit-sized transistors of gate to deliver current Sometimes called fanout
• Need to decide: g ≡ 1 for inverter effort
– How many stages to use?
• Parasitic delay p
– How large should each gate be? – Represents delay of gate driving no load
– How fast can decoder operate? – Set by internal parasitic capacitance
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Delay Plots Computing Logical Effort

d =f+p • Logical effort is the ratio of the input
= gh + p 2-input capacitance of a gate to the input
NA ND Inv erter
6
g = 4/3
capacitance of an inverter delivering the
NormalizedDelay:d

5 p=2 same output current

• What about 4 g=1
d = (4/3)h + 2
• Measure from delay vs. fanout plots
p=1
NOR2? 3 d = h +1
• Or estimate by counting transistor widths
2 Ef f ort Delay : f
2 2 A 4
1
Y
Paras itic Delay : p 2 B 4
A 2
0 A Y Y
0 1 2 3 4 5 1 B 2 1 1
Elec tric alEf f ort:
h = C out / C in Cin = 3 Cin = 4 Cin = 5
g = 3/3 g = 4/3 g = 5/3

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UT Austin, ECE Department
VLSI Design
6. Logical Effort

Catalog of Gates Catalog of Gates

• Logical effort of common gates • Parasitic delay of common gates
– In multiples of pinv (≈1)
Gate type Number of inputs
1 2 3 4 n Gate type Number of inputs
Inverter 1 1 2 3 4 n
NAND 4/3 5/3 6/3 (n+2)/3 Inverter 1
NOR 5/3 7/3 9/3 (2n+1)/3 NAND 2 3 4 n
Tristate / 2 2 2 2 2 NOR 2 3 4 n
mux Tristate / mux 2 4 6 8 2n
XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8 XOR, XNOR 4 6 8

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Example: Ring Oscillator Example: FO4 Inverter

• Estimate the frequency of an N-stage ring • Estimate the delay of a fanout-of-4 (FO4)
oscillator inverter
d

• Logical Effort: g = 1 31 stage ring oscillator in

Electrical Effort: h = 1 0.6 μm process has Logical Effort: g = 1 The FO4 delay is about
frequency of ~ 200 MHz
200 ps in 0.6 μm process
Parasitic Delay: p = 1 Electrical Effort: h = 4
60 ps in a 180 nm process
Stage Delay: d = 2 Parasitic Delay: p = 1
f/3 ns in an f μm process
Frequency: fosc = 1/(2*N*d) = 1/4N Stage Delay: d = 5 (f/3 ps in an f nm process)

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Multistage Logic Networks Paths that Branch

• Logical effort generalizes to multistage
networks • No! Consider paths that branch:
• Path Logical Effort G = ∏ gi
15
Cout-path G =1 90
• Path Electrical Effort H= H = 90 / 5 = 18 5
Cin-path
15
GH = 18 90
• Path Effort F = ∏ f i = ∏ gi hi
h1 = (15 +15) / 5 = 6
10
x
y z h2 = 90 / 15 = 6
20
g1 = 1
h1 = x/10
g2 = 5/3
h2 = y/x
g3 = 4/3
h3 = z/y
g4 = 1
h4 = 20/z
F = g1g2h1h2 = 36 = 2GH
• Can we write F = GH in general?
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UT Austin, ECE Department
VLSI Design
6. Logical Effort

Branching Effort Multistage Delays

• Introduce branching effort • Path Effort Delay DF = ∑ f i
– Accounts for branching between stages in path

b=
Con path + Coff path • Path Parasitic Delay P = ∑ pi
Con path
• Path Delay D = ∑ d i = DF + P
B = ∏ bi
Note:

∏ hi = BH
• Now we compute the path effort
– F = GBH

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Designing Fast Circuits Gate Sizes

D = ∑ d i = DF + P • How wide should the gates be for least
• Delay is smallest when each stage bears delay?
same effort fˆ = gh = g CCoutin
1
fˆ = gi hi = F N
gi Couti
⇒ Cini =
• Thus minimum delay of N stage path is fˆ
1
D = NF N + P • Working backward, apply capacitance
transformation to find input capacitance of
• This is a key result of logical effort
• Find fastest possible delay
each gate given load it drives
• Doesn’t require calculating gate sizes • Check work by verifying input cap spec is
met
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Example: 3-stage path Example: 3-stage path

x

• Select gate sizes x and y for least delay x

y
45
from A to B A 8
x
y B
45
x
Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27
y Electrical Effort H = 45/8
x
45
Branching Effort B=3*2=6
A 8
x Path Effort F = GBH = 125
y B
45 Best Stage Effort fˆ = 3 F = 5
Parasitic Delay P=2+3+2=7
Delay D = 3*5 + 7 = 22 = 4.4 FO4
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UT Austin, ECE Department
VLSI Design
6. Logical Effort

Example: 3-stage Path Best Number of Stages

• Work backward for sizes • How many stages should a path use?
y = 45 * (5/3) / 5 = 15 – Minimizing number of stages is not always
fastest
x = (15*2) * (5/3) / 5 = 10
• Example: drive 64-bit datapath with unit
inverter InitialDriver 1 1 1 1

8 4 2.8

45 16 8

A P: 4
P: 4 23
N: 4
N: 6
P: 12 B
45
D = NF1/N + P
N: 3 DatapathLoad 64 64 64 64

= N(64)1/N + N N:
f:
1
64
2
8
3
4
4
2.8
D: 65 18 15 15.3
Fastest

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Derivation Best Stage Effort

• Consider adding inverters to end of path • pinv + ρ (1 − ln ρ ) = 0 has no closed-form
– How many give least delay? solution
N - n1 ExtraInverters
Logic Block:
n1 n1Stages

D = NF N + ∑ pi + ( N − n1 ) pinv
1

• Neglecting parasitics (pinv = 0), we find ρ =

Path Effort F

i =1
∂D 1 1 1
2.718 (e)
= − F N ln F N + F N + pinv = 0 • For pinv = 1, solve numerically for ρ = 3.59
∂N

• Define best stage effort ρ = F

1
N

pinv + ρ (1 − ln ρ ) = 0

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Sensitivity Analysis Decoder Ex: Number of Stages

• How sensitive is delay to using exactly the best • Decoder effort is mainly electrical and branching
number of stages? Electrical Effort: H = (32*3) / 10 = 9.6
1.6
1.51
Branching Effort: B=8
D(N) /D(N)

1.4
1.26
1.2 1.15

1.0

(ρ =6) (ρ =2.4) • If we neglect logical effort (assume G = 1)

Path Effort: F = GBH = 76.8
0.0
0.5 0.7 1.0 1.4 2.0

N/ N
Number of Stages: N = log4F = 3.1
• 2.4 < ρ < 6 gives delay within 15% of optimal
– We can be sloppy! • Try a 3-stage design based on rough estimation
– For example, use ρ = 4

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UT Austin, ECE Department
VLSI Design
6. Logical Effort

Decoder: Gate Sizes & Delay Decoder: Comparison

Logical Effort: G = 1 * 6/3 * 1 = 2 (not estimation) • Compare many alternatives with a
spreadsheet
Path Effort: F = GBH = 154
Design N G P D
Stage Effort: fˆ = F 1/ 3 = 5.36
NAND4-INV 2 2 5 29.8
Path Delay: D = 3 fˆ + 1 + 4 + 1 = 22.1
Gate sizes: z = 96*1/5.36 = 18; y = 18*2/5.36 = 6.7 NAND2-NOR2 2 20/9 4 30.1
A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]
INV-NAND4-INV 3 2 6 22.1
10 10 10 10 10 10 10 10 NAND4-INV-INV-INV 4 2 7 21.1
NAND2-NOR2-INV-INV 4 20/9 6 20.5
y z word[0]
NAND2-INV-NAND2-INV 4 16/9 6 19.7
96 units of wordline capacitance
INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4
y z word[15]
NAND2-INV-NAND2-INV-INV-INV 6 16/9 8 21.6
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Review of Definitions Method of Logical Effort

1) Compute path effort F = GBH
Term Stage Path 2) Estimate best number of stages N = log 4 F
N
number of stages 1 3) Sketch path with N stages
G = ∏ gi 1
D = NF N + P
logical effort g
4) Estimate least delay
H=
Cout-path
electrical effort h= Cout
Cin-path
Cin
5) Determine best stage effort fˆ = F N
1

B = ∏ bi
Con-path +Coff-path
branching effort b= Con-path

effort f = gh F = GBH

6) Find gate sizes gi Couti

effort delay f DF = ∑ f i Cini =
P = ∑ pi
fˆ
parasitic delay p

d= f +p D = ∑ d i = DF + P
delay
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Limits of Logical Effort Summary

• Chicken and egg problem • Logical effort is useful for thinking of delay in
– Need path to compute G circuits
– Numeric logical effort characterizes gates
– But don’t know number of stages without G
– NANDs are faster than NORs in CMOS
• Simplistic delay model – Paths are fastest when effort delays are ~4
– Neglects input rise time effects – Path delay is weakly sensitive to stages, sizes
• Interconnect – But using fewer stages doesn’t mean faster paths
– Iteration required in designs with wire – Delay of path is about log4F FO4 inverter delays
– Inverters and NAND2 best for driving large caps
• Maximum speed only
• Provides language for discussing fast circuits
– Not minimum area/power for constrained delay
– But requires practice to master
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