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CS3351 DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION LT PC

3 02 4
COURSE OBJECTIVES:
• To analyze and design combinational circuits.
• To analyze and design sequential circuits
• To understand the basic structure and operation of a digital computer.
• To study the design of data path unit, control unit for processor and to familiarize with the
hazards.
• To understand the concept of various memories and I/O interfacing.

UNIT I COMBINATIONAL LOGIC 9

n
Combinational Circuits – Karnaugh Map - Analysis and Design Procedures – Binary Adder –
Subtractor – Decimal Adder - Magnitude Comparator – Decoder – Encoder – Multiplexers -

e.i
Demultiplexers

UNIT II SYNCHRONOUS SEQUENTIAL LOGIC 9

Introduction to Sequential Circuits – Flip-Flops – operation and excitation tables, Triggering of FF,
Analysis and design of clocked sequential circuits – Design – Moore/Mealy models, state

UNIT III
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minimization, state assignment, circuit implementation - Registers – Counters.

COMPUTER FUNDAMENTALS 9
Functional Units of a Digital Computer: Von Neumann Architecture – Operation and Operands of
Computer Hardware Instruction – Instruction Set Architecture (ISA): Memory Location, Address
tes
and Operation – Instruction and Instruction Sequencing – Addressing Modes, Encoding of Machine
Instruction – Interaction between Assembly and High Level Language.

UNIT IV PROCESSOR 9
Instruction Execution – Building a Data Path – Designing a Control Unit – Hardwired Control,
No

Microprogrammed Control – Pipelining – Data Hazard – Control Hazards.

UNIT V MEMORY AND I/O 9

Memory Concepts and Hierarchy – Memory Management – Cache Memories: Mapping and
Replacement Techniques – Virtual Memory – DMA – I/O – Accessing I/O: Parallel and Serial
Interface – Interrupt I/O – Interconnection Standards: USB, SATA
w.

45 PERIODS

PRACTICAL EXERCISES: 30 PERIODS

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1. Verification of Boolean theorems using logic gates.

2. Design and implementation of combinational circuits using gates for arbitrary functions.
3. Implementation of 4-bit binary adder/subtractor circuits.
4. Implementation of code converters.
5. Implementation of BCD adder, encoder and decoder circuits
6. Implementation of functions using Multiplexers.
7. Implementation of the synchronous counters
8. Implementation of a Universal Shift register.
9. Simulator based study of Computer Architecture

www.Notesfree.in
 www.Notesfree.in

COURSE OUTCOMES:
At the end of this course, the students will be able to:
CO1 : Design various combinational digital circuits using logic gates
CO2 : Design sequential circuits and analyze the design procedures
CO3 : State the fundamentals of computer systems and analyze the execution of an instruction
CO4 : Analyze different types of control design and identify hazards
CO5 : Identify the characteristics of various memory systems and I/O communication
TOTAL: 75 PERIODS

TEXT BOOKS:
1. M. Morris Mano, Michael D. Ciletti, “Digital Design : With an Introduction to the Verilog HDL,
VHDL, and System Verilog”, Sixth Edition, Pearson Education, 2018.

n
2. David A. Patterson, John L. Hennessy, “Computer Organization and Design, The
Hardware/Software Interface”, Sixth Edition, Morgan Kaufmann/Elsevier, 2020.

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REFERENCES:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig Manjikian, “Computer Organization and
Embedded Systems”, Sixth Edition, Tata McGraw-Hill, 2012.
2. William Stallings, “Computer Organization and Architecture – Designing for Performance”,
Tenth Edition, Pearson Education, 2016. fre
3. M. Morris Mano, “Digital Logic and Computer Design”, Pearson Education, 2016.
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 www.Notesfree.in

CS3351 - DIGITAL PRINCIPLES & COMPUTER ORGANIZATION

UNIT II

SYNCHRONOUS SEQUENTIAL LOGIC

Introduction to Sequential Circuits – Flip-Flops – operation and excitation tables, Triggering of FF,

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Analysis and design of clocked sequential circuits – Design – Moore/Mealy models, state minimization,

state assignment, circuit implementation - Registers – Counters.

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2)J-k FLp- top www.Notesfree.in
3) D Fp-flop
T Pp-fop
 www.Notesfree.in

) SR Elp-flop
S-R Latch
Similar v
enable ik voplaod by
clo ck palse (eL
stynal
and uipuk ae Callod Synchonous npals
The S
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F Plops output ony om

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clock pulse.
J e s m bol
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CLR
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tes
R
Puncuom Table
No

Stai
CL S R No chag
Rasek

O
Set
O
w.

Dndteaminal

amd output waweforms

ww

Input
CLK L 3 L

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D www.Notesfree.in
FAp. lop
we
tuoe latcho and
lakches Gnd an u v a e
Consunead w
x

D D
D latch D latch
(masa s lave)

n
CL

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the nas le
The ust Aatch is callacl
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U

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The
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Output a
fre
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Samplos he
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clock tnva ter

s'
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i
enabled and oultput
he Jatch is
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No

beeause CLk 0
masi latch dia blad
TThe
he
Aeve,
ls tfe Log1èl
Clk
w h e n the thbput puse ehanges
D urput is ansfeaied
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the dala
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as **a elock Jumauin

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ww

uh the Rvel
Cam
Cam charqe only
chage ny Auming
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teop
*The output the i p - om o
clock
Rasion d the
the Grap Stm bot

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 www.Notesfree.in
Co nsliuction o an edge-Ji9getad p-bop wne
Three SR Latches

.in
eLK
R
-

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sfr and
extean al
heexternal
the D (dala ))
D (Jata
Two latches aespond
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CLR (clock)
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te
tre
paovdes
he output ob
+Thiid lateh
No

CL 0
logtè lavel di psent
Btalc
amasn h
t
The output
w.

D 0 , eLk=

9oes T Res at s tate

AA3et s tale
ww

*Fup-ftop

CLk=
to
S chamqes s t state
p-1top goes t

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 www.Notesfree.in
ckocK chthe
x Whan he put posi ti've-adae
tiggesm
up-op maks a
posi tve iansi b on

thie Yalue D isiansferied to

A nagabve iansi.hon oom 1 to o dos not abfad
the output

chavackeai tue Tabe

n
Dattt1)

e.i
Raset
Set

elbck perod al
Qltt) hext stati
fre ome

charactatts ie EAuaion
tes
Q t t i ) = D|

ioit)
i t bebe eaual
eaual
t h e output
The noxt stati tat.
No

D Tha reent
the Yalue chput
D flip- fiop
Grapue Symbolor Edge-Tigered
w.

(a Pesibve -adqe_ b Nagatve- edga

ww

ansuuelicb
*Mest econemica) nd anE fip- p
The rdge tiiggered -ftop
numbe
- t A q uues the gmallest
p . fops ean e Cons kuslid by uing th
ohr pe www.Notesfree.in
p - o p md Cxheanal ogeè
www.Notesfree.in
3 - Fp- floP
J a c k ktby .
and k (Auset)
*Too thpulz Jtset)
Thvea opeaaions Grap Are Symbot
Set it 6
Aeet t to o
) C

tha outpus
i)eomplament

.in
Ciuut diagnam
coia D tp-top
amd qals
consludzd

ee
sfr
.

D
J
te

D-
No

Table
characteúie

J altt)
w.

No change
oQt)
Rase
Set
ww

Complament

characteats i e _FAuabonM

t+1) Ja'tk'a

D Jo'+k'

www.Notesfree.in
 www.Notesfree.in
=1, k =0
clock sels the output të r
The nert edge

*Jurput oli
the p-ttop to

J-0, =
edge Acsei
the output t o

*nex clock

.in
Aseli it ts o
xkunput

ee
J-k
clock adge tompluentz e Output
The next
sfr
elock edgeeaves the output
Cunehanged
The
te
No

4) TFA -flop up-fRop

Fp-Rop
fp-top, Complementeng
Togg
J- Flp-top
w.

Usi ng twhen ripuli

obtaunid rom a Jk p - fop Croaphuc Symbel

k ae lied together
and
ww

T
T
outpat
the
does not change
a
clock edge

J =
he output
a clwck edge Compementi
CocaneS
Appiauehu for dusiqu ng bihay
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 Using
www.Notesfree.in D
shp-ep
TEAp- ttop Cann be Constuclect wih a a ttip-p
am d an exclusive OR a t

CLLit dàgiam

D
T

n
e.i
Sym bet
Crapkue fre
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eharaeheislie Ta ble
No

T@tt+)
No change
w.

Q't) Cemmplement
ww

Charaeters ie Equaion

T a/ Ta+Ta
Q ttt) =

No change th Output

The output Complemen www.Notesfree.in

 B.3
www.Notesfree.in Analysus clockod Sequonial Cucui
given e u u t witl do undor catan operah
Anals u dosu be3 what a
clocked A equenual euaut ia lCond bors
The behavioY a
and Fe 3ta
datemaned om tha anpakthe outpui,
bib up ap
and the next sta aAu bo th a urneti on
The output
2tate
theeiput ond the pAosent

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Anass
obtaining a
to ble or a iagam fer
Consis is ts and inteanal
tha m e equene anpulh, outpub

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tatis.
Statt Fquation
sfr
Stat Tabe

Státi Diagaam
te
Example2
No

A
w.
ww

D- 1D
B

e'

CK

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www.Notesfree.in
Step
Stat Eq,uahons
the next state as a unct on tho
* 8 pecu
PALsent stati and ui puk
D f-lops A, B
h put
output

n
e.i
Alt+) At)x()+ Bt) x(t)
18() Ax( E)

y)
fre
AE)++BE)x'()
lali
t>next Stat of the flp-top one clock adge
tes
tha Booaan expes Ns ow

A l the Yan a bles

th pAsentstai.
LAn tion
No

ACt+1) Ax+ Bx
Bt+) Atcx)

y A+ B) '
w.

Stap bon Tablu

Sta Ta ble / Taansi
ww

and
ime Sequentw hpui, outpal3
The enumea ëd un a
Can bee
tup-top atals

Btae ka ble
Conuis4 - Seclions
T h e table
)Prexent stat
i) viput
1) next 8ta
v Cutput.
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www.Notesfree.in
Present Ata states t p - ops nod B at ony
iven ui me t
tnput a value or eoch possi bla present Atala
elocdo
naxtAtah 8tali 4 th p tops one
cyele
Ja l al ume t+

at me or eack preent a tali

output
Yallue y
amd unput Conuon

n
e.i
Present Stati Tnp ut Next Stata Output
AB

e O
sfr
O

O
te

O
No

O
w.

3 rat
Combunabona oh Present
isbng
isbng binary all
bin a
amd npuls
ww

dalrermened yom ogec

state Yalus cuu
NexE

the staa eualions

d agram o foom
AlttH)= Ax+Bx
BEHI) = A'x

Au'+ Bx'

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euncdFom ih Sta Table
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in fip-tops
=
nunpub

Phesent Staiz Next Stai u t pu

L>0 X=
A B AB
AB

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O

ee
8tate Diagnanm
+The informafhon avai lable tn astate tabk can be

represen nd
sfr
graphicaly h tha fe7m a

ucla
stati doqar

vepresen lid by a
A 8 tale is
beliwen states ax ndialzd by
taansibons
the
te
he ui lo»
duiaclid unes Connecung

ol
No

(oo
o
w.

i d a n t u s tha
the
eule identhus
nside each
ww

number
*The btnasy
8tati oth ip-ops
labelad wt too bunay numbas
The Auecädunes ase
Beparalkd alash.
labeled
nput yalue during the present 3talte
s
the numba ahter he s l a s aives the output
8 t a . wi the given úput
dui ng he present www.Notesfree.in
 www.Notesfree.in
*The 8ta diaqram ives a pickeral vo tat

hansi tions
-more 8 u tabe o human tntepretation
the cuiuut operat'on

Output Equaboms
ciuit That genct e s
The paat h e Combinaional
exteanal outputs is deseibed alge braically by

n
a Bet Boolean Kune oms Called output Aab ons

e.i
Pnput E9uab
he paat th CuLct
fre That aeneaates t thput
is bed alge braially by a set
tip-tleps dascai
Boolaan funct'ons ealled the - f lop arnput
equatons (ex itab'on equations)
tes

Da
No

name tha hip tep

Pa
DA A z +
w.

D A'z

A+8)
ww

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a)www.Notesfree.in
Analysis wh D pip-ops

Inpat eauation DA
DA =A O Oy
w5 Output A
D tp-ttopP .

No autput equahons a e given

.in
gtep
diaqram

CK
f ree A
tes
StatTable
Step
tip-tepA
the psent Atai fea
No

ona colu m n
ton
hwo anpals
umnsoa
.
htthe
w o
co taa
r e x E s t a l a

A
column for tha
one
w.

Next S t a i

Present Stah npus

A
A
ww

o
O
O
.

www.Notesfree.in
 Next Blate
www.Notesfree.in Vaus a o bt aunod em tha state

eauaion
ACt 41) A O* Oy
eualon.
Stali equalion u th Aama a tK inpu
Stp 8 Stale Diaqsam

00,

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ol, 1o

The uicuut has orne up-top and tuoo 8 ra o,

ee
naadad be couse
beease
Aslash en.tha uuuctid i na notnet
Cuiuit
com bunalioral
output om
a
h a is no
sfr
J FUp- Flops
b) Anals is wi6
a x t stato Vauus,
l o obt aun te
te
table o
chaaac teis té
ehea
COes ponding
chanackels
ic equakon .
No

e uit hat
iol
i)Psouedue yaluea o a Beauen
-8tab cam

The next o TT Ppe

ype Can
uch as

ses p-4tops
w.

oadure
be dived snahi o llotoing teams
ah
aquaion
Dekermine th up-ttop anput Yaniables
.
8tati and put
ww

tprsent equaton
ah put
each
hat "tk bhay yalues e
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2.
-tlop t tabe
tabe.
corvesponurg s
8t at t
ta
3 . Use the valuas
Valuias
tha
Tha
the rnaxt 8tati
cakenrune
o

Exampla A and B
JK phtops
wo

*One put e

no outpuz www.Notesfree.in
 www.Notesfree.in
Sequential
Cuau wits J Fip- Flep

in
fr ee. B
tes

CLK
No

Soln

gkeP FAup lep npub

euaioms
w.

= B KA B
+A A
Ka A '
ww

CAayactenshe

Step2:
i s k ,

Stati Tabl
Vext Statt Fp-Flep Inpak
Preent Stati Input
JA KA
D

O
O
O
O www.Notesfree.in
o
 Values
NeXt Sfale v as
7 sna eharacheistic Tablo
JA a
www.Notesfree.in
eYa lualid wing upu eauaiom

Next Sa - evaluad uing chayacte1.8 the Table

J K Nextstab
A JA B
B J B , KB
'

n
NexE Stat valuas uing 8tata Equauon
Can ke btaned alo by
by

e.i
8tak yalis
Tharaxt charaeeriste
eyauabng tha Atate eqjuatons rom the

euab on
fre
Proodue
t lams
Deteamuine u - t o p input equalions
tho
tes
Yauables
amd unput
btha preent s tati
Subshbii the unput n s nb the p - op
eh anaete isic eg,uuaion to ebtaun th Btati equalion
No

3.Use the Cere3 ponding state 2qualions to ateamine the

Taxt Atati values tn ha state tabla

Xmp Input eeuab on

w.

StepT
Step Stall ea,uahoms
Jk f/F QlEt) =Ja+ka
chaoackerk be eauaton er
ww

Altt) JA'+ K'A

B(ED = J8'+K'B
ons i &hanackeus he q
Subsihute the nput aqua JA B
KA Bx

AlE) =
Ja' +K A
Kg A
= BA'+(Bx)'A
= BA' +(B-+2A
BA'B'A+RA
Alt+D A'BAB' +Az www.Notesfree.in
 www.Notesfree.in
BlE+)= B k B
x'B (N®x)B
B'x Ax +A xB

n
B'x'+ ABx +A'BX

e.i
BCt+)

Step3: Stat Taba

fre
Previous Table

Step 4 StatDiagzam
es
ot
r o outpul
O
So (S
N

O
w.
ww

www.Notesfree.in
 www.Notesfree.in
)Analyks witT Fp -plops:
Same
Example

D D

n
e.i
fre
tes
clk
No

ckck e 3 e t

Soln TFp-8lops A,B

Two
w.

input
output }
equalion
am output
ww

e9ualions
gtep Dnput
A = Bz

B
AB

9tat Table
Step 2 next Stai , oukput
Preent Stale, input he
can be deuved om
Vales toa tha next &talis
www.Notesfree.in
stale equatns
 -Bukbhit
www.Notesfree.in T and T n chaeat teris bc
euahonm.
Qlt+)-TO
Alt +)= 'A A TaTQ
(B)A+ (8x)'A
=

A'Bx + (B+) A
ACttt) A'BX + AB+Ax
Blt+D TeB

n
B(tH)= x®B

e.i
8tat Table a Beauan tal
fre Cucut w T Plp-feps

Present State Pnput Next Stat Output

A B
AB
tes

O
No

O
O
O

O
w.

Step 8 : SEatëDiaram
ww

Ki
ofp dupenes an
Present 8ali ny
dupen dunt e i/p
PrexentSlalk/outpot

(1olo)
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 www.Notesfree.in
Mealy and Mooe Models Fn Stati Maclunes

aiui
lwe models o Seq uen bial
i) Mealy model

it) MocYe Modal

T h dije omly
th tha cothe output
eneaid

.in
i) Mealy Model :

u a unction bolh t preent3ta

Th output

e
md the i p u t fre
Block diagam
Output
Srp Next Stat Sta Combinatioralt Oulpu
tes
Combnabonal Pagä CM ealy 1yr)
A Legc
eleck
No

and h
amdhu
x
b el5
bo thput
l thput
ua uneiom
Outp at B
Omd
w.

A
Present &tatt Circuts -

iadg
is d) l o ckad Seqsen ba
Anals
/o
ww

olo (16)
(oOK
lo
o

Tha outpu may chan9 the arpus ehange duing

*The outpat the Yale that à present immediately

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 www.Notesfree.in
it) MocYe Modol
Tha outp ut s a
Tunchan eny hu present atai
BAo ck Diogram

Inpul Next &tot Sta Cutpul

ombnotoral outpol
Combinabioa Pgil (1McaN
LEc
logc TA tyP)

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Cuck

e
E wit
fre Jk Fp.tps
Cndul duagnn
Analisi
h present Btalk only
a fundbion
tes
Output u

O
So
No

ayncho 4 2d
w.

wauit. aa

The Outpui ha 6eauanüal

with t h elock
on +p-ttop outpulz
tha dapend on
ww

-becouse
w5the elok
a ynchorizad
that

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 www.Notesfree.in
3 . 4 S t a Racducion and Assianment

Simpby a
dugn b educing tha numbe ob aal
and ptops it ses

-ops vecducos tte cost

the numbez b
Radueing
a cCuit.

State Rduckon

n
The Aeduetiom unthe number ) p-tops a
the 2tati-yeduueion

e.i
eenbal c i u i t i ueed s

PAoblam.
Stale Reduchon Atgetthm fre ralis in aa

ocaduresoaAaducang
te um bea 4
external nput-outpat
Stati table whle Ka2pung tha
Aoqemena unehanged.
tes
produta. 2 stalis
tops a h2
m h a numbe s r a l s may result
Anduckon
No

Teducion t-ttops
Kampl Stati diagarm
w.

olo
olo
(a
ww

|o
ole

Trpt Beuern 0101o1l0100,

r i tial Stale : a www.Notesfree.in
 1 ind he complal
Stepwww.Notesfree.in Seqence
*Hach chput c7 | pr0ducus an output or
t tRa next 3tak
ha uiuut 6 qo
ccu

Stati e f fa f 3a
b d
O
Cnput
O
output
tha next Column

.in
next 8tah wuten ah the Dp
Th

u m bel Stalis
Ra uw he
Step
StatiTable

Obeain
f ree
direetty om

Next state
tk Brau diagra

Output
tes
Present Stati 0 X=
XoX=1|

b
No

3
w.

d
ww

8tali aa saud b be aqui valnt

+Two
the s e t b npculs ThH qive
-pr eoch mombex Bend the uicut
amd
exaetuth 2ame cutput
to am 2qui vaunt Atati
8 a m e 3tati
on
e Fe to the

ae equivalunt
3fales
*When tuo emeed
C TRoct
cu altei9
Thecut alteing
tham Can be
-One b
Hput-Output yelaionshups

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 www.Notesfree.in

Stals e amd ave equi valent

Bet to alis a t
outpub o 4

Btot Table
the
Recluung

Next Stat Output

Yresent St a
b

n
O

e.i
a

e
e
b
e eqi valant
sfr w i t A tAa
Ramove9sta amd repiace

Btab e
d ave eauivalent
ote
Cmd
i)Stal d
Can be Aamoved Omd raplacad by
Bta
Reducad 8 t a t Table
.N

Next Sraë utput

Present Sta =}

a
w

O
ww

2
a
e

Co ony 5 stal
RaducodSta diaqam
sLep
olc olo

oo
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 www.Notesfree.in
Step 4 t- nput sequon co

Stati C d e d d e dea

Input
Output
Same as h cngina

.in
tb ve
he umbe stalis m ven
Radu ead

ree
Stati Assignment
Asgn uniqu Coded
buary Values to t h 2tali
iaut wn mtalis, t h cod
f
Contain n bi 2"m
tes
3 bils>*staks m co
8raes
3tep A ssign bunay Yauss
No

yar
AUse bnary CAunten
ainmenl
USe one -fhet aignmen L
w.

Thre buhay Stat Asgnments

Veni blw

ALcignmernt Aaskaomnt 2. Assianment 3

Oyu hot
gtati G y a y ocla
ww

O0100

o)000

whun
ode Only mu bt tn the cod g9oup hange
um beà fo tha nxt.

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ono-hot assign ment oneone bit
www.Notesfree.in equal toi
uses CYe ttp-ttep Per 3tat
One- het entodin9 Jads to simple daeedn9 logrc
er the naxt atata and otput
than machuies
l

n
xone-het ma chines Coun be
wth3e9enlial bunaj encoding

e.i
Rdutd StateTable t5 BTUy Asignmant

fre
Next Stai Outpu

Pirasen Stat
t =o
es =|
No

o11
w.
ww

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 www.Notesfree.in

3.5 DESIGN PROCEDURE

• Design procedures or methodologies specify hardware that will implement a desired
behavior.
• The design effort for small circuits may be manual, but industry relies on automated
synthesis tools for designing massive integrated circuits.
• The sequential functionality that is to be implemented by the synthesis tool.
• Illustrate manual methods using D, JK, and T flip-flops.

✔ The design of a clocked sequential circuit starts from a set of specifications and culminates
in a logic diagram or a list of Boolean functions from which the logic diagram can be

.in
obtained.
➔ The first step in the design of sequential circuits is to obtain a state table or an
equivalent representation, such as a state diagram.
➔ A synchronous sequential circuit is made up of flip-flops and combinational gates.
➔ The design of the circuit consists of choosing the flip-flops and then finding a

e
combinational gate structure that, together with the flip-flops, produces a circuit which
fulfills the stated specifications.
fre
➔ The number of flip-flops is determined from the number of states needed in the circuit
and the choice of state assignment codes
➔ Once the type and number of flip-flops are determined, the design process involves a
transformation from a sequential circuit problem into a combinational circuit problem.
tes
The procedure for designing synchronous sequential circuits can be summarized by
a list of recommended steps:
1. From the word description and specifications of the desired operation, derive a state
diagram for the circuit.
No

2. Reduce the number of states if necessary.

3. Assign binary values to the states.
4. Obtain the binary-coded state table.
5. Choose the type of flip-flops to be used.
6. Derive the simplified flip-flop input equations and output equations.
w.

7. Draw the logic diagram.

a) Synthesis Using D Flip-Flops

Example:
ww

• To design a circuit that detects a sequence of three or more consecutive 1’s in a string of bits
coming through an input line
Step 1: State diagram for sequence detector

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 www.Notesfree.in

•
Starting with state S0, the reset state.
•
If the input is 0, the circuit stays in S0,
•
If the input is 1, it goes to state S1 to indicate that a 1 was detected.
•
If the next input is 1, the change is to state S2 to indicate the arrival of two
consecutive 1’s,
• If the input is 0, the state goes back to S0.
• The third consecutive 1 sends the circuit to state S3.
• If more 1’s are detected, the circuit stays in S3.
• Any 0 input sends the circuit back to S0.
✔ In this way, the circuit stays in S3 as long as there are three or more consecutive 1’s

.in
received.
✔ This is a Moore model sequential circuit, since the output is 1 when the circuit is in state S3
and is 0 otherwise.

Step 2:

e
a) Synthesis Using D Flip-Flops

•
fre
Assign binary codes to the states and list the state table.
tes
No

Step 3:
• Choose two D flip-flops to represent the four states,
• Label their outputs A and B.
w.

• one input x
• one output y.
✔ The characteristic equation of the D flip-flop is Q(t + 1) = DQ
➔ the next-state values in the state table specify the D input condition for the flip-flop.
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✔ The flip-flop input equations can be obtained directly from the next-state columns of A and
B and expressed in sum-of-minterms form as

A, B - present-state values of flip-flops A and B,

x – input
DA, DB -input equations.
y - output
• The minterms for output y are obtained from the output column in the state table.

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Step 4:
K-Maps for sequence detector

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• The Boolean equations are simplified by means of the maps
• The simplified equations are

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Step 5:
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Logic diagram of a Moore-type sequence detector
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No
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Excitation Tables

• D-type flip-flops
◦ The input equations are obtained directly from the next state.
• JK and T types of flip-flops
◦ In order to determine the input equations for these flip-flops, it is necessary to derive a
functional relationship between the state table and the input equations.

Excitation Table for J-K Flip-flop:

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✔ There are four possible transitions from the present state to the next state.

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✔ The required input conditions for each of the four transitions are derived from the
information available in the characteristic table.

matter whether the input is 1 or 0.

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✔ The symbol X in the tables represents a don’t-care condition, which means that it does not

✔ When both present state and next state are 0, the J input must remain at 0 and the K input
can be either 0 or 1.
✔ Similarly, when both present state and next state are 1, the K input must remain at 0, while
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the J input can be 0 or 1.
✔ If the flip-flop is to have a transition from the 0-state to the 1-state, J must be equal to 1,
since the J input sets the flip-flop.
✔ Input K may be either 0 or 1. If K = 0, the J = 1 condition sets the flip-flop as required;
No

✔ If K = 1 and J = 1, the flip-flop is complemented and goes from the 0-state to the 1-state as
required.
✔ Therefore, the K input is marked with a don’t-care condition for the 0-to-1 transition.
✔ For a transition from the 1-state to the 0-state, we must have K = 1, since the K input clears
the flip-flop. However, the J input may be either 0 or 1, since J = 0 has no effect and J = 1
w.

together with K = 1 complements the flip-flop with a resultant transition from the 1-state to
the 0-state.

Excitation table for the T flip-flop:

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• From the characteristic table,

• when input T = 1, the state of the flip-flop is complemented, and
• when T = 0, the state of the flip-flop remains unchanged.
✔ when the state of the flip-flop must remain the same, the requirement is that T = 0.
✔ When the state of the flip-flop has to be complemented, T must equal 1.

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b) Synthesis Using JK Flip-Flops

Example:

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Step 1:
Maps for J and K input equations

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No

Step 2:
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Logic diagram for sequential circuit with JK flip-flops

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c) Synthesis Using T Flip-Flops

Example:
• Designing a binary counter.
• An n -bit binary counter consists of n flip-flops that can count in binary from 0 to 2n – 1.

State Diagram

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✔ Binary states indicated inside the circles,
✔ The flip-flop outputs repeat the binary count sequence with a return to 000 after 111.
✔ The directed lines between circles are not marked with input and output values as in other
state diagrams.
✔ State transitions in clocked sequential circuits are initiated by a clock edge;
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✔ the flip-flops remain in their present states if no clock is applied.
✔ The only input to the circuit is the clock, and the outputs are specified by the present state
of the flip-flops.
✔ The next state of a counter depends entirely on its present state, and the state transition
occurs every time the clock goes through a transition.
No

Step 1:
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• The three flip-flops are symbolized by A2, A1, and A0.

• Binary counters are constructed most efficiently with T flip-flops because of their
complement property. The flip-

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Step 2:
Maps for three-bit binary counter

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Step 3:
Logic diagram of three-bit binary counter

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No
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3.6 Registers and Counters

✔ Registers
✔ Shift Registers

• A clocked sequential circuit consists of a group of flip‐flops and combinational gates.

• Circuits that include flip‐flops are usually classified by the function they perform
• Two such circuits are
◦ registers and
◦ counters.
 A register is a group of flip‐flops, each one of which shares a common clock and is capable

.in
of storing one bit of information.
 An n‐bit register consists of a group of n flip‐flops capable of storing n bits of binary
information.
 In addition to the flip‐flops, a register may have combinational gates that perform certain
data‐processing tasks.

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 The flip‐flops hold the binary information, and the gates determine how the information is
transferred into the register.
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Four‐bit register
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No
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• The common clock input triggers all flip‐flops on the positive edge of each pulse, and the
binary data available at the four inputs are transferred into the register.
• The value of ( I3,I2,I1,I0) immediately before the clock edge determines the value of (A3, A2 ,
A1 , A0 ) after the clock edge.
• The four outputs can be sampled at any time to obtain the binary information stored in the
register.
• The input Clear_b goes to the active‐low R (reset) input of all four flip‐flops.
• When this input goes to 0, all flip‐flops are reset asynchronously.
• The Clear_b input is useful for clearing the register to all 0’s prior to its clocked operation.
• The R inputs must be maintained at logic 1 (i.e., de-asserted) during normal clocked

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operation

Register with Parallel Load

 Registers with parallel load are a fundamental building block in digital systems.
 Synchronous digital systems have a master clock generator that supplies a continuous train

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of clock pulses.
 The pulses are applied to all flip‐flops and registers in the system.
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 The master clock acts like a drum that supplies a constant beat to all parts of the system.
 A separate control signal must be used to decide which register operation will execute at
each clock pulse.
 The transfer of new information into a register is referred to as loading or updating the
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register.
 If all the bits of the register are loaded simultaneously with a common clock pulse, then
loading is done in parallel.
 A clock edge applied to the C inputs of the register, load all four inputs in parallel.
 To fully synchronize the system, ensure that all clock pulses arrive at the same time
No

anywhere in the system, so that all flip‐flops trigger simultaneously.

Four‐bit register with parallel load

• A four‐bit data‐storage register with a load control input that is directed through gates and
into the D inputs of the flip‐flops
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• The additional gates implement a two‐channel mux whose output drives the input to the
register with either the data bus or the output of the register.
• The load input to the register determines the action to be taken with each clock pulse.
◦ When the load input is 1, the data at the four external inputs are transferred into the
register with the next positive edge of the clock.
◦ When the load input is 0, the outputs of the flip‐flops are connected to their respective
inputs.
• The feedback connection from output to input is necessary because a D flip‐flop does not
have a “no change” condition.
• With each clock edge, the D input determines the next state of the register.

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• To leave the output unchanged, it is necessary to make the D input equal to the present
value of the output
• The transfer of information from the data inputs or the outputs of the register is done
simultaneously with all four bits in response to a clock edge.

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SHIFT REGISTERS

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➔ A register capable of shifting the binary information held in each cell to its neighboring cell,
in a selected direction, is called a shift register.
➔ The logical configuration of a shift register consists of a chain of flip‐flops in cascade, with
the output of one flip‐flop connected to the input of the next flip‐flop.
➔ All flip‐flops receive common clock pulses, which activate the shift of data from one stage
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to the next. The simplest possible shift register is one that uses only flip‐flops

Four‐bit shift register

No
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• The output of a given flip‐flop is connected to the D input of the flip‐flop at its right.
• This shift register is unidirectional (left‐to‐right).
• Each clock pulse shifts the contents of the register one bit position to the right.
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• The configuration does not support a left shift.

◦ The serial input determines what goes into the leftmost flip‐flop during the shift.
◦ The serial output is taken from the output of the rightmost flip‐flop the clock’s signal
can be suppressed by gating the clock signal to prevent the register from shifting.

a) Serial Transfer:
• The datapath of a digital system is said to operate in serial mode when information is
transferred and manipulated one bit at a time.
• Information is transferred one bit at a time by shifting the bits out of the source register and
into the destination register.
• parallel transfer - all the bits of the register are transferred at the same time.

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• The serial transfer of information from register A to register B is done with shift registers,
Serial transfer from register A to register B

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• The serial output ( SO ) of register A is connected to the serial input ( SI ) of register B.
• To prevent the loss of information stored in the source register, the information in register A
is made to circulate by connecting the serial output to its serial input.
• The initial content of register B is shifted out through its serial output and is lost unless it is

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transferred to a third shift register.
• The shift control input determines when and how many times the registers are shifted.
•

•
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an AND gate that allows clock pulses to pass into the CLK terminals only when the shift
control is active the shift registers have four bits each.
Then the control unit that supervises the transfer of data must be designed in such a way
that it enables the shift registers, through the shift control signal, for a fixed time of four
clock pulses in order to pass an entire word
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Timing diagram
No

✔ The shift control signal is synchronized with the clock and changes value just after the
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negative edge of the clock.

✔ The next four clock pulses find the shift control signal in the active state, so the output of
the AND gate connected to the CLK inputs produces four pulses: T1, T2, T3, and T4.
✔ Each rising edge of the pulse causes a shift in both registers.
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✔ The fourth pulse changes the shift control to 0, and the shift registers are disabled.
Example:
• The binary content of A before the shift is 1011 and that of B is 0010.
 The serial transfer from A to B occurs in four steps

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➔ With the first pulse, T1, the rightmost bit of A is shifted into the leftmost bit of B and is also
circulated into the leftmost position of A.
➔ At the same time, all bits of A and B are shifted one position to the right.
➔ The previous serial output from B in the rightmost position is lost, and its value changes
from 0 to 1.
➔ The next three pulses perform identical operations, shifting the bits of A into B, one at a
time.
➔ After the fourth shift, the shift control goes to 0, and registers A and B both have the value
1011.
➔ The contents of A are copied into B, so that the contents of A remain unchanged i.e., the

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contents of A are restored to their original value.

➢ In the parallel mode, information is available from all bits of a register and all bits can be
transferred simultaneously during one clock pulse.
➢ In the serial mode, the registers have a single serial input and a single serial output.

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➢ The information is transferred one bit at a time while the registers are shifted in the same
direction.

b) Serial Addition:
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• The two binary numbers to be added serially are stored in two shift registers.
• Beginning with the least significant pair of bits, the circuit adds one pair at a time through a
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single full‐adder (FA) circuit
No
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• The carry out of the full adder is transferred to a D flip‐flop, the output of which is then
used as the carry input for the next pair of significant bits.
• The sum bit from the S output of the full adder could be transferred into a third shift
register.
• By shifting the sum into A while the bits of A are shifted out, it is possible to use one
register for storing both the augend and the sum bits.

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• The serial input of register B can be used to transfer a new binary number while the addend
bits are shifted out during the addition.
➔ The operation of the serial adder is as follows:
◦ Initially, register A holds the augend, register B holds the addend, and the carry flip‐flop
is cleared to 0.
◦ The outputs (SO) of A and B provide a pair of significant bits for the full adder at x and
y.
◦ Output Q of the flip‐flop provides the input carry at z.

• The shift control enables both registers and the carry flip‐flop, so at the next clock pulse,

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both registers are shifted once to the right, the sum bit from S enters the leftmost flip‐flop
of A, and the output carry is transferred into flip‐flop Q.
• The shift control enables the registers for a number of clock pulses equal to the number of
bits in the registers.
• For each succeeding clock pulse, a new sum bit is transferred to A, a new carry is

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transferred to Q, and both registers are shifted once to the right.
•
•
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This process continues until the shift control is disabled.
The addition is accomplished by passing each pair of bits together with the previous carry
through a single full‐adder circuit and transferring the sum, one bit at a time, into register
A.
• Initially, register A and the carry flip‐flop are cleared to 0, and then the first number is
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added from B.
• While B is shifted through the full adder, a second number is transferred to it through its
serial input.
• The second number is then added to the contents of register A , while a third number is
transferred serially into register B.
No

• This can be repeated to perform the addition of two, three, or more four‐bit numbers and
accumulate their sum in register A.

✔ The parallel adder uses registers with a parallel load, whereas the serial adder uses shift
registers.
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✔ The number of full‐adder circuits in the parallel adder is equal to the number of bits in the
binary numbers, whereas the serial adder requires only one full‐adder circuit and a carry
flip‐flop.
✔ Excluding the registers, the parallel adder is a combinational circuit, whereas the serial
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adder is a sequential circuit which consists of a full adder and a flip‐flop that stores the
output carry.
The state table that specifies the sequential circuit

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• The present state of Q is the present value of the carry.

• The present carry in Q is added together with inputs x and y to produce the sum bit in
output S.
• The next state of Q is equal to the output carry.
• If a D flip‐flop is used for Q, the circuit reduces to the one

➔ If a JK flipflop is used for Q, it is necessary to determine the values of inputs J and K by

referring to the excitation table
➔ The two flip‐flop input equations and the output equation can be simplified by means of
maps to

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Second form of serial adder

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No

c) Universal Shift Register:

• If the flip‐flop outputs of a shift register are accessible, then information entered serially by
shifting can be taken out in parallel from the outputs of the flip‐flops.
• If a parallel load capability is added to a shift register, then data entered in parallel can be
taken out in serial fashion by shifting the data stored in the register.
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• Some shift registers provide the necessary input and output terminals for parallel transfer.

• Shift register has the following capabilities:

1. A clear control to clear the register to 0.
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2. A clock input to synchronize the operations.

3. A shift‐right control to enable the shift‐right operation and the serial input and
output lines associated with the shift right.
4. A shift‐left control to enable the shift‐left operation and the serial input and output
lines associated with the shift left.
5. A parallel‐load control to enable a parallel transfer and the n input lines associated
with the parallel transfer.
6. n parallel output lines.
7. A control state that leaves the information in the register unchanged in response to
the clock. Other shift registers may have only some of the preceding functions, with
at least one shift operation.

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 A register capable of shifting in one direction only is a unidirectional shift register.

 One that can shift in both directions is a bidirectional shift register.
 If the register has both shifts and parallel‐load capabilities, it is referred to as a universal
shift register.
The block diagram symbol and the circuit diagram of a four‐bit universal shift register
that has all the capabilities

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Function Table for the Register

No
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➔ When s1s0 = 01, terminal 1 of the multiplexer inputs has a path to the D inputs of the flip‐
flops. This causes a shift‐right operation, with the serial input transferred into flip‐flop A3.
➔ When s1s0 = 10, a shift‐left operation results, with the other serial input going into flip‐flop
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A0.
➔ Finally, when s1s0 = 11, the binary information on the parallel input lines is transferred into
the register simultaneously during the next clock edge.

• It is more economical to use a single line and transmit the information serially, one bit at a
time.
• The transmitter accepts the n ‐bit data in parallel into a shift register and then transmits the
data serially along the common line.
• The receiver accepts the data serially into a shift register.
• When all n bits are received, they can be taken from the outputs of the register in parallel.

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• The transmitter performs a parallel‐to‐serial conversion of data and the receiver does a
serial‐to‐parallel conversion.

d) Types of Shift Register:

i. Serial in/Serial out (SISO)
ii. Serial in/Parallel out (SIPO)
iii. Parallel in/Serial out (PISO)
iv. Parallel in/Parallel out (PIPO)

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i) Serial-In–-Serial-Out Shift Register:

No

Shift-right Register:
using D flip-flops, using J-K fl ip-fl ops
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Operation of the Shift-right Register:

1. To shift a 1 into the flip-flop, J = 1 and K = 0,
2. To shift a 0 into the flip-flop, J = 0 and K = 1.

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Example: The entry of the four bits 1010 into the register - Illustration

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No
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No

Shift-left Register
(a) using D flip-flops, (b) using J-K flip-flops
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Operation of the Shift-left Register

ii) Serial-In–Parallel-Out Register:

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• Data bits are entered into the register in the same as serial-in serial-out shift register.
• But the output is taken in parallel.
• Once the data are stored, each bit appears on its respective output line and all bits are
available simultaneously instead of on a bit-by-bit.

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No
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8-bit shift register – Logic Diagram fre
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No

iii) Parallel-In–Serial-Out Register:

• the bits are entered in parallel i.e., simultaneously into their respective stages on parallel
lines.
• There are four data input lines, X0, X1, X2 and X3 for entering data in parallel into the
register.
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• SHIFT/ LOAD input is the control input, which allows four bits of data to load in parallel
into the register.
• When SHIFT/LOAD is LOW, gates G1, G2, G3 and G4 are enabled, allowing each data bit
to be applied to the D input of its respective Flip-Flop.
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• When a clock pulse is applied, the Flip-Flops with D = 1 will set and those with D = 0 will
reset, thereby storing all four bits simultaneously.

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• When SHIFT/LOAD is HIGH, gates G1, G2, G3 and G4 are disabled and gates G5, G6 and

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G7 are enabled, allowing the data bits to shift right from one stage to the next.
• The OR gates allow either the normal shifting operation or the parallel data-entry operation,
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depending on which AND gates are enabled by the level on the SHIFT/LOAD input.

iv) Parallel-In–Parallel-Out Register:

• In this type, there is simultaneous entry of all data bits and the bits appear on parallel
outputs simultaneously.
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No
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Counters:

• A register that goes through a prescribed sequence of states upon the application of input
pulses is called a counter.
• A counter is essentially a register that goes through a predetermined sequence of binary
states.
• The input pulses may be clock pulses, or they may originate from some external source and
may occur at a fixed interval of time or at random.
• The sequence of states may follow the binary number sequence or any other sequence of
states.

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• The gates in the counter are connected in such a way as to produce the prescribed sequence
of states.

✗ Various types of registers are available commercially.

 The simplest register is one that consists of only flip‐flops, without any gates.

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 A counter that follows the binary number sequence is called a binary counter .
➔ An n ‐bit binary counter consists of n flip‐flops and can count in binary from 0
through 2n – 1.

Counters are available in two categories:

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1. Ripple counters (Asynchronous Counters)
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2. Synchronous counters.

1. Ripple counters:
• In a ripple counter, a flip‐flop output transition serves as a source for triggering other flip ‐
flops.
No

a) Binary Ripple Counter

• The count starts with binary 0 and increments by 1 with each count pulse input.
• After the count of 15, the counter goes back to 0 to repeat the count.
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Binary Count Sequence

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✔ A binary ripple counter consists of a series connection of complementing flip‐flops,

with the output of each flip‐flop connected to the C input of the next higher order flip ‐
flop.
✔ The flip‐flop holding the least significant bit receives the incoming count pulses

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✔ Every time that A0 goes from 1 to 0, it complements A1.

✔ Every time that A1 goes from 1 to 0, it complements A2.
✔ Every time that A2 goes from 1 to 0, it complements A3 and so on for any other higher
order bits of a ripple counter.

Four‐bit binary ripple counter

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No
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Example: The transition from count 0011 to 0100.

✔ A0 is complemented with the count pulse.

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✔ Since A0 goes from 1 to 0, it triggers A1 and complements it.

✔ As a result, A1 goes from 1 to 0, which in turn complements A2, changing it from 0 to
1.
✔ A2 does not trigger A3, because A2 produces a positive transition and the flip-flop
responds only to negative transitions.
✔ Thus, the count from 0011 to 0100 is achieved by changing the bits one at a time, so the
count goes from 0011 to 0010, then to 0000, and finally to 0100.
✔ The flip‐flops change one at a time in succession, and the signal propagates through the
counter in a ripple fashion from one stage to the next.

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• The output of each flip‐flop is connected to the C input of the next flip‐flop in sequence.
• The flip‐flop holding the least significant bit receives the incoming count pulses.
• The T inputs of all the flip‐flops in (a) are connected to a permanent logic 1, making each
flip-flop complement if the signal in its C input goes through a negative transition.
• The bubble in front of the dynamic indicator symbol next to C indicates that the flip ‐flops

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respond to the negative‐edge transition of the input.
The negative transition occurs when the output of the previous flip‐flop to which C is
•
connected goes from 1 to 0.

b) Binary countdown counter:

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• A binary counter with a reverse count is called a binary countdown counter .
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✔ In a countdown counter, the binary count is decremented by 1 with every input count pulse.
✔ The count of a four‐bit countdown counter starts from binary 15 and continues to binary
counts 14, 13, 12, . . . , 0 and then back to 15.
✔ A list of the count sequence of a binary countdown counter shows that the least significant
bit is complemented with every count pulse.
No

c) BCD Ripple Counter:

• A decimal counter follows a sequence of 10 states and returns to 0 after the count of 9.
• A counter must have at least four flip‐flops to represent each decimal digit, since a decimal
digit is represented by a binary code with at least four bits.
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• The sequence of states in a decimal counter is dictated by the binary code used to represent
a decimal digit.
State diagram of a decimal BCD counter
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• A decimal counter is similar to a binary counter, except that the state after 1001 (the code
for decimal digit 9) is 0000 (the code for decimal digit 0).

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The logic diagram of a BCD ripple counter using JK flip‐flops

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No
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• The four outputs are designated by the letter symbol Q, with a numeric subscript equal to
the binary weight of the corresponding bit in the BCD code.
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• The output of Q1 is applied to the C inputs of both Q2 and Q8 and the output of Q2 is
applied to the C input of Q4.
• The J and K inputs are connected either to a permanent 1 signal or to outputs of other flip‐
flops.
• Signals that affect the flip‐flop transition depend on the way they change from 1 to 0.
• The operation of the counter can when the C input goes from 1 to 0, the flip‐flop is
◦ set if J = 1
◦ cleared if K = 1,
◦ complemented if J = K = 1, and
◦ left unchanged if J = K = 0.

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d) Decade counter:
• The BCD counter is a decade counter
Block diagram of a three‐decade decimal BCD counter

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• Multiple decade counters can be constructed by connecting BCD counters in cascade, one
for each decade.
• The inputs to the second and third decades come from Q8 of the previous decade.

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• When Q8 in one decade goes from 1 to 0, it triggers the count for the next higher order
decade while its own decade goes from 9 to 0.
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No
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2. Synchronous Counters
• Clock pulses are applied to the inputs of all flip‐flops.
• A common clock triggers all flip‐flops simultaneously

a) Binary Counter:
• the flip‐flop in the least significant position is complemented with every pulse.
• A flip‐flop in any other position is complemented when all the bits in the lower significant
positions are equal to 1 .

Four‐bit synchronous binary counter

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No
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• The C inputs of all flip‐flops are connected to a common clock.

• The counter is enabled by Count_enable.
✔ If the enable input is 0, all J and K inputs are equal to 0 and the clock does not change the
state of the counter.

✗ The first stage, A0, has its J and K equal to 1 if the counter is enabled.
✗ The other J and K inputs are equal to 1 if all previous least significant stages are equal to 1
and the count is enabled.
✗ The chain of AND gates generates the required logic for the J and K inputs in each stage.

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• The counter can be extended to any number of stages, with each stage having an additional
flip‐flop and an AND gate that gives an output of 1 if all previous flip‐flop outputs are 1.
• The flip‐flops trigger on the positive edge of the clock.

b) Up–Down Binary Counter:

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• A synchronous countdown binary counter goes through the binary states in reverse order,

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from 1111 down to 0000 and back to 1111 to repeat the count.
• The bit in the least significant position is complemented with each pulse.
• A bit in any other position is complemented if all lower significant bits are equal to 0.
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• It has an up control input and a down control input.

◦ When the up input is 1,
▪ the circuit counts up, since the T inputs receive their signals from the values of the
previous normal outputs of the flip‐flops.
◦ When the down input is 1 and the up input is 0,
▪ the circuit counts down, since the complemented outputs of the previous flip‐flops
are applied to the T inputs
◦ When the up and down inputs are both 0,
▪ the circuit does not change state and remains in the same count.
◦ When the up and down inputs are both 1,

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▪ the circuit counts up.
• This set of conditions ensures that only one operation is performed at any given time.
• The up input has priority over the down input.

c) BCD Counter

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• A BCD counter counts in binary‐coded decimal from 0000 to 1001 and back to 0000.

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State table of a BCD counter
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• The input conditions for the T flip‐flops are obtained from the present‐ and next‐state
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conditions
• The flip‐flop input equations can be simplified by means of maps.
• The unused states for minterms 10 to 15 are taken as don’t‐care terms.
• The simplified functions are
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• The circuit can easily be drawn with four T flip‐flops, five AND gates, and one OR gate.
• Synchronous BCD counters can be cascaded to form a counter for decimal numbers of any
length.

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d) Binary Counter with Parallel Load:

• Counters employed in digital systems quite often require a parallel‐load capability for
transferring an initial binary number into the counter prior to the count operation.

Top‐level block diagram symbol

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The logic diagram of a four‐bit register

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• When equal to 1, the input load control disables the count operation and causes a transfer of
data from the four data inputs into the four flip‐flops.
• If both control inputs are 0, clock pulses do not change the state of the register.
• The carry output becomes a 1 if all the flip‐flops are equal to 1 while the count input is
enabled.
• This is the condition for complementing the flip‐flop that holds the next significant bit.
• The carry output is useful for expanding the counter to more than four bits

Function Table for the Counter

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✔ The four control inputs— Clear, CLK, Load, and Count —determine the next state.
✗ The Clear input is asynchronous and, when equal to 0, causes the counter to be cleared
regardless of the presence of clock pulses or other inputs.
✔ indicated in the table by the X entries, which symbolize don’t‐care conditions for
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the other inputs.
✗ The Clear input must be in the 1 state for all other operations.
✗ With the Load and Count inputs both at 0, the outputs do not change, even when clock
pulses are applied.
✗ A Load input of 1 causes a transfer from inputs I0 - I3 into the register during a positive
No

edge of CLK .
✔ The input data are loaded into the register regardless of the value of the Count input,
because the Count input is inhibited when the Load input is enabled.
✔ The Load input must be 0 for the Count input to control the operation of the counter.
✔ A counter with a parallel load can be used to generate any desired count sequence.
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Two ways to achieve a BCD counter using a counter with parallel load
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OTHER COUNTERS
• Counters can be designed to generate any desired sequence of states.
• Counters are used to generate timing signals to control the sequence of operations in a
digital system.
• Counters can also be constructed by means of shift registers

a) Divide‐by‐ N counter (Modulo‐ N counter)

• A divide‐by‐ N counter (also known as a modulo‐ N counter) is a counter that goes through
a repeated sequence of N states.
• The sequence may follow the binary count or may be any other arbitrary sequence

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Counter with Unused States
• A circuit with n flip‐flops has 2n binary states
Step 1: State Transition Diagram

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Step 2:
State Table for Counter
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Step 3:
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• Flip‐flop input equations can be simplified by using minterms 3 and 7 as don’t‐care

conditions.
• Use K-map
JA: KA :

JA = B KA = B

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JB: KB:

JB = C KB = 1
JC: KC:

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JC = B’ KC = 1

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The simplified equations are
JA = B
JB = C
JC = B
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KA = B
KB = 1
KC = 1

Step 4: Logic Circuit Diagram

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b) Ring Counter:
• A ring counter is a circular shift register with only one flip‐flop being set at any particular
time; all others are cleared.
• The single bit is shifted from one flip‐flop to the next to produce the sequence of timing
signals.
four-bit shift register connected as a 8-4-2-1 ring counter
Ring Counter (Initial value = 1000)

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• The initial value of the register is 1000 and requires Preset/Clear flip-flops.
• The single bit is shifted right with every clock pulse and circulates back from T3 to T0.

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State Diagram

1000
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0001 0010
• Each flip-flop is in the 1 state once every four clock cycles and produces one of the four
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timing signals
Sequence of four timing signals
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✗ Each output becomes a 1 after the negative-edge transition of a clock pulse and remains 1
during the next clock cycle.
Logic Circuit Diagram (Using D Flip flops)

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Counter and Decoder

✗ For an alternative design, the timing signals can be generated by a two ‐bit counter that goes
through four distinct states.

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✗ The decoder decodes the four states of the counter and generates the required sequence of

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timing signals.
✗ To generate 2n timing signals, we need either a shift register with 2 n flip‐flops or an n ‐bit

Example:
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binary counter together with an n ‐to‐2 n ‐line decoder.

• 16 timing signals can be generated with a 16‐bit shift register connected as a ring counter or
with a 4‐bit binary counter and a 4‐to‐16‐line decoder.
◦ In the first case, 16 flip‐flops are needed.
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◦ In the second, 4 flip‐flops are needed and 16 four‐input AND gates for the decoder.
• It is also possible to generate the timing signals with a combination of a shift register and a
decoder.
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c) Johnson Counter:
✗ A k ‐bit ring counter circulates a single bit among the flip‐flops to provide k distinguishable
states.
✗ The number of states can be doubled if the shift register is connected as a switch‐tail ring
counter.
✗ A k ‐bit switch‐tail ring counter will go through a sequence of 2 k states.
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✗ Starting from all 0’s, each shift operation inserts 1’s from the left until the register is filled
with all 1’s. In the next sequences, 0’s are inserted from the left until the register is again
filled with all 0’s.
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✔ A switch‐tail ring counter is a circular shift register with the complemented output of the
last flip‐flop connected to the input of the first flip‐flop.
✗ The circular connection is made from the complemented output of the rightmost flip ‐flop to
the input of the leftmost flip‐flop.

✔ The register shifts its contents once to the right with every clock pulse, and at the same
time, the complemented value of the E flip‐flop is transferred into the A flip‐flop.

✗ Starting from a cleared state, the switch‐tail ring counter goes through a sequence of eight
states

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Count Sequence and required decoding

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✗ A Johnson counter is a k ‐bit switch‐tail ring counter with 2 k decoding gates to provide
outputs for 2 k timing signals

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Four-stage switch-tail ring counter

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✗ Each gate is enabled during one particular state sequence, the outputs of the gates generate
No

eight timing signals in succession.

✗ The decoding of a k ‐bit switch‐tail ring counter to obtain 2 k timing signals follows a
regular pattern.
✗ The all‐0’s state is decoded by taking the complement of the two extreme flip‐flop outputs.
✗ The all‐1’s state is decoded by taking the normal outputs of the two extreme flip‐flops.
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✗ All other states are decoded from an adjacent 1, 0 or 0, 1 pattern in the sequence.

Example:
• sequence 7 has an adjacent 0, 1 pattern in flip‐flops B and C .
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• The decoded output is then obtained by taking the complement of B and the normal output
of C, or BC.

➢ Modifying the circuit to avoid undesirable condition when finding itself in an unused
states..
➢ One correcting procedure is to disconnect the output from flip‐flop B that goes to the D
input of flip‐flop C and instead enable the input of flip‐flop C by the function
DC = (A + C)B
DC is the flip‐flop input equation for the D input of flip‐flop C.
• Johnson counters can be constructed for any number of timing sequences.

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• The number of flip‐flops needed is one‐half the number of timing signals.

• The number of decoding gates is equal to the number of timing signals, and only two‐input
gates are needed.

Modulus-N-Counters:
• The counter with ‘n’ Flip-Flops has maximum MOD number 2n.
• Find the number of Flip-Flops (n) required for the desired MOD number (N) using the
equation,
2n ≥ N
MOD 10 Counter:

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2n= N= 10
23= 8 less than N.
24= 16 > N(10).

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The simple datapath with the control unit

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• The input to the control unit is the 6-bit opcode field from the instruction.
• The outputs of the control unit consist of
◦ three 1-bit signals that are used to control multiplexors (RegDst, ALUSrc, and MemtoReg),
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◦ three signals for controlling reads and writes in the register file and data memory (RegWrite, MemRead,
and MemWrite),
◦ a 1-bit signal used in determining whether to possibly branch (Branch), and
◦ a 2-bit control signal for the ALU (ALUOp).
• An AND gate is used to combine the branch control signal and the Zero output from the ALU; the AND gate
output controls the selection of the next PC.
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i) Operation of the datapath for an R-type instruction

Ex:
add $t1,$t2,$t3

Four steps to execute the instruction

1. The instruction is fetched, and the PC is incremented.
2. Two registers, $t2 and $t3, are read from the register file; also, the main control unit computes the setting of
the control lines during this step.
3. The ALU operates on the data read from the register file, using the function code (bits 5:0, which is the funct fi
eld, of the instruction) to generate the ALU function.
4. Th e result from the ALU is written into the register fi le using bits 15:11 of the instruction to select the
destination register ($t1).

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The datapath in operation for an R-type instruction

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ii) The execution of a load word

Ex:
lw $t1, offset($t2)

Five steps :
1. An instruction is fetched from the instruction memory, and the PC is incremented.
2. A register ($t2) value is read from the register file.
3. The ALU computes the sum of the value read from the register file and the sign-extended, lower 16 bits of the
instruction (offset).
4. The sum from the ALU is used as the address for the data memory.
5. The data from the memory unit is written into the register fi le; the register destination is given by bits 20:16 of
the instruction ($t1).

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The datapath in operation for a load instruction

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The datapath in operation for a load instruction

• The control lines, datapath units, and connections that are active are highlighted.
• A store instruction would operate very similarly.
• The main diff erence would be that the memory control would indicate a write rather than a read, the second
register value read would be used for the data to store, and the operation of writing the data memory value to
the register fi le would not occur.

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iii) Operation of the branch-on-equal instruction

Ex:
beq $t1, $t2, offset

Four steps in execution:

1. An instruction is fetched from the instruction memory, and the PC is incremented.
2. Two registers, $t1 and $t2, are read from the register file.
3. Th e ALU performs a subtract on the data values read from the register file. The value of PC + 4 is added to the
sign-extended, lower 16 bits of the instruction (offset) shift ed left by two; the result is the branch target
address.
4. The Zero result from the ALU is used to decide which adder result to store into the PC.

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The datapath in operation for a branch-on-equal instruction

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The final datapath and control

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MEMORY MANAGEMENT
• The task of subdivision is carried out dynamically by the OS and is known as memory
management.
• Uniprogramming system:
◦ main memory is divided into two parts: one part for the OS (resident monitor) and one
part for the program currently being executed.
• Multiprogramming system:
◦ the "user" part of memory is subdivided to accommodate multiple processes.

i) Swapping

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• Three types of queues:
1. the long-term queue of requests for new processes,
2. the short-term queue of processes ready to use the processor, and

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3. the various I/O queues of processes that are not ready to use the processor.
• I/O activities are much slower than computation and therefore the processor in a uniprogramming
system is idle most of the time.

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• Memory holds multiple processes and that the processor can move to another process when
one process is waiting.
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• But the processor is so much faster than I/O that it will be common for all the processes in
memory to be waiting on I/O.
• Thus, even with multiprogramming, a processor could be idle most.

Solution is swapping
• a long-term queue of process requests, typically stored on disk.
• These are brought in, one at a time, as space becomes available.
• As processes are completed, they are moved out of main memory.
• Now the situation will arise that none of the processes in memory are in the ready state (e.g.,
all are waiting on an I/O operation).

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• The processor swaps one of these processes back out to disk into an intermediate queue.
• This is a queue of existing processes that have been temporarily kicked out of memory.
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• The OS then brings in another process from the intermediate queue, honors a new process
request from the long-term queue. Execution then continues with the newly arrived process.

ii) Partitioning
• The simplest scheme for partitioning available memory is to use fixed-size partitons.
No

• Even with the use of unequal fixed-size partitions, there will be wasted time
• In most cases, a process will not require exactly as much memory as provided by the
partition.
◦ For example,
▪ a process that requires 3M bytes of memory would be placed in the 4M partition,
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wasting 1M that could be used by another process.

It leads situation in which there are a lot of small holes in memory.
As time goes on, mem becomes more and more fragmented, and memory utilization declines.

One technique for overcoming this problem is compaction.

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A process in memory consists of instructions plus data. The instructions will contain addresses for
memory locations of two types:
*Addresses of data items
* Addresses of instructions, used for branching instructions

A logical address is expressed as a location relative to the beginning of the program Instructions in the
program contain only logical addresses.
A physical address is an actual location in main memory. When the processor executes a process, it
automatically converts from logical to physical address by adding the current starting location of the
process, called its base address)

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iii) Paging
• unequal fixed-size and variable-size partitions are inefficient in the use of memory
• Suppose, however that memory is partitioned into equal fixed-size chunks that are relatively
small, and that each process is also divided into small fixed-size chunks of some size.
No

• The chunks of a program, known as pages, could be as signed to available chunks of memory,
known as frames or page frames
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• At a given point in time, some of the frames in memory are in use and some are free,

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• The list of freeframes is maintained by the OS. Process A, stored on disk, consists of four
When it comes time to load this process, the OS finds four free frames and loads the four
pages of the process A into the four frames page

Example, that there are not sufficient unused contiguous frames to hold the process. Does this prevent
the OS from loading A?
The answer is no, because once again use the concept of logical address.

• A simple base address will no longer suffice. Rather, the OS maintains a page table for each
process.

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• The page table shows the frame location for each page of the process.
• Within the program, each logical address consists of a page number and a relative address
within the page.

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• That refinement is demand paging. which simply means that each page of a process is brought
in only when it is needed, that is, on demand.
• Thus, at any one time, only a few pages of any given process are in mem and therefore more
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processes can be maintained in memory, When it brings one pag it must throw another page
out; this is known as page replacement).

iv) Segmentation
• Segmentation allows the programmer to view memory as consisting of mul tiple address
spaces or segments.
• Segments are of variable, indeed dynamic, size.
• The programmer or the OS will assign programs and data to different segments.
• There may be a number of program segments for various types of programs as well as a
number of data segments.

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• Each segment may be assigned access and usage rights. Memory references consist of a
(segment number, offset) form of address.
• This organization has a number of advantages to the programmer over a segmented address
space:
1. It simplifies the handling of growing data structures. If the programmer does not know
ahead of time how large a particular data structure will become, it not necessary to guess.
The data structure can be assigned its own segment and the OS will expand or shrink the
segment as needed.
2. It allows programs to be altered and recompiled independently without requiring that an
entire set of programs be relinked and reloaded. Again, this is accomplished using

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multiple segments.
3. It lends itself to sharing among processes. A programmer can place a utility program or a

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useful table of data in a segment that can be addressed by other processes
4. It lends itself to protection. Because a segment can be constructed to contain well-defined
set of programs or data, the programmer or a system administra tor can assign access
privileges in a convenient fashion

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DIRECT MEMORY ACCESS (DMA)

• A direct memory access (DMA) is an operation in which data is copied (transported) from
one resource to another resource in a computer system without the involvement of the CPU.
• To copy data from HDD to pen drive, CPU is not necessary
• CPU is general purpose processor and has lot of work has to be done by CPU in a computer
system.
• DMA is speed up the memory operations
• DMA reduces the CPU interaction in data transfer, so CPU utilization will be high in the
system

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DMA Controller:
• The unit that controls DMA transfers is referred to as a DMA Controller

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• DMAC is a controller (a chip) specially designed for Data transfer Invented by Intel.
• In DMA process, DMAC will take over the control of the Bus and become master of it until
the transfer is completed or CPU revoke the grant of master of bus
◦ I/O device request the DMAC (DRQ) to transfer data
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◦ DMAC request CPU to grant bus to use (HLQ - Hold request)
◦ CPU grants the access to use bus by DMAC (HLDA - Hold Acknowledgement)

• To initiate the transfer of a block of words, the processor sends to the DMA controller the
starting address, the number of words in the block, and the direction of the transfer.
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• The DMA controller then proceeds to perform the requested operation.
• When the entire block has been transferred, it informs the processor by raising an interrupt
signal.

Registers in DMAC:
No
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• DMA controller registers that are accessed by the processor to initiate the data transfer.
• Two registers are used for storing the starting address and the word count.
• The third register contains status and control flags.
• The R/W bit determines the direction of the transfer.
◦ When this bit is set to 1, the controller performs a Read operation.
◦ Otherwise, it performs a Write operation.
• Additional information is also transferred as may be required by I/O device.
• When the controller has completed transferring a block of data, it sets the Done flag to 1.
• Bit 30 is the Interrupt-enable flag, IE.

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◦ When this flag is set to 1, it causes the controller to raise an interrupt after it has
completed transferring a block of data.
• Finally, the controller sets the IRQ bit to 1 when it has requested an interrupt.

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• One DMA controller connects a high-speed Ethernet to the computer's I/O bus.
• The disk controller, which controls two disks, also has DMA capability and provides two
DMA channels. It can perform two independent DMA operations, as if each disk had its own
DMA controller.
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• To start DMA transfer of block of data from the main Memory to one of the disks, an OS
routine write the address and word count info into the registers of the disk controllers.
• The DMA controller proceeds independently to implement the specified operation.
• When the transfer is completed, this fact is recorded in the status and control register of the
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DMA channel by setting the Done bit.

• At the same time, if the IE bit is set, the controller sends an interrupt request to the processor
and sets the IRQ bit.
• The status register may also be used to record other information, such as whether the transfer
took place currently or errors occurred.

The DMA Controller Transfers the Data in Three Modes:

1. Burst Mode
2. Cycle Stealing Mode
3. Transparent Mode

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Burst Mode:
• Once the DMA controller gains the charge of the system bus, then it releases the system bus
only after completion of data transfer.
• Till then the CPU has to wait for the system buses.
Cycle Stealing Mode:
• The DMA controller forces the CPU to stop its operation and relinquish the control over the
bus for a short term to DMA controller.
• After the transfer of every byte, the DMA controller releases the bus and then again requests
for the system bus.
• In this way, the DMA controller steals the clock cycle for transferring every byte.

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Transparent Mode:
• The DMA controller takes the charge of system bus only if the processor does not require the
system bus.

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Storage Buffer:
• Most DMA controllers incorporate a data storage buffer.
• In the case of the network interface, the DMA controller reads a block of data from the main
memory and stores it into its input buffer.

computer bus.
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• This transfer takes place using burst mode at a speed appropriate to the memory and the

Then, the data in the buffer are transmitted over the network at the speed of the network.
Advantages:
• Transferring the data without the involvement of the processor will speed up the read-write
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task.
• DMA reduces the clock cycle requires to read or write a block of data.
• Implementing DMA also reduces the overhead of the processor.
Disadvantages:
• As it is a hardware unit, it would cost to implement a DMA controller in the system.
No

• Cache coherence problem can occur while using DMA controller.

Arbitration:
• A conflict may arise if both the processor and a DMA controller or two DMA controllers try
to use the bus at the same time to access the main memory.
• To resolve these conflicts, an arbitration procedure is implemented on the bus.
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Bus Arbitration
→A device that initiates data transfers on the bus at any given time is called a bus master.
→Bus arbitration is a process by which next device becomes the bus controller by transferring bus
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mastership to another bus

Bus arbitration schemes usually try to balance two factors:
▪ Bus priority: the highest priority device should be serviced first
• Fairness: Even the lowest priority device should never be completely locked out from the bus

Types of Bus Arbitration:

i)Centralized Arbitration
ii)Distributed Arbitration

Centralized Arbitration:
• A single bus arbiter performs the required arbitration.

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• The bus arbiter may be the processor or a separate controller connected to the bus.
• There are three different arbitration schemes that use the centralized bus arbitration approach
1. Daisy Chaining Method
2. Centralized Bus Arbitration Polling or Fixed Priority or Rotating Priority Method
3. Independent Request Method

• A DMA controller indicates that it needs to become the bus master by activating the Bus-
Request line, BR.
• When Bus-Request is activated, the processor activates the Bus-Grant signal, BGI, indicating
to the DMA controllers.

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• This signal is connected to all DMA controllers using a daisychain arrangement.

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• If DMA controller 1 is requesting the bus, it blocks the propagation of the grant signal to
other devices.
• Otherwise, it passes the grant downstream by asserting BG2.

• The current bus master indicates to all devices that it is using the bus by activating another

•
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open-collector line called BusBusy BBSY.
During its tenure as the bus master, it may perform one or more data transfer operations. After
it releases the bus, the processor resumes bus mastership.
• The arbiter circuit ensures that only one request is granted at any given time, according to a
predefined priority scheme. Alternatively, a rotating priority scheme may be used to give all
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devices an equal chance of being serviced.
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Distributed arbitration:
• All devices waiting to use the bus share the responsibility of carrying out the arbitration
process
• Arbitration process does not depend on a central arbiter and hence distributed arbitration has
higher reliability.
• Each device is assigned a 4-bit ID number All the devices are connected using 5 lines, 4
arbitration lines to transmit the ID, and one line for the Start-Arbitration signal
• A winner is selected as a result of the interaction among the signals transmitted over these
lines by all contenders. The net outcome is that the code on the four lines represents the
request that has the highest ID number.

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• if the input to one driver is equal to one and the input to another driver connected to the same
bus line is equal to 0 the bus will be in the low-voltage state. In other words, the connection
performs an OR function in which logic I wins.

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• Assume that two devices, A and B, having ID numbers 5 and 6. respectively. are
requesting the use of the bus.
• Device A transmits the pattern 0101, and device B transmits the pattern 0110.
• The code seen by both devices is 0111. Each device compare the pattern on the
arbitration lines to its own ID, starting from the most significant be If it detects a
difference at any bit position, it disables its drivers at that bit position and for all lower-
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order bits.
• It does so by placing a 0 at the input of these drivers.
• In the case of our example, device A detects a difference on line ARB1. Hence, it
disable its drivers on lines ARBI and ARBO.
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• This causes the pattern on the arbitration lines to change to 0110, which means that B
has won the contention.
• Note that, since the code on the priority lines is 0111 for a short period, device B may
temporarily disable driver on line ARBO.
• However, it will enable this driver again once it sees a 0 on line ARBI resulting from
the action by device A.

• Decentralized arbitration has the advantage of offering higher reliability, because

operation of the bus is not dependent on any single device.
• Many schemes have been proposed and used in practice to implement distributed
arbitration.

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PARALLEL AND SERIAL INTERFACE

Interface Circuits:
• The I/O interface of a device consists of the circuitry needed to connect that device to the bus.
On one side of the interface are the bus lines for address, data, and control.
• On the other side are the connections needed to transfer data between the interface and the I/O
device.
• This side is called a port, and it can be either a parallel or a serial port.

An I/O interface does the following:

1. Provides a register for temporary storage of data

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2. Includes a status register containing status information that can be accessed by the processor
3. Includes a control register that holds the information governing the behaviour of the interface
4. Contains address-decoding circuitry to determine when it is being addressed by the processor

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5. Generates the required timing signals
6. Performs any format conversion that may be necessary to transfer data between the processor
and the I/O device, such as parallel-to-serial conversion in the case of a serial port

Parallel Interface: fre

• A typical keyboard consists of mechanical switches that are normally open.
• When a key is pressed, its switch closes and establishes a path for an electrical signal.
• This signal is detected by an encoder circuit that generates the ASCII code for the
corresponding character.
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• A difficulty with such mechanical pushbutton switches is that the contacts bounce when a key
is pressed, resulting in the electrical connection being made then broken several times before
the switch settles in the closed position.
• Although bouncing may last only one or two milliseconds, this is long enough for the
No

computer to erroneously interpret a single pressing of a key as the key being pressed and
released several times.
• The effect of bouncing can be eliminated using a simple debouncing circuit.
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Figure 7.10: Keyboard to Processor connection

• The output of the encoder consists of one byte of data representing the encoded character and
one control signal called Valid.
• When a key is pressed, the Valid signal changes from 0 to 1, causing the ASCII code of the
corresponding character to be loaded into the KBD_DATA register and the status flag KIN to
be set to 1.

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Input-interface-circuit

• The interface circuit connected to an asynchronous bus on which transfers are controlled by
the handshake signals Master-ready and Slave-ready.
No

Implementation of the status flag circuit

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• The KIN flag is the output of a NOR latch connected

• A flip-flop is set to 1 by the rising edge on the Valid signal line.
• This event changes the state of the NOR latch to set KIN to 1, but only when Master-ready is
low.

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• The reason for this additional condition is to ensure that KIN does not change state while
being read by the processor.
• Both the flip-flop and the latch are reset to 0 when Read-data becomes equal to 1, indicating
that KBD_DATA is being read.

• A designer using modern computer aided design tools would specify these functions using a
hardware description language such as VHDL or Verilog.
• The resulting circuits would depend on the technology used and may or may not be the same
as the circuits shown in these figures.

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Output Interface:
• used to connect an output device such as a display.
• Assume that the display uses two handshake signals, New-data and Ready, in a manner

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similar to the handshake between the bus signals Master-ready and Slave-ready.

• When the display is ready to accept a character, it asserts its Ready signal, which causes the
DOUT flag in the DISP_STATUS register to be set to 1.
•

•
DISP_DATA.
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When the I/O routine checks DOUT and finds it equal to 1, it sends a character to

This clears the DOUT flag to 0 and sets the New-data signal to 1.

• In response, the display returns Ready to 0 and accepts and displays the character in
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DISP_DATA.

• When it is ready to receive another character, it asserts Ready again, and the cycle repeats.
No
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Display to processor connection.

Serial Interface:
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• A serial interface is used to connect the processor to I/O devices that transmit data one bit at a
time.
• Data are transferred in a bit-serial fashion on the device side and in a bit-parallel fashion on
the processor side.
• The transformation between the parallel and serial formats is achieved with shift registers that
have parallel access capability.

• The input shift register accepts bit-serial input from the I/O device.
• When all 8 bits of data have been received, the contents of this shift register are loaded in
parallel into the DATAIN register.

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• Similarly, output data in the DATAOUT register are transferred to the output shift register,
from which the bits are shifted out and sent to the I/O device.

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• Two status flags, which refers to as SIN and SOUT, are maintained by the Status and control
block.
• The SIN flag is set to 1 when new data are loaded into DATAIN from the shift register, and
cleared to 0 when these data are read by the processor.
The SOUT flag indicates whether the DATAOUT register is available.
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•
• It is cleared to 0 when the processor writes new data into DATAOUT and set to 1 when data
are transferred from DATAOUT to the output shift register.

• The double buffering used in the input and output paths

• It is possible to implement DATAIN and DATAOUT themselves as shift registers, thus
obviating the need for separate shift registers.
• After receiving one character from the serial line, the interface would not be able to start
receiving the next character until the processor reads the contents of DATAIN.
• Thus, a pause would be needed between two characters to give the processor time to read the
input data.

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• With double buffering, the transfer of the second character can begin as soon as the first
character is loaded from the shift register into the DATAIN register.
• Thus, provided the processor reads the contents of DATAIN before the serial transfer of the
second character is completed, the interface can receive a continuous stream of input data
over the serial line.
• An analogous situation occurs in the output path of the interface.

• During serial transmission, the receiver needs to know when to shift each bit into its input
shift register.
• Since there is no separate line to carry a clock signal from the transmitter to the receiver, the

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timing information needed must be embedded into the transmitted data using an encoding
scheme.

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• There are two basic approaches.
• The first is known as asynchronous transmission, because the receiver uses a clock that is not
synchronized with the transmitter clock.
• In the second approach, the receiver is able to generate a clock that is synchronized with the
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Asynchronous Transmission:
• This approach uses a technique called start-stop transmission.

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• Data are organized in small groups of 6 to 8 bits, with a well-defined beginning and end. In a
typical arrangement, alphanumeric characters encoded in 8 bits are transmitted
• The line connecting the transmitter and the receiver is in the 1 state when idle.
• A character is transmitted as a 0 bit, referred to as the Start bit, followed by 8 data bits and 1
or 2 Stop bits.
• The Stop bits have a logic value of 1.
• The 1-to-0 transition at the beginning of the Start bit alerts the receiver that data transmission
is about to begin.
• Using its own clock, the receiver determines the position of the next 8 bits, which it loads into
its input register.

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• The Stop bits following the transmitted character, which are equal to 1, ensure that the Start
bit of the next character will be recognized.
When transmission stops, the line remains in the 1 state until another character is transmitted.

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Synchronous Transmission:
• In the start-stop scheme, the position of the 1-to-0 transition at the beginning of the start bit is
the key to obtaining correct timing information.
No

• This scheme is useful only where the speed of transmission is sufficiently low and the
conditions on the transmission link are such that the square waveforms shown in the figure
maintain their shape.
• For higher speed a more reliable method is needed for the receiver to recover the timing
information.
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• Encoded data are usually transmitted in large blocks consisting of several hundreds or several
thousands of bits.
• The beginning and end of each block are marked by appropriate codes, and data within a
block are organized according to an agreed upon set of rules. Synchronous transmission
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Interconnection Standards
• A typical desktop or notebook computer has several ports that can be used to connect I/Odevices,
such as a mouse, a memory key, or a disk drive.
• Standard interfaces have been developed to enable I/O devices to use interfaces that are independent
of any particular processor.

• A memory key that has a USB connector can be used with any computer that has a USB port.

Universal Serial Bus (USB)

• The Universal Serial Bus (USB) is the most widely used interconnection standard.
• A large variety of devices are available with a USB connector, including mice, memory keys, disk
drives, printers, cameras, and many more.
• The success of the USB is due to its simplicity and low cost.

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• The original USB specification supports two speeds of operation, called low-speed (1.5 Megabits/s)
and full-speed (12 Megabits/s).

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• USB 2, called High-Speed USB, was introduced.
• It enables data transfers at speeds up to 480 Megabits/s.

• As I/O devices continued to evolve with even higher speed requirements, USB 3 (called Superspeed)
was developed.
•

• Key objectives:
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It supports data transfer rates up to 5 Gigabits/s.

1. Provide a simple, low-cost, and easy to use interconnection system

2. Accommodate a wide range of I/O devices and bit rates, including Internet connections, and
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audio and video applications
3. Enhance user convenience through a “plug-and-play” mode of operation

Device Characteristics
• The kinds of devices that may be connected to a computer cover a wide range of functionality.
• The speed, volume, and timing constraints associated with data transfers to and from these devices
No

vary significantly.
• The sampling process yields a continuous stream of digitized samples that arrive at regular intervals,
synchronized with the sampling clock. Such a data stream is called isochronous, meaning that
successive events are separated by equal periods of time. A signal must be sampled quickly enough
to track its highest-frequency components.
• Data transfers for images and video have similar requirements, but require much higher data transfer
rates. To maintain the picture quality of commercial television, an image should be represented by
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about 160 kilobytes and transmitted 30 times per second. Together with control information, this
yields a total bit rate of 44 Megabits/s. Higher-quality images, as in HDTV (High Definition TV),
require higher rates.

Plug-and-Play
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• The USB standard defines both the USB hardware and the software that communicates with it.
• Its plug-and-play feature means that when a new device is connected, the system detects its existence
automatically.
• The software determines the kind of device and how to communicate with it, as well as any special
requirements it might have.
• As a result, the user simply plugs in a USB device and begins to use it, without having to get
involved in any of these details.
• The USB is also hot-pluggable, which means a device can be plugged into or removed from a USB
port while power is turned on.

USB Architecture
• The USB uses point-to-point connections and a serial transmission format.
• When multiple devices are connected, they are arranged in a tree structure

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• Each node of the tree has a device called a hub, which acts as an intermediate transfer point between
the host computer and the I/O devices.
• At the root of the tree, a root hub connects the entire tree to the host computer.
• The leaves of the tree are the I/O devices: a mouse, a keyboard, a printer, an Internet connection, a
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camera, or a speaker.
• The tree structure makes it possible to connect many devices using simple point-to-point serial links.

• Polling:
• If I/O devices are allowed to send messages at any time, two messages may reach the hub at the
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same time and interfere with each other.

• The USB operates strictly on the basis of polling.
• A device may send a message only in response to a poll message from the host processor.
• Hence, no two devices can send messages at the same time.
• This restriction allows hubs to be simple, low-cost devices.

• Address:
• Each device on the USB, whether it is a hub or an I/O device, is assigned a 7-bit address. This
address is local to the USB tree and is not related in any way to the processor’s address space.

• The root hub of the USB, which is attached to the processor, appears as a single device.
• The host software communicates with individual devices by sending information to the root hub,
which it forwards to the appropriate device in the USB tree.

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• Connection:
• When a device is first connected to a hub, or when it is powered on, it has the address 0.
• Periodically, the host polls each hub to collect status information and learn about new devices that
may have been added or disconnected.
• When the host is informed that a new device has been connected, it reads the information in a special
memory in the device’s USB interface to learn about the device’s capabilities.
• It then assigns the device a unique USB address and writes that address in one of the device’s
interface registers.
• It is this initial connection procedure that gives the USB its plug-and-play capability.

Isochronous Traffic on USB

• An important feature of the USB is its ability to support the transfer of isochronous data in a simple

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manner.
• isochronous data need to be transferred at precisely timed regular intervals.
• To accommodate this type of traffic, the root hub transmits a uniquely recognizable sequence of bits

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over the USB tree every millisecond. This sequence of bits, called a Start of Frame character, acts as
a marker indicating the beginning of isochronous data, which are transmitted after this character.
• Thus, digitized audio and video signals can be transferred in a regular and precisely timed manner.

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Electrical Characteristics
• USB connections consist of four wires, of which two carry power, +5 V and Ground, and two carry
data.
• Thus, I/O devices that do not have large power requirements can be powered directly from the USB.

• Two methods are used to send data over a USB cable.

• When sending data at low speed, a high voltage relative to Ground is transmitted on one of the two
data wires to represent a 0 and on the other to represent a 1.
• The Ground wire carries the return current in both cases.
• Such a scheme in which a signal is injected on a wire relative to ground is referred to as single-ended
transmission.

• The speed at which data can be sent on any cable is limited by the amount of electrical noise present.

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• The term noise refers to any signal that interferes with the desired data signal and hence could cause
errors.

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• Single-ended transmission is highly susceptible to noise.
• The voltage on the ground wire is common to all the devices connected to the computer.
• Signals sent by one device can cause small variations in the voltage on the ground wire, and
hence can interfere with signals sent by another device. Interference can also be caused by one wire
picking up noise from nearby wires.

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The High-Speed USB uses an alternative arrangement known as differential signaling.
The data signal is injected between two data wires twisted together.
The ground wire is not involved.
• The receiver senses the voltage difference between the two signal wires directly, without reference to
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ground.
• This arrangement is very effective in reducing the noise seen by the receiver, because any noise
injected on one of the two wires of the twisted pair is also injected on the other.
• Since the receiver is sensitive only to the voltage difference between the two wires, the noise
component is cancelled out.
• The ground wire acts as a shield for the data on the twisted pair against interference from nearby
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wires. Differential signaling allows much lower voltages and much higher speeds to be used
compared to single-ended signaling.
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SATA

• In the early days of the personal computer, the bus of a popular IBM computer called AT,
which was based on Intel’s 8080 microprocessor bus, became an industry standard.
• It was named ISA, for Industry Standard Architecture.
• An enhanced version, including a definition of the basic software needed to support disk
drives, was later named ATA, for AT Attachment bus.
• A serial version of the same architecture became known as SATA, which is now widely used
as an interface for disks.

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• Like all standards, several versions of SATA have been developed with added features and
higher speeds.
The original parallel version has been renamed PATA, but it is no longer used in new

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equipment.

• The basic SATA connector has 7 pins, connecting two twisted pairs and three ground wires.
• Differential transmission is used, with clock frequencies ranging from 1.5 to 6.0 Gigabits/s.
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video devices.
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Some of the recent versions provide an isochronous transmission feature to support audio and

Features:
1. Low Voltage Requirement: SATA operates on 500mV (0.5V) peak-to-peak signaling. This
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help in promoting a much low interference and crosstalk between conductors.
2. Hot Plugging: This feature helps users to change or remove storage devices even when the
computer is running.
3. Staggered Spin-Up: Allows sequential hard disk drive startup, which helps even out power
load distribution during system booting.
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4. Native Command Queuing (NCQ): Usually, the commands reach a disk for or writing from
different locations on the disk. When the commands are carried out based on the order in
which they appear, a substantial amount of mechanical overhead is generated because of the
constant repositioning of the read/write head. SATA II drives use an algorithm to identify the
most effective order to carry out commands. This helps to reduce mechanical overhead and
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improve performance.
5. Port Multipliers: Allows the connection of up to 15 drives to a SATA controller. This
facilitates the building of disk enclosures.
6. Port Selectors: Facilitates redundancy for two hosts connected to a single drive, allowing the
second host to take over in the event of a primary host failure.
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7. Simplified construction: PATA cables had 40-pin/80-wire ribbon cable. This was complex
in structure. In comparison, SATA had a single 7 pin data cable and a 15 pin power cable.
This cable resulted in a higher signaling rate, which translates
8. Differential Signaling: SATA uses differential signaling. Differential signaling is a
technology which uses two adjacent wires to simultaneously the in-phase and out-of-phase
signals. Thus, it is possible to transfer high-speed data with low operating voltage and low
power consumption by detecting the phase difference between the two signals at the receiver's
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9. High data transfer rate: SATA has a high data transfer rate of 150/300/600 MBS/second.
This capability of SATA allows for faster program loading, better picture loading and fast
document loading.
10. Large Cable Length : SATA cable can be of length up to 1 meter, whereas PATA cable can
only have a length of maximum 18 inches.

Operating Modes:
SATA operates on two modes:

1)IDE mode: IDE stands for Integrated Drive Electronics. This mode is used to provide backward

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compatibility with older hardware, which runs on PATA, at low performance.

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2)AHCI mode: AHCI is an abbreviation for Advanced Host Controller Interface. AHCI is a high-
performance mode that also provides support for hot-swapping.

The Serial ATA [SATA] bus is defined over two separate connectors, one connector for the data lines
and one for the power lines.
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