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    Pic16c54c PDF, Pic16c54c Description, Pic16c54c Datasheet, Pic16c54c View - Alldatasheet

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    danyetn

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    MicrRocHIP: PIC16C5X EPROM/ROM-Based 8-Bit CMOS Microcontroller Series Devices Included in thie Data She “The lair "=" used fllonina the pal numbers. throughout this document Indicate plural, meaning there fs more ‘han one part variety fr the Indested deve, High-Performance RISC CPU (Only 38 singe wordinstuctions to eare + ainstcons are single jee (200 ns excepttor program branche wich ste ogy + Operating speed: OC - 20 Ue oc inpt 16200 nsinsrcton cycle 112-3 idenstuctons 1 eiatwde eat slack + bret ret ang rea aaresseg modes Peripheral Features: + S-bteal ime clckteourter (RO) wah 6 progammate presser + Power Reset POR) + Dence Reset Timer (ORT) + wat Taner (NDT) ws oun on-chip RG oscbtor for etl opraten, + Progranimabie code protection + Power aavng SLEEP mose RG Low-cost RC osctor XT: Standard eystalresenatr LP: Power sain, lewtequency rsa (CMOS Technology: + Low-poner high peed CMOS EPROMROM tecmnoi0gy + Fay sane aesgn + wie operating votage ana ampere range EPROM Commerciaundueti 2 0V 0628 EPROM Extended 25V 196 0V + Lou power corsunton <2 matypeal @ 5 « He ss catypeal @ 3, 322 © 06 zatypical sancy cent (wit WOT sated) @3V, 00 70°C Ths document figure and able tes | tater toa varies of te part number Indicted, (Le. The tle "Figure 14-1 {Leas Conaltions = PICISCO4A", ais refers 1 PICTELCSAR and PICISLYSSA par EPROM pine | vo [EPROM pay ee ab accep Teeter ne. Preliminary ‘Devuseaeepe + PIC16C5X POI, S01, Wincowed CEROIP Preliminary 290 weap Tesmaogy ne PIC16C5X Device Ditferences vouge ) ozslater Process Neue Device Range | Set senator | tectnology | goon | ‘Miter (Prose (Wzrors) PIcrecee 25825 | _Facoy | Seenotet 72 | PTR | No cress | 2555 | user | Seenoet | 07 | PICTOREAB | Yes PIcrecss 25825 | Fac | SeeNotet 7 = Ne. crecssa | 2556 | user | Seenaw1 | 07 = ve PICTeCsS: 25825 | Facioy | SeeNetet 7 = Ne. pcweesa | 2556 | User | SeeNow1 | 07 | PICISORGEA | vee powesre | 2558 | User | SeeNowt | 07 | PCTSORETC| Yes icveceea | 20826 | User | SeeNow1 | 09 | PICTOORERA | Nol pcworsea | 26626 | Faciry | SeeNow! 2 WA ve Picworss© | 2558 | Faciry | Secnowt | 07 NA Ye Picweors7= | 25025 | Fac | SecNeet | 08 WA Ye Powworsre | 2586 | Fasay | SecNoet | 07 WA ve Pioweorsaa | 25625 | Factay | SeeNewt | 09 NA ve pcwworses | 2558 | Facioy | SeeNetet | 07, NA Ye Note you change for tis aevice te aroher device, please very osclator charactnstcsin you pplication 11886 cep Tesrcay ne Preliminary Denoasis pape PIC16C5X 10. General Desenpbon 5 20. PICIOCSX Device Vacs 7 30 Arentocral Oversee 3 40° Memory Oraizaon 5 80 Ter Mocue ana THRO Register zr 10 Special Feates ofthe CFU ey 80 netuchon Set Summary 3 80 Development Suscor. 55 100 Eectcal Charecerstes PICIBCHE 8 310. Eteshneal Chaacerstes PIGIBCS4S5/68157 or 120. Elechncal Choracorstes- PIGIBCRS¢A 88 150 Electical Charactonstcs -PIOISCRSTS. 7 160 Eecieal Charsctonstes PICSCSBA 131 470 Eecncal Ghracerctes PICYBCRSCA HS 180 DC ang AC Chavactenees -PICTOCSAAICRETBICHSACRBRA 190 180. Eleccal Chaacerses 200 DC and AC Charactensics 240 Packaging Information 105 ‘spend Compatity oor Index 208 C-Lne Support an PICI9¢5X Product Kentcaton Syston a1 PICBCS4/SSGES7 Product lertseaton Syst a4 To Our Valued Customers Most Current Data Sheet ‘mimeencp Theat rade fis vaue noe se wrsun hte 29. DSSOOGOA Seen AGT ecu ESSN ‘Serer ete rm nes grins ee et ran Secs cere mgm es ce ee rt Shae aeaereecomiree cemetery oe pe eet ot "Nome a nse erence «Moers are “pb Soa eee ra ena ingest ce a op oh en in te ae atonrgatte os SS Sees nema acs cece aaa es BEeean as "eeu ease regenmnnetsasecttt « gost wees yr ceria Denoasis ane + Preliminary 290 weap Tesmaogy ne PIC16C5X 1.0 GENERAL DESCRIPTION ‘The PICIECSX tom wleroehip Tecnology 2 tamy of lowcost righ peromanee, et, uly. EPROM! ROWaaees COS mierecentalers Cempoys a RISC arcttechre wih ony 30 shoe novangle ile nstuctors Alnstuctons are er Ge eye (200 ns excep fr program branches hich {bho to eyes. The PICISCEX deivers perfomance [order ctmapeausenigher hans compatarsinte Same pce catagory. The 12-bit wide nstucbne a Noni Symmetric testing in 2 code compressa ‘ver ober bt merocorvolers ine dats. The easy {o'use and ear to remember netucton set ree Sveoomert ime sn feanty ‘The PIC TECK products are equpged wih special ea tures thal reduce system cost and power reguremerts (DRT) elmnate the need tr extemal reset icy ‘There ar tur osiatorconigorssone 9 ene om) eluding the powerseung LP (Low Powe!) esa! Sd cart sgung RC over Power eavng SLEE? ‘rode, Wastchdog Timer and code grotecton fetes rece system ost power an ely ‘The UV ersabe CERDIP pactaped versions are tea ‘er cose deveoprent,whle he costefecne Ore Tine Proyanmatie (OTF) versions are sutatle for producan mary volume, The customer can Take fl Soveriage of Mlrecho's prce leases in OTP merccentolers ie. pereting tom the OTPe ‘ew, The PICHECSK produce ate supported by = {20 ar cost evelopment soglammet ad 3 fal ‘eated propianmer Al te tole ate suprted on IBiI*PC ana compavble macnnes. 1.4 Applications The PICT6CX series fs pret in appeaton rang Ing tom highspees aoe ans applance mole! {onl to owpower remote wansmersteceters poming daveesanatelecam processors The PROM ‘Eennaogy mates customizing appeaton pregans (eansmitar codes, motor specs, recone! Fea ee, ec) extaroy fast and conenent The sma {eotnnt package, for trough hol or surage mount ing make the meroconrale sees pre or arp ‘ons th space imators Laveen ow-pover hah Deromance ease of use ana VO Menay mate te PICt#C8X seves very versie ven in areas where no Imercontolr use hasbeen cofadered belo 9 timer funtons, eplcement of ha" ge in liger system, copaceseeraplestons). 11886 cep Tesrcay ne Preliminary Denoassaapes PIC16C5X TABLE 1-41: PICISC5X FAMILY OF DEVICES EPROM Peg EEE res re Pacagee ep sc e protect ang high lO current eapabity - or Onemton i) oo Le mor— faROR peor hapa pT fonnsscr lesen scor lstomso> _[ropn scr _[zepn ssor ‘lilcnico"™ Faniy devices have Power-on Rese seca Wats fpotet anc igh U0 cent capa (eentPICT6CE2) selectable code inary ‘388 mean Tesagy ne PIC16C5X 2.0 PIC16C5X DEVICE VARIETIES 2 vanity a requency ranges and packaging options ‘ae avalate Depending on appleatan ard producton requrerans, th proper device opon can Se selected using he infrmaton ins sect When plaeng orders peace use the PICTSCEX Prowet Keenifeaon Sytem at he back of is datasheet spect the coe! port namber dence types, ab inccated he devee number EPROM program memery and operate ver he EPROM program memory and operate over an fended okays ange EPROM program memory and operate over 3 Bovios avenge ROM program memory and operate over the ancard vate ange 5 LER, asin PICTELCRSAE, These devices have FROM program memory ard operate over 3° ‘ended atage ange 24 UVErasable Devices (EPROM) Backazes, ate opin fr sottpe devecprent ard Blt programs LY erasable devices can be progammed for any of the four osellter contgursions Mieroewo's PICSIART™ and PRO NATE programmers, both ‘ispot programming ofthe PICIOCEX. Third pany rooremmers a0, me avalabl, reer 0 the Td 22 ‘The aalabity of OTP seco Gintomers expecing eqven code changes and seats ‘The OTP devees, packaged in plosbe packages perma he ser to progam tem once In aden To the pogram menary Be coniguaten bis must be programmed Microchip fers 2 GTP Progamming Service for ‘aisle for users who choose not to program = ‘medium vo hgh quaruy ct uns and whose code Dates have sablecd The Seve ae ena Canfguraton bt optors aeady plogranmed by the ‘Scory ‘Conan code and prottype vendeaton Procedures apply before preducion stgment ae [aisle Plesee contat your hirocnp Tectnoogy ‘ses ofc for more detals 24 Serialized. (Quick-Tumaround:-Production (SOT Devices Microchip ofers the uniue progrmmag service ‘where few userdetnod lets enc dee are progrmmed tn aernt sera) nmmoae The ser) humbers may. be random, pseutorendom ot entgaten bt opens areas perenne ty Be Seral pregammng slows each davce to have a Uniqs nomber wich cn eerve 35 an ey C008, Dascword or ID number 25 Read Only Memory (ROM) Devices Microchip offers masked ROM versions of several of the highest volume pars, ging he customer 3 lw ‘ast opton or high volume, mature rods 11886 cep Tesrcay ne Preliminary Denoasisape? PIC16C5X NoTEs: PIC16C5X 3.0 ARCHITECTURAL OVERVIEW ‘The nigh peteemance of he PICISCSK amy can 2e commonly fund in RISC merepoeessors. To beam wh the PICTECSK uses a Hard aentecre whch program and data are aeceseed on separate Sunes ‘Tas improves Sandi ovr tadtora Yon Neumann archectire where poaram and dala ore ‘wuned oo Be same bus Separaing progam ard data memory further atows nstucton to be aed opcodes ate 12s wide makin i porsble Lo ave a Srge word instuctone ®t ce. program tremor sczoas bus feches 9 12-6 inrocon m2 Singe Cle A two-stage ppelne oveiaps fn snd crecitenofnsuctons Consequenty. al rtrustons 3) exacste na sig eye (2008 @ 282) ‘except fr program ranches. ‘The PICTECS2 addressee. 384 x 12 of program momoy the PCTSSHsCRSt and PLCTECSSS Gourees 612¥ 12 of program meme, te PICTOCEDRGRSOS actress 1K X 12 of progam memoty and the PICIECSTSICRSTS and PletecsecRsas adsess 2x12 of progam memory Al progam memory sir regetor fies and dala momen. Al special funcion ‘hea meray The PICISOSX has) nah ‘thogera syresicalisrocbon St that rakes Bessibe f9 cary eu any opeaton on ary Teste? sng ay adeeasng mase Ths syrmeticl atte and ack of speca optimal stustons) make frogrammng weh he PICIBCSX Sipe yot eee Inaddten the learning curves reduced sigan vetting repster The ALU is 2. general purpoce 2rtwnetc unt It pereims antete ana Bactean ‘ctor between data the working eegitr and ary register fle The ALU is Bis wide and capale of ation siracion, shit and legeal operatons.Unoss Dherwse mentored athmetic operatans ae 00's mpement in natu, In two-cperand nsuctons ‘spcally one operandi the W working register The (her epefand setter aie register or an meds near In ingle operand netustons he operand Is ether the W register orale eget. ‘Toe W register isan 82 working reper used for [ALU operates. Itis not anaderessabe reper Cesening on the instruction executed, he ALU may siecle vaues ofthe Cay (C, Digt Cary (OC), Sand Zero (2) nthe STATUS register The © and [Bo tte operate a a aro and Sig Sao out 11886 cep Tesrcay ne Preliminary Denoasis pape PIC16C5X PIC16C5X TABLE 34: PINOUTDESCRIPTION -PICTECE2, PICIECE4s, PICIECREAs,PICTECESE, PICISCRSBs, PICTECSSs, PICIECRSSs me [00.80% |$80° [10] input vcinton ‘ Now| No. [Type | Levels Desens Par Ta po] Tt Sarma TRA Rat we | 2 | uo] mm Rao] 6 | 7] uO | TT | Beairecinal VO pom Rt 7 | 6 fw] m Fz e | 8 fio] mm 53 e | a fuo | mm Rs 4 | 2 uo} mm R86 2 | fu] m Ra? | @ {to | Took! 3 [2 | 1 | St |Glookineutto Tie Hoi be tea e Vesor Von Wat ss, tredce cron coneameton Weta | 4 | aT | ST [taser ea: (eset) mpuvproyanmingvlage pul Ths fone anacive low rset the device Volage onthe [iGCRvre ain must exceed Von to avo unntenced entenng of programming mode SSCA | 18GB _| TST [Osctntor cys npuietemal cocksoure nod DSCRCLKOUT] 18] 17 | © | — [Oslo ens cust Connects to crystal or esonatria [ysl osclnior mote nC mod, OSC2 pn crue CLROUT which nas 14 he Reauency of CSC, and denctes Ves) ia fg 1S |B | Ponte sep tortane and 0 ane Vee = [56 | > | —[Greundretrenee rege ana 0 pins ager 11886 cep Tesrcay ne Preliminary Temio paper PIC16C5X TABLE32: _PINOUTDESCRIPTION- PiCTECE&s, PICT8C57e, PICIECRE7s DP, $016] SSOP VOIP | input Nome 1 Ae oe ee Description Fav ©] | 10 | TH erarectona Oper Raz e | 7 [io] m 0 wf 9] 10 | TIL |Beareconal 10 pow Ret 1 | w | vo | me RS | 2 | vo | m ee | 3 | uo | mm Res is [as | io | mm ee we | ae | vo | mm Ret | 7 | to | om Ret | a | vo | mm Ro » | 2 | io] m Re a |B [io] me Roe 2 | 2 | io] m RO a | 2 |v] m RO? | 3 | to | me T0Cki + [2 | 1 | ST [Geckinputio tre Must be ted to Vis oro tt muse oo [BW [7] SF [aster ear (ose mput Ths pn wan civ ow west ioThe | dere OSGTLAN| 97 |_| 1] ST osatetaraysiatnpenieral cbck somes pal OscuCLKOUT] 28 [20 | 0 | — |Oselnorcnta uput Connects to cea or resonaior = Cyst oscar mode in te mode, 862 pn ouput [CLKOUT wich has 1 he Fequency of OSC, and dentes veo 2 [ae [e_[—Postie suppy or ioei ana vO ns | vss 4 [ase [P= [round erence frog an 10 pe ouput Net ses FUT TTC inna St = Seber ager in oasis ane 12 Preliminary 290 weap Tesmaogy ne PIC16C5X 34 Clocking Schemelinstruction Cycie ‘The docking (OSC'/CLKN pin sinter ies by You to genase out nan-ovenageng quadate checks nary Of, G2, O3 and Ot teal, Cee program chute ncementad every G1. and he mstucion fetched ftom progiam memery ard itched int ineructon reqater m4. ts cecooed Sd ect dng te falling 0 trounh Qe The ‘Seske and inetucten yoavton fou shown > Figure 2:2 ond Example 1 32 Insinction Flowipeining An nsructon Cycle consists of fou cycles (21.2 {Gb ana Ga) The isucton Seen and oweute ae Dipeined sich that fetch fates one insucton cycle joe However due lo Be ppetnng, each inseucion fecnvely erecutes in ove cle. an inseucton PIC16C5X NoTEs: PIC16C5X 4.0 MEMORY ORGANIZATION PICTBCEX memerys organzed nto preg memery ‘data memory For devices wih move han S12 apes! program menor, a saga snene uses ‘wo STATUS reister bis For devices wih 9 data memory register fie of more than 22 registers 2 Sonking seheme re sed Data memery banks are ‘ezessed using the Fle Selechon Register (FSR) 441 Program Memory Organization Woot adbeting SHE moan nen) Seceguely ttacss, meorear a Heteelivnon rion Poa Gert 0) Gusset asing 310597 pagan nes) ee eased te Se, wet Br agra Sooner Peyapsow st Wicsing 98 1 poem ery space Ficuors ones arp Ste eva Sacatinmg tats Saba mene teat gat 2) Rcsong ana toe Be cay [eee scare erpunes Tete oon Hees TPH ANOE demeanor te coatitam be PeNeeess Jee ih esna tocar or a BiceeeTa mn FIGURE.41: Plctscs2 PROGRAM MEMORY MAP AND STACK Le “tT 54 38) | oncipaooan zB wees 11886 cep Tesrcay ne Preliminary porrererrerl PIC16C5X FIGURE 4-4: PICISCSTSICRETSICEBS! (CRSee PROGRAM MEMIORY MAP AND STACK cnc roxan oes) z ‘tora rage) | est ‘oy ome) — Sh crameoran | on PIC16C5X 42 Data Memory Organization FIGURE 4-6: PICIC82, PICTECsAe, PICIGCREts, PICT6CSS5, ait Three daa meray fo vce peed Piclecste, FICIECR Sts by ts register fi The register le sched mo to REGISTER FILE MAP. ‘ineiona! groups: special funeion registers and Fre sears general purpose reastes = ‘The special function cegisters include the TMRO »{|__ wont | register the Program Counter (PC), the Status ots [rm Register the VO rogsters (ports), andthe Fe Select coy [row Repistes FSR) In ston, 3078 purpose reaiste's lowes ‘re vsed to conrl the 10 port configuration and | seus _| peessaeoptone on [rsa | For the PICIECS2, PICTECS4e, PICTECRSAE om | pomre™ Piotoeses ana PICTSGRSSs, the eepster Mes ‘composed of 7 spacial function registers and 25 ‘ners purpose reneters Figure £6). on | cman For the PICACSs the raiser ls composed of @ c| Ses srecal function esters and 24 general purpose “o reasiens For he PICIECSTS and PICIECRSTs, tne raga fle & composed of special ancton east, 24 gener 1 Sutpose fegte's snd up Io #8 acaiinal geneva utpose rogisers that may be addressed using @ huss Mears oman 47 Sankng scheme (Pgs #5) 2 Reseed Sd For he PIGI9088s and PICTECRSGs, he reper le composed of special kncton epstes, 28 aeners urpose egiste's and up to 48 aedtional general utpose registers tnat may be addressed using @ Sarkng scheme (Fue +7) ‘The ropter toe accatses eter ares or racy ‘tough he te select register FSR (Secon 47) 11886 cep Tesrcay ne Preliminary Tenia pageT PIC16C5X FIGURE 4-6: PICISC57SICR57e REGISTER FILE MAP. FoR FIGURE 47 To f ! aoe \ \ a i \ ae ' 1 resoes_forn Leen |e com | Sem] Sem | See ce. | Se | Sh | Sen PICTSC588/CRS9e REGISTER FILE MAP. Doses ane 18 Preliminary Were Tearaogy ne PIC16C5X 422. SPECIAL FUNCTIONREGSTERS ‘The specal registers can be assed into wo sts ‘The special function registers associate withthe The SsecalFuncion Registers ar registers used ty “gaya uncon ate desered nth action “hose ine CPU and peripheral functions fo contol Me ead tate apetabon a the erga fealues ate operaton of he eve (able 1) {fesertes in tne seetn foreach pargherl ere TABLE 41: SPECIAL FUNCTION REGISTER SUMMARY PIC16C5X 43° STATUS Register ‘This resiter contains the ahmeti stats ofthe ALU the RESET status and ne page preselect BES for progam remotes ger than 512 words ‘ie STATUS register con be te gestation for any ‘egisteris the destnaton fran nstucion that aes disabled. These bis are set or claarea accoraing to the device gis Furthermore the TO and PD tt re the STATUS repster as destnaton maybe aferent For example, PIC16C5X PIC16C5X as the Prooram | Preliminary 1 388 mean Tesagy ne PIC16C5X FIGURE 4-12: LOADING OF PC BRANCH INSTRUCTIONS - PICIGCS7S/PICIECRSTs, AND PICTECSES/PICTECREBS aT 11886 cep Tesrcay ne Preliminary porrerereer| PIC16C5X ar FSR Registers Tho INDF register is not a physical register. Addressing INDF actually adsresces te reaster whose adress contained the FSR renter (FSR IS panien Ths sine aaaressing EXAMPLE 44; INDIRECT ADDRESSING Regier fie 05 conan he value 10% east fle 08 conan he vale Ah + Liza te vue Os tone FSR reise * Ateadf he INDE register wil tum he value orion + Increment the vl ofthe FSR reise by one (fare ost) + Bread fhe INDR register now il retarn he Reading INDF ise indiecy (FS 0) wit reduce Dan Wrtng wo the INDF rege neat Yess n no-opraten (attough STATUS bis may be atected). ‘A simple program to clear RAM locations 10h-1Fh EXAMPLE 42: Denoasis pape Preliminary HOW TO CLEAR RAM USING INDIRECT ADDRESSING PIC16C5X PIC16C5X Preliminary PIC16C5X 6.0 TIMERO MODULE AND ‘TMRO REGISTER ‘The Timer roaule na the lowing feces + eet tmericounte register, THRO + bit sofrae prograrnate prescakr ge Select exemal cook gue 1 a a sinplited block diagram of he Tmere mode while Pee 6-2? shows the electcal stucte ofthe Tene put Timer mode is selected by clearing te TOCS bt (OPTIONS) Inver mode, the Timer mode wil nerement every insrucion el (wht pesca’) I ‘THRO reste fe wren. the neroner ses or the frowng two oyses (gue 69 and Faure 6-2) ‘The use can wotk around Ths by wring an adusted aus te THRO epee Couner made Is selected by seting ne TOCS mt (OPTION®5*) In tis mode, Ted wl nrement ‘ner on every targeting adge of pn TOOK. The Inerementng edge is determined bythe source edge Sect ot 1056 (OPTION) Clearng he TOSE ot ‘secs the rising edge. Restrictons onthe eterna ‘Seek npuae dacusescinaetai m Secon 6+ The prescaer may be used by eiher the Tine rmoaule or te Wtendog Timer put not Bom The peseaerassgnment conta im sotate by te Chole PSA (OeTIONeS»)Clamng the PSA Dt ‘assign the plescalet fo Tero. Te prescaler hot reseable er yetatla.Winen the. preseacr {esioned othe Tard edule, proscate vues of 2 a2) 1258 re soecabe. Sevton 5.2 seis ne pein fhe presi 1 summary of regsors associated wth the Tine FOUR 61. _TMERO BLOCK DIAGRAM base a I ter fee PP vege ‘Boyce asiay) SHE pedis rat ves 2 SUEMOEOMGG Saeco: GUE 62 ELECTRICAL STRUCTURE OF TOK! PR cad aor kw HP SBmRa vee £50 pomcon et 11886 cep Tesrcay ne Preliminary rere PIC16C5X FIGURE 6-3: TIMERO TIMING: INTERNAL CLOCKINO PRESCALE, FIGURE 6-4: TIMERO TIMING: INTERNAL CLOCKIPRESCALE 1:2 TABLE 6-1: REGISTERS ASSOCIATED WITH TIMERO Address Nome SRT BRE BRS Bes BRI Bk2 Bri Bio “Reser” Om TWRO—TimerO-B-btreahime clociounter Dsoasis ane 28 Preliminary 7 o90 urea Temagy ne PIC16C5X 6.41 Using Timerd with an External Clock Winen an extemal clock inpit used for Tene. rust cet cetan Yegarerers. The external lock requirement ave f0 nema phase cose (Tose) metementng of Tuner afer syacherzaion hen no prescaer is use, the eternal lock inputs ‘he exe a he preset opt The syncronization oF Tock! wih" the eternal phase cocks {esonpienedoyeamsing the peeeser ouput on te G2 and G4 cyces of the nena phase. cocks (Figua 5) Tomretare. ts necessary tar TOK be high atleast osc (and a smal RC lay ct 201) {hd iow fo atleast Tose (and 2 smal RC day of 200s) Reter to the eectieal spectcaton of Ce FIGURE 6-5 nan a pesca suas, he extemal cack pt ded. by the asrchreneus ronle courteripe pesca Soha he prascatr ouput s syed For the externa cock to mast the soning requrement me ple ecurer most Be taken ins Serourt Theres recessry for TOK! hane 2 Benod of last 47005 (ans a smal RE aay ot ns) dvded by the presale vale The ony (donot uate he miner pulse with querer ot 10 ns. Rote to parameters 40, 41 ane 42 Ine ec specicain othe desea deve 612, TIMEROINCREMENT DELAY Since the presale output is synchronized wih the Inloral lst thers smal etay rm the eve he exeral clock edge oceu's fe the tne the TinerO ‘nodule le acualy neemantad Fue 6 snows he {ei fom the external clack edge to the timer irermentng ‘TIMER TIMING WITH EXTERNAL CLOCK. Jon! a2t an! at Peseaerooua) {TD Jat) a2i Ga! at fat! a21 Gat at at a2! Galax ‘sale r ‘(tee Seraing Path hoa 4 4 stenatcosrecats fy KO Seonaceseg [| inser Trt) ‘boty tom sr neut ange o Te ema soe Tees. (usten ot Teo) Sherer te eran meaning neta teveen oes on Tred roe ‘nal ox fn pesaet sued Ponca capa aber 5 Te arows nace be poms Are wre sping c= 11886 cep Tesrcay ne Preliminary pamererer) PIC16C5X 62 Prescaler An i counter avlabie as a prescaer fr the ‘mero module of 36 posisea fo the Watendog Timer (WOT) (WOT postcaer not mplemented on Picsc82) respecte (Secton 512) Forse is cour beng vetrred to. 35. “prescalr brroughout ths outa sheet Noe that te prescaler tay be used by eter he Timed meas othe WOT, Bit not bmn Thus 2 pescaer aswgnmart for the Timer module means tat there fro prescler et theWOT and wee ere ‘ne PSA ana P52 PSO Dis (OPTIONS) determine Droseaerasigment and preecae ao. nen assigned to he Timet0 modus, at nstuctons wining tote TWO rege (22. PIC16C5X 7.0 SPECIAL FEATURES OF THE CPU Winat st 2 mirocontoler apart fom other proceseors we special cuts that desl uty needs of reat time appcatons The PICISOSX fy rterded to maximize system relay, minimize cost ‘tveughelimnaban ef external component previ power saveg.opelatng maces and flr cose Protection These stres ae uiltor selection Reset + Power On Reset (POR) Device Rese Timer (ORT) + Watchdog Tener (NDT) (natimplemeried on PICTECS2) + SLEEP + Coe protection + acatons (net implemented on PIC18CS2) ‘The PICTECSK Family has a Watchdog Timer which can be shat of ony tough conigraton BI VOTE fans ff of ts ow RO oscar fr saded flab “There gan 18 ms daly provided dy he Device Reset Timer (ORT), nlended Yo kee te chp it vest unt she ental onstrate ith te mar on-omD, tros acpfcaions needno eternal eset cet ‘The SLEEP made 1 designed to ter a very lo erent poe dwn mode The ver can wake oom ‘SCEEP though external reset ar tough a Watenaog Timer tme-ut Several esate optors ate ale ‘made avaatio to alow te parte tthe apoieaton ‘Tae RO escilatorapton saves system cst whe he LP crystal opton saves power A set of consgraton Disa used te select varieusopions 74 Configuration Bite Contawaion bits can be programmed to select “Secon of the oscil type. and one Sts the Ppotecion bes (Rgue 7-1 and Fgue7.2) tr me Prowsces,” PICISCREA, PICT8CeE, PICIECRES, PICIBCRR, and PICTOCRSS covens TP oF ROM voes nave te cesar consguaten rogrammed athe fciory and these parts ae ested fcrordngly (cee, Produc! enbieaton Sytem” ‘Uapraa ne back os datasheet) PICI6CRS4A/CS4BICRSABICEACICREACICSEAICSGAICRSGAICE7C! Raps ess FIGURE 7-1: CONFIGURATION WORD FOR ‘CRSTBICRSTCICSSBICREEAICREGB ose raccion ot 0 Cage procter oF bt 10: FOSG1F08C0: Osler session bis Nate 1 Reframe PICTsCEx egarmngSpectetnn ane Numb! CEI de ris ono asses ine comauson vor 11886 cep Tesrcay ne Preliminary Dssnesis page PIC16C5X FIGURE 7-2: CONFIGURATION WORD FOR PICT6CS2/CS4ICS4AICSSICSEICSTICEZA, S014 Unimplemered Read 20 bt 2 WHTE atncog tes ena tot implemented on PIC5C52) bt 10 FOScHFOsCR: Cetierslcton is! Ne 1 Reto ACNSC8X orang Spectators (ene Nuroe S300 ce 2 eet spore ana osc o Pictish nooene Rea el Doses ane 22 Preliminary 7 o90 urea Temagy ne PIC16C5X 72 Oscilator Configurations 721 OSCILLATOR TPES PICYBCEXs can be operated in our fret oir modes, The user ean progam two consauation Bs (Fose Festa) to select ane of nase fou made + LP Low Power Cosa © XT CeysiatResenator HS High Spe CrystatResonator 1 RC ResstoCapacor pas See Section 71 RESONATORS 10 XT. LP or HS modes, a crystal or ceramic rescnato: 4 connected he OSCIICLAN ang OSCDICLKOUT gine. to esahish celia (Figure 7-3) The ErCystex ein dosgn rogues te vee of § paral cutental Use of series acral may ave Speatcaions. When ie XT, UP or HS ides, te [OSCTICLKIN pin gure). FIGURE 7-3: CRYSTAL OPERATION (OR CERAMIC RESONATOR) (HS. XT OR LP O8C_ CONFIGURATION) FIGURET-4: EXTERNAL CLOCK INPUT (OPERATION (HS, XTOR LP (OSC CONFIGURATION) oven =—fosca TABLE 71: CAPACITOR SELECTION FOR CERAMIC RESONATORS = PICY6CBX, PIC16CREX (se [Resonator] Cap. Range | Cap. Range Tyee Fea | ot xT | desnez | Zope | anT00gF Zone | 158apr | “tesa Somme | tesspr | tees. HS | somme | issepF | teeao ssoure | 10229 | 10225 ote: Thase vatuey ae tor design ganee only ‘erst, the user should coneult the reso- sor mana fraepropie ates CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR -PICTOCBX, PICTOCREX TABLE 7. ‘ah = 1010) <=] = eee osed Pee zoone |_issope_| tava iT fo %T] 100 He | 15-309] 200-200 oF cm a zooK2 | 15.20pF | 100.200 pF 2 seasons fe) may be feted tr gue | tee | eGo ae Most oe He ae 2 Ri vandewintn ayaa cee (apo anne | 5200F | asauer zoure |_1s209r | 152056 Wee T Forvoo= <6 C1=c2=200F 2: These vals arr design guidance on XT mode fo av sersnong ental lewd lal pecteaton Snes each Ccyalhas ts oun emaracorstes, he user ‘Sol corse cysts manctactres fr aoerconate vies of enteral components Note: W you change Wom tis devise wo ‘another device please verily esclator tharacersis In your application 11886 cep Tesrcay ne Preliminary poe) PIC16C5X ciRcurr “ Eimer 2 prepacages oscil ora simple oscilater reat wih TTL gates can be used as an edetnal ysis osclatr cveut Prepacaged ose provide a wee optaing range aod beter sabity A Mel-desgned crystal celltr tl prond 9000 Derormance wit TTL gates. Two (pes of c¥sal busta cuts can be vest one wth pal Fgue7.5 stows implementaten of 2. pate! fesonanteaclaercecut The erat designed to Use te fundamental Fequercy ofthe crystal The ‘4AS34 ierter parts the fo0-depes pase shit that paral oecistrrequeee The 47 kd ester Drovies the negate feedback for tabi, The 10 2 FIGURE 7-6: EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT (USING X7, HS OR LP OSCILLATOR MODE) Note” if you change fom this devs te This ere also desgned io use the fundamental trequeney of the arya The verter porarms. 2 180 degice chase shit ina svies resonant osiltor rout The S00 restore pouse the negate feedback obins tne ivertersnther nea rein FIGURE 7.6: EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT (USING XT, HS OR LP. OSCILLATOR MODE) Ls faked Nels! W you change tom tis device @| nother device, please verity oxi characteristissn your appleston. 724 RCOSCILATOR For timing insensitive appicatons, the RC dence ‘ston fers adonal cos saungs The RC osclator freqengy #8 tinction of the spp wokage, the resrtor (Rem) and caractor (Cod) wes, and te Sparing empatute In aslon ois, he ober process paraneervaraten. Furhermers, he [Sterence nie tame capactance between packape ‘ypes. wil abo atoct the osclanen eqveny epecinly forme Com valoes, The user nso needs fake no account anton de fa erence of era 2.2 KO the oscilator operation may become unstable ‘sop compte For vey high Rot ako (Gg, 1G) me oscar becomes sense to noe, humaey and leakage, Tho, we recommend Keepng Rost between 3) ard 00 ka ‘unaugh the oscar wal operate wah no esta capac (Cent =O 9) we recommend vang wakes ‘Stove 20g foroaee and stable ators Wh nor Smal xtermal cpactance, the esalatonHequency an vey eamatealy coe to changee im ocr apattances, such as PCB vace capactance ot package less tame capsctance Denoasis pape 2 Preliminary 1 388 mean Tesagy ne PIC16C5X ‘The Elecncal_spectestons,sactons shaw RC ‘requeneyvanabon fom part t pat due To normal ‘so, see the Electrical Specicatons sections for ‘ration of oscil frqueney ae to fo guen RextGont values as wel a quency varaton sue © ‘pera tempertre or gem Cans VDD vale ‘The oxiltrfequency, dices ty 4, salle on {he OSc2CLKDUT pin, and can be used fr St purposes or syrcrenize other fai FIGURE 7-7: _RC OSCILLATOR MODE oscac.rour W you change fom tis device v| another device, please verity oslstr haractrss in your applestion, 73. Reset FICIBCEX devices may be reset in ore of the ‘atoung ways + Power(On Reset POR) + RICE reset normal operation) + NICTR wake-up est (tam SLEEP) + WOT reset normal operation) + WOT wake-up eset (rom SLEEP) Table 73 shows these reset condtions fr the PCL and STATUS regters Some rites ae rot fect nary rere condtion ‘The ats ie uno on POR and uncharged any ther reset Most other tegtrs ae tesa 2 ovet state” on PoworOn Resel (POR), CLR or WY veset A HL or WOT wasup trom SLEEP ‘see venutsin a device eset and nota cominuaton of operan befor SLEEP ‘Te TO and PD bis (STATUS <4) ae set or eared depending on the oferet reoet contin (Secien 77) These bis may be used fo determine Tle To ts a ful descrtion of reset states ofa ‘agit igure 7-2 shows 2 simpli Back agian 11886 cep Tesrcay ne Preliminary pamererer) PIC16C5X TABLE 7-3: RESET CONDITIONS FOR SPECIAL REGISTERS Condition Adam ‘sar 08h Power On Reset ‘TABLE 7-4: RESET CONDITIONS FOR ALL REGISTERS FIGURE 7-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Preliminary 7 o90 urea Temagy ne PIC16C5X 74 Power-On Reset POR) ‘The PIGISCRX fm incorporates on-chip Power-On Reset (POR) cxcuy whch proudes an ieral eh reset fr mest powersp stuatons To use tis fate ‘he user metey tes the MCURFF pi io Veo A Sinped ose iagiam of te onchip Power-on Rest oreut showin Figure 18 Timer (Secten 75) crcut ae dowel relates. On pewerup he rset atch is seta the ORT reset ‘The DRT ter bogs eouning once detects HCL sebbenigh Bier the une cut per, when's peal 4@ me, tl reset the vest Itch ana thus end Be cng tenet sg |A power up empl where NTR is not ted to YOO is Shown im igure 7-10. VO ie alowed to res and Sapize before bergng CLR igh The chp vil {ual come out of reset TORT mesc afer TCR in Figue 7-11. the cn-nip Power-on Rese ate Being ised (KICLR and veo are ted Yogete. The ‘You's stable bet ne slat up ter umes out rt ‘hates na petlem m geting a pope’ eset However, Fura -12 depicts» problem stuston where VO ises too sow The tne between hen the ORT {erees 2 hgh on he BETRVPe pn, and wren the CLR Ver pin (and Woo) actualy reach tefl valve, 2 oolong. tue stuaten, when be tarp tne! nde chp a, evtae et guarantees taunt ‘scorn! RC scute be used te sees lenger PO Geiay tes ure 3) ‘Note: When he davee sare narnal operation (ents th fat conden), device opert| Sa cunian Ceag, ee poraure, ets) must be meet to ensue eperaton I these cantons ae not met the device mis be Roi in reset ut operaing codons ae met vihen oe seine. FIGURE T-9: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW \Voo POWER-UP) a] IT + External Pones-On Reset cicitiseavired alps dacargetne capactor gusty when ‘oo poners down FR 40k reconmendes tomake sre hat Vetage atop aioss Rows nl volte he ‘Sever cereal epectieabon Y= 1000 fo 1A velit any cunt ‘owing no EUR omental eapactor © inthe event of OLR pn breakcown ce fo Prtiosiac oscharge (E55)o1 Piss Overseas (EOS). 11886 cep Tesrcay ne Preliminary caer PIC16C5X FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (NCLR NOTTIED TO Voo) FIGURE 7-11: TIME-OUT SEQUENCE ON POWER-UP (NCLR TIED TO Voo): FAST VoD RISE TIME: we 7 wwrenva. Por par FIGURE 7-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO Voo}: SLOW V0 RISE TIME, nea ees guy te Tar reat ages ng oe Yoo na eaced ts fl ae ‘MBESNBE Be epi oat ODE ono Say VA Soa Dsoasis ane 28 Preliminary PIC16C5X 78 Device ResetTimer (ORD ‘The Devce Reset Tener (ORT) provides a fed 18. tera taut on Tenet The GR operates on an mernal RC oscinor The process is Retin RESET ‘long ne DRT fete The ORY day allows apie, resonators requre a caran tie eer power fe {Ssabish a sale oaciloton The amin ORT keeps ‘he dence ma RESET conction fr appronmatey #8 mms afer the volage on te NCLRVEr’ pi has reacted a loi hah (UM) level Ths. external RC etoons comecied ote EUR input are not fequred in mest cases, alowng fer savnge ‘Contsenstve andor space ences appleabone. ‘The Device Reset ime daly wl vary rm aoe to ‘raton See AC parameters er deine ‘The DRT wi also be tegared upon aWatanog Tier fime-ou Ths s parcaly gran! er appleatons Sng te WOT to wate Me PICTSCSX Tort SLEEP mode automaticaly 718 Watchdog Timer (WET not Implemented on PIC16C52 ‘Ta wathog Timer (WOT) is ao runing on-chip RC occiator which dees not require any eternal Components, Tie RO escator = separate fom the Re estat tne OSE ACLKIN pn That mean at ‘he WOT wilran even the doc on the OSCICLAN and OSCZICLROUT pine have been slopped, Tor fxape, by exceuton of @ 11886 cep Tesrcay ne Preliminary pomererer) PIC16C5X FIGURE 7-13: WATCHDOG TIMER BLOCK DIAGRAM TABLE 7-5: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TMER Denoasis pape Preliminary 7 o90 urea Temagy ne PIC16C5X 7 Status Bits (TOPO) The TO ana PD bts inthe STATUS regeter can ce tered to ceermina #3 AESET cordon hae been {aused ty a pover-incondion, a HCE or Watchdog mer (WOT) reset ora CUR Sr WET wakeup rae TABLE 7.6: TOIPD STATUS AFTER RESET TO PD RESET was caused by These STATUS tis are ony afected by events ted table Table 7.9 tats the reset conditions forthe special functon registers, whie Table 7-4 ste the reset Condoons fra he esters 11886 cep Tesrcay ne Preliminary Tease PIC16C5X 7.9 Power-Down Mode (SLEEP) A device may te powered dann (SLEEP) and inter ‘ne PowerOow modes entered by enecaing = PIC16C5X 8.0 INSTRUCTION SET SUMMARY more operance which turer specty the operaton of the mtusion. The PICIGCSEnercten set sora ‘pie 92. goips the netucions to. beard Soren” ard eral and coro! operons ate 8 ‘rows heopde ell cesognors For bporentedinstuctors,Yecresens ae rater designate nad represents 2 estnabon designator The ‘te repstr degra sed spel when one te le eget wie bo ued he mstucson ‘The desinaton designator species whave the rut ofthe operation it be placed I's i". he routs Siaces tne W register ra 6: te ess placed mie le epster spesied nthe inscton Fer botieted instructions, represents a bt te (STATUS-6 8) = PCH109 O= Pose> PIC16C5X conr Complement syne avai} pends: 1 operation) (det Satis Atecied 2 neon PIC16C5X Inoremantt PIC16C5X Move mover pends: a 1 pe (es Sis AtoZ Eneoorg Preliminary PIC16C5X OPTION Load OPTION Register PIC16C5X sucer per: peaton Enter SLEEP Mose [beh steer oon — wor. WOT prescke, PIC16C5X SWAPF Swap Nibbles inf PIC16C5X NoTEs: PIC16C5X 9.0 DEVELOPMENT SUPPORT A Development Toole ‘The Picmicro™ microcontrollers are supported with 2 {Ur range of narguare and sofware covlopment PICMASTER™/PICMASTER CE Real-Time PICSTART” Plus Entry-Level Prsoype + PICDEM2 Lon-Cost Demensaton Board | MPASH Assembler + MPLAB™ Sit Sofcare Sesto MPLAB-C1T (© Comper) + Fuzzy Logie evelooment System (aasyrec-) 92. PICMASTER: High Performance MPLAB IDE ‘The PICMASTER Universal in-Grcut Emustor is itended 1 provde the product deveopment engineer witha complete mérocorvoler design tol se frat PICHASTER ie supped wn he MPLAB™ Integrates Devecprent Enonment (DE), whch atows eating, ‘make snd download, and seus debuaging fom 2 ings enonment Intechangestl aget probes alow the system tobe osy reconhgred for snulston. of arent processors. The unwersal arcectre. of be PICMASTER allows cxparsion 12 supet ll new Miroehip mcocontoles desgned asa abe emulsion system wih ‘vanced features tat ae general und en ere ‘cershve deveoprant ols The PC conpatble 325, {Bnsngher sch patorm and hice Minow Si emionment were chosen fo best make hese ‘eauies alate fo you, e and user CE comtant version of PCNASTER is availate fr European Union (EU) countes cireut Emulator ICEPIC lw oetn out emustor soon ere Wieroonp PIC 20300 PICTBCSK ad PICTON fansies of 9 OTP merorontolers ICEPIC Is aesiges 10 opeate on PC-compatte ‘machnes ranging fom 205817 through Penium™ IGEPICTetures veal me, nansmusveerulaton, 9.4 PROMATE I: Universal Programmer ‘The PRO MATE I Universal Programmer = a Ubeatred proganmer capable of opeatag ‘Sand-alone mode aa wel as PC-hosted rade PAO UATE Ihe CE compliant ‘Te PRO NATE Il has srosrammabic Yoo and VFF ‘Hepler whch stows o very programmed memory ‘VoD in Yoo max fr mani ray has 20150 sly ang rer mena te ‘sssey to suport vafcus package pes n tae ‘Sone moe the PRO WATE Ilcan saad, enty or Progam PCIzOK Pictscoe0, FICTECEX, PIe18c200 and FICTTOXX devices can a0 seh 95° PICSTARTPlus Entry Level Development System ‘he PICSTART programmer = an_aasy-iours low-cost protaype programmer itconect othe PC Va one ofthe COM (RS-222) ports MPLAB Iegrated Development Environment cote makes veg the progame simple and efcent PICSTART Pus hat ecommended fy poducbon prograrming PICSTART Pus supports al PIC 1203004, PIC4C000, PIGHECSX, PCTECAXX and PIG! 7OXX. ‘deces th ip to 40 pins Larger pn count sees ‘ich asthe PICIBC329, PICTECS and PICTTCTSS tray pe suspores win an soaoter octet PICSTART Plas is CE comolont 11886 cep Tesrcay ne Preliminary DSonAeIS panes PIC16C5X 98 PICDEM-tLen-CostPicmicro. Demonstration Board ‘ne PICDENN- ea amele bears wnicn demote the capabities of) several of ierocnps Iescorrolers The micocontolers supporied ate Plotseax (Pletecse to Plctaceaa), PIcvecet Plotos2x. PICTOCT!, ICTOOEX, PICHTCAZ {and Software is included to run basic demo programs ‘he cers can program the sample mcrocotolere Drovideg withthe PICDENI board. on a PRO NATE I or PIESTART-Plis programmer and asi test frmerare. The user can also comet the fownioad the terwate 12 te enulator fr texteg ‘Additonal proetype area ie avail forthe user 12 mmicocorvlersocat() Some oft eaures include Sn RS-222 orcs, 2 polomtometor for smulted ‘ralog pst pusnutlon swicnes and est LEDS oonecad io PORTE 9.7 PICDEM-2.Low-Gost PICIECKX. Demonstration Board The PICDENA2 is a simle ceronstaton board that pports the FICI6C62. PICTECON. PICTECOE, PrCrecro and PICISCT« micocontolers. Al the necessary hardware ane stare neuded to fun the base demenstaon programs. The use Sin tw PICDEAE boars, on 3 PRO UATE prosrammer or PICSTARTPLe, ana cay test frmate The PICMASTER emutor may 20 be Used wih the PICDEW.2 bone to test fare ‘Asouora poioype area nas been proce othe User for ading abana hardware ond eamnectg te tne merocanoter sockets) Some o the atures include 8 R23? mteace push-baton swiehes. & Dotontomster fr smulaee song np > Sera) EEPROM fo demonstate usoge of the EO bus and feparato headers fr eonnecbon fan LCD mele sr akeypas oe Demonstration Board ‘he PIGDEMS is 2 simle denonsvaton board hat depots hs PICTACEZS and PTE nna PLC package til aso support future pin PLCC. necessary hardware and software ve laded fo fun he base demonstration programs. The user an progiam the samsle mcrocontolers povided wath the. PICDEM.3 boara, en # PRO VATE I programmer or PICSTART Fis wih an adepler ocr and easiy est frmwate The PICMASTER: matory aso be used with he PICDEW.S board tees timate Addionalprtsype area hat been Prowded tote user for ading. Marae and anmecing& tothe miracotoly socks) Same of ihe. fates incase an S232. mora, ush-uton sienes, a potertometr tor mulated Balog input, a thermistor and separate headers lee onnacton to sn external Le mule spa 8 Kayes ‘so proved on the PICDEMSS Soar! is an LOD Pavel tm commons and 12 segments ha = apate of paying ie, lempeetre and iy ofthe ‘tetce ana Wiaidone 31 sofware fr soning the ‘Semunplaad LCD senate an 2 PC. simple Seal ‘emutploar rhe LOD signals. 9.9 MPLAB™ Integrated Development Environment Software enlopment previous unseen in te St rietecontroler mavset MPLA fe'8 window G28e9 oseaton which conaine + Atul eared eotor 1 Thee operating moses + Aproget manager + Custamzabie tool bar and kay mapping 1 A sats bash poet rman 1 Extensive onne help VPLS alows you + Eat your source les (ether secemby oF) + One ouch assemble er compile) and dawnload fo Piomer tons (automaticaly urdates projet intrmavon) + Debug eg bso Int fle + Tanto data dynamealy va ODE (con to be repacedby OLE) + Run ups our emulatrs one same PC The ability to use MPLAB wih crochi's smuatoe ows 2 Content ator and the aly 10 easly ich fo the lew eos snr ote ul featured morn minima ang oe ent 9.10 Assembler (MPASM The MPASM Universal Macro Assembler is a PCrosted symbole atsemtier “ksupperts Iizecontoter seres incudng the PICTICSNX PASM eters tul featured Macro capabines, fonaona assendty, ans several source and ising formate t generics vanous ouject cogs format 12 Support Mireche's deveopment eos aswel 2s nd pay praia. oasis anes Preliminary 1 388 mean Tesagy ne PIC16C5X PASM slows tut symbote debugging tom PICHASTER Mirechi’s Unnereal Emus System PASM nas the folowing teaues 0 assst evelopag sotare for speiic use applicators bec codefer a Mich mocontclers + Nace assenbiy capably + Produces al the les (hie. Listing Smo, Sn sci equred for symboke deb ur Merostips eraser sets ‘Supports Ho (deat) Decimal and Octal source ana sing formats. \VPASW seosdes rich dete language fe support programming ote Plemica Dvectves seh making the cevelopment of your asemble source 8.41 Software Simulator (MPLAB-SIM) evelopment a a PC hast enwonment I alows te ‘nan astucton level On ary gen instante ser may examine or meaty any ofthe da areas Drovde external ‘simus to ary! the pins Toe ‘recuton can be permed in singe step, Secie LUPLAB-SIM fulysuppotssymboke debugging useg JUPLAB-C ane MPASH. The Sofware Simulator are ‘he low cost fexbily te develop and” debug cote ‘side of the labotory envrormert making f 37 xcolent mutsroject sate development C0 9.42 ¢.Compiler (MPLAB-C17) ‘The MPLAB-C Code Development System fe 3 completa C'compler and Inegatod cevlopment Sruonment fr licrocnps PICTON samy of merocontolers. The compler proves, poverul magiaton capabiles and ease of use nat und wih For easer souce level debugging, the conpier frosdessytelnfoction that compat wih be PLAS DE memory epay 43 Fuzzy Logie Development system. (uszyTECH.MP| fuzzytECHMF tzzy late devlopment tools ‘yaista te versene a lov east nteguctery orton MP Esser fr designers (2 a3 Comprehenehe woreng krowteage of izzy loge System design and 2 fulseared verso, fassyTEGHie Edton ‘or mplemening more compen systems, Both versions inckide Micoch's_fascy.A™ ‘ernstaon board tr nande-on expenence wih ‘izzy loge systems mplementaton Generator MPDeveWay is an easytouse Windows-based Aleston Cade Ganertr With M-OriveWay You cat wevaly conigreal he perpherals ra PICmere (devce sna wna ce ofa muse, generate al he Inialeton and many funebonl code modes in © language "The “supa uly compatible. wih Merhps MPLAB-C C complet The code peduced ‘= higsy modular and sens eacyimtgrsbon of your fem code. lP-DrieWay is iteligen! enon to Imantsn your code. trough subseqven Code 9.15 SEEVAL” Evaluation and Programming System ‘Tog SEEVAL SEEPRON Designers Kt supports a Lerocnp 2re and re Sonal EEPROM. The kt Ineides everithng necesary to ree, wie ease ot Droge spect! aura of ary Merochp SEEPREM oduct eeluing Smart Senias” and sec seas ade of anass and elablty cleans The total ‘econ sigricanoy reduce be to-markat ard resutn sn optmaed ssn 9.16 KeELog” Evaluation: Programming Tools KeeLoa evaluation and grogramming tools suppoct ierocnpe HCS. Secure Data erogvcts The HS brauston et neues an LCD aeplsy 19 chow ‘hanging codes" decoder fo decode aemissons and 3) proyamming nfrfce to. roam. est 11886 cep Tesrcay ne Preliminary DesnAeS panes Got eesoesa Aeuumaid un AMopunes dueacineesh « EMULATOR PRODUCTS Inheet Emaltr v v NPLAB™ICE imereortrmacr | ¥ ‘SOFTWARE PRODUCTS Enact v Fay Logie. Toa PROGRAMMERS Ure Dow v ‘DEMO BOARDS eves eateyt AHQONOIN Wows STOOL INaNAOTAAIG XS99LDId Pict6cs2 PIC16C5X 10.0 ELECTRICAL CHARACTERISTICS - PIC16¢52 Abeolute Maximum Ratingst amet Temperature under Bias -sect+as0 storage Temperature “BC 10 +1500 ‘vonage on ao win respect to Vs oviewsv votage on CLR weh respecte Vis ove +av Vota on al ote ins wth respect to Vis “OBV (veo +D6V) ‘Total Power Dssipaon™ 00 mw Mae Curent out of Ves 0 160.8 vax Curent into Veo pn koma a Curent into an input pn TOGK On). 0 <8 Input Clamp Current. ik (<0 or = Yoo) ma ‘put Clamp Gurren, Ix Wo < Oro Woe) ma ae Oupu Currant sunk by any UO pin toma ate Ouput Current soueed by ay UO pn toma ae uu Curent sourced ty a singe 10 port (PORTA or 8) toma ae Output Curent sun by a Sng YO par (PORTA 2B) toma Note 1: Pane Disipaton is caleuated as folows Pa 0x (00 § ow + F Von Vou) xt Feu xlu) TOTOE, Sesrs soe oes ina urd Maury Rage nay cau parvanr danageto deve Ths inthe operator lsings ofthe specication 1 hol pled Exposure to maumum fang condians br ended atods may afet dence rls 11886 cep Tesrcay ne Preliminary porvererers| PIC16C5X Pict6cs2 Pics6¢82-04 (Commercial) ic 16¢52-04 industrial ‘Standard Operating Conatons (unless otherwise specie (De characteriaties Operating lemperare. OC = Tas +70 (commerea) Power Suppty Pins “AOC 2 TAS 195°C indo) Characteristic ym | min | wo | tax | Unis Conditions vor | — | 18 | — | V [Device SLEEP Mage supe Curren mo || [ss | a sav nave os | 2| om These paradise chavaclied bl notiesed Nite 5 ‘ata inthe Types he") clu i aeedoncharacterzaton resus t 25°C. The data fr dein tance tony ands ol tetod $e ln owe Voo can be award in SLEEP made winoutosng RAM data, ‘he smi evens manly a uncton of fe operat vliage and requency lhe actors such a bus leat oxctater ype bus ate, ena cose exceson pater, and temperaue so Rave an pact oa 3) The test condton fora 00 measurements in aciv operation mod 16 ‘OSC1 = external square ve, fom raovall al VO pn states. pled > Vie TOCK! = ee, HETR = vee For standoy corret measurements the canons are the same, excep that For RC opton, does ot nue carer tough Ret Te cent hough the restr canbe estimated by the formula n= VoDaRet a} win Rent rmoasured wih me parm SLEEP mose, wih all/O pis m n-mpedance sate andtedt9 VEO ana VS, ‘Dsoasis ane so Preliminary 7 o90 urea Temagy ne Pict6cs2 PIC16C5X 1c18c52-04 (Commercial) PIC16¢62-b industria be charscteristice Seanad Opening ences les ether spc) soe Operating lenperaie OCS Tas +70 commer Sacer -A0-G-2 Tas ¥85°C Gnd) Powe: Suopy Pi Operating Vonage ven ranges descibedin Sacon 101 ‘Characteristic Sym [min [Typ [won| Unite Cention Input Low Vorage ve = woperts ves | = | o2vec |v |ematnimpedance CER Gent ro9er) ves | = | otsvio| v ‘Tock Senn Tage) vss | — | o1svoo | v (OSC (Schmit nage ves | = | otsvee | v- |acosten ent, vee | = | bbb | ¥ [xr opton Input High Votage vw = wopene oasvoo | = | vos |v |reranvect 20 | — | voo | v |soveVoosssv™ IER Senn Tg) oasvoo | — | veo | v ‘Tock (Senn Tage) oasvoo | — | vo | v (O8¢1 (Schmit nage basvoo | — | vio |v {Ret optan ony ovo — | van | V |xTepton Hysresis of Schmit | vino oisveos) || Input Leakage Current | For voo=85¥ vopers os | +1 | oa |vensveneveo, occ + cx [vem vaseo25v ‘Tock sos | | fk \eesven

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